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arm: k3: Enable instruction cache for main domain SPL

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Change spl_enable_dcache so it also enable icache on SPL
initialization for the main domain part of the boot flow. This
improves bootloader booting time.

Link: https://lore.kernel.org/all/20231109140958.1093235-1-joao.goncalves@toradex.com/
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Tested-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Joao Paulo Goncalves 2023-11-13 16:07:21 -03:00 committed by Tom Rini
parent 7fea353686
commit 52a86e69e2
6 changed files with 7 additions and 7 deletions
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2
arch/arm/mach-k3/am625_init.c
View File

@ -209,7 +209,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
}
spl_enable_dcache();
spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

2
arch/arm/mach-k3/am654_init.c
View File

@ -258,7 +258,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_dcache();
spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

4
arch/arm/mach-k3/common.c
View File

@ -521,7 +521,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
}
}
void spl_enable_dcache(void)
void spl_enable_cache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
@ -542,7 +542,7 @@ void spl_enable_dcache(void)
gd->arch.tlb_addr + gd->arch.tlb_size);
gd->relocaddr = gd->arch.tlb_addr;
dcache_enable();
enable_caches();
#endif
}

2
arch/arm/mach-k3/common.h
View File

@ -37,7 +37,7 @@ void disable_linefill_optimization(void);
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
void spl_enable_dcache(void);
void spl_enable_cache(void);
void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);

2
arch/arm/mach-k3/j721e_init.c
View File

@ -286,7 +286,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_dcache();
spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

2
arch/arm/mach-k3/j721s2_init.c
View File

@ -231,7 +231,7 @@ void k3_mem_init(void)
if (ret)
panic("DRAM 1 init failed: %d\n", ret);
}
spl_enable_dcache();
spl_enable_cache();
}
/* Support for the various EVM / SK families */