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u-boot-imx-20190612

Browse Source 
--------------------
 
 - Board fixes:
 	- imx6logic
 	- wandboard
 	- mx6sabre boots again
 	- imx8qm_mek
 	- pico-* boards
 	- Toradex apalis / colibri
 	- engicam imx6 (environment)
 	- KP MX53
 	- opos6ul
 - Switch to DM:
 	- vining2000
 	- dh MX6
 	- Toradex colibri i.MX7
 	- Novena
 - Security : fix CSF size for HAB
 - Other:
       - imx: fix building for i.mx8 without spl
       - pcie and switch to DM
 
       mx6sabreauto: Enable SPL SDP support
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Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imx

u-boot-imx-20190612
--------------------

- Board fixes:
	- imx6logic
	- wandboard
	- mx6sabre boots again
	- imx8qm_mek
	- pico-* boards
	- Toradex apalis / colibri
	- engicam imx6 (environment)
	- KP MX53
	- opos6ul
- Switch to DM:
	- vining2000
	- dh MX6
	- Toradex colibri i.MX7
	- Novena
- Security : fix CSF size for HAB
- Other:
      - imx: fix building for i.mx8 without spl
      - pcie and switch to DM

      mx6sabreauto: Enable SPL SDP support
This commit is contained in:
Tom Rini 2019-06-11 13:41:24 -04:00
commit 529faf80c3
127 changed files with 5945 additions and 1257 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Kconfig
View File

@ -138,6 +138,8 @@ config SYS_MALLOC_F_LEN
depends on SYS_MALLOC_F
default 0x1000 if AM33XX
default 0x2800 if SANDBOX
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5)
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,

1
MAINTAINERS
View File

@ -157,6 +157,7 @@ T: git git://git.denx.de/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/vf610/
F: arch/arm/dts/*imx*
F: arch/arm/mach-imx/
F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/

4
Makefile
View File

@ -1087,6 +1087,10 @@ endif
u-boot.bin: u-boot-fit-dtb.bin FORCE
$(call if_changed,copy)
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)
else ifeq ($(CONFIG_OF_SEPARATE),y)
u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
$(call if_changed,cat)

15
arch/arm/dts/Makefile
View File

@ -540,7 +540,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
dtb-$(CONFIG_MX6Q) += \
imx6-apalis.dtb \
imx6q-display5.dtb \
imx6q-logicpd.dtb
imx6q-logicpd.dtb \
imx6q-novena.dtb
dtb-$(CONFIG_TARGET_TBS2910) += \
imx6q-tbs2910.dtb
@ -570,7 +571,8 @@ dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
dtb-$(CONFIG_MX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb.dtb
imx6sx-sdb.dtb \
imx6sx-softing-vining-2000.dtb
dtb-$(CONFIG_MX6UL) += \
imx6ul-geam.dtb \
@ -588,10 +590,13 @@ dtb-$(CONFIG_MX6UL) += \
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
imx6ull-phycore-segin.dtb \
imx6ull-dart-6ul.dtb
dtb-$(CONFIG_ARCH_MX6) += \
imx6-colibri.dtb
imx6-apalis.dtb \
imx6-colibri.dtb \
imx6q-dhcom-pdk2.dtb
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
@ -605,8 +610,10 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-mek.dtb \
fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
fsl-imx8qxp-colibri.dtb \
fsl-imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb

128
arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi Normal file
View File

@ -0,0 +1,128 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 Toradex AG
*/
&mu {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&pd_lsio {
u-boot,dm-spl;
};
&pd_lsio_gpio0 {
u-boot,dm-spl;
};
&pd_lsio_gpio1 {
u-boot,dm-spl;
};
&pd_lsio_gpio2 {
u-boot,dm-spl;
};
&pd_lsio_gpio3 {
u-boot,dm-spl;
};
&pd_lsio_gpio4 {
u-boot,dm-spl;
};
&pd_lsio_gpio5 {
u-boot,dm-spl;
};
&pd_lsio_gpio6 {
u-boot,dm-spl;
};
&pd_lsio_gpio7 {
u-boot,dm-spl;
};
&pd_conn {
u-boot,dm-spl;
};
&pd_conn_sdch0 {
u-boot,dm-spl;
};
&pd_conn_sdch1 {
u-boot,dm-spl;
};
&pd_conn_sdch2 {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpio6 {
u-boot,dm-spl;
};
&gpio7 {
u-boot,dm-spl;
};
&lpuart0 {
u-boot,dm-spl;
};
&lpuart1 {
u-boot,dm-spl;
};
&lpuart2 {
u-boot,dm-spl;
};
&lpuart3 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};

615
arch/arm/dts/fsl-imx8qm-apalis.dts Normal file
View File

@ -0,0 +1,615 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2017-2019 Toradex
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/memreserve/ 0x80000000 0x00020000;
#include "fsl-imx8qm.dtsi"
#include "fsl-imx8qm-apalis-u-boot.dtsi"
/ {
model = "Toradex Apalis iMX8QM";
compatible = "toradex,apalis-imx8qm", "fsl,imx8qm";
chosen {
bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
stdout-path = &lpuart1;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
<&pinctrl_gpio12>, <&pinctrl_gpio34>, <&pinctrl_gpio56>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_gpio_bkl_on>,
<&pinctrl_gpio_keys>, <&pinctrl_gpio_pwm0>,
<&pinctrl_gpio_pwm1>, <&pinctrl_gpio_pwm2>,
<&pinctrl_gpio_pwm3>, <&pinctrl_gpio_pwm_bkl>,
<&pinctrl_gpio_usbh_en>, <&pinctrl_gpio_usbh_oc_n>,
<&pinctrl_gpio_usbo1_en>, <&pinctrl_gpio_usbo1_oc_n>,
<&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>,
<&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>,
<&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>,
<&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
<&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
apalis-imx8qm {
pinctrl_gpio12: gpio12grp {
fsl,pins = <
/* Apalis GPIO1 */
SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021
/* Apalis GPIO2 */
SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021
>;
};
pinctrl_gpio34: gpio34grp {
fsl,pins = <
/* Apalis GPIO3 */
SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021
/* Apalis GPIO4 */
SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021
>;
};
pinctrl_gpio56: gpio56grp {
fsl,pins = <
/* Apalis GPIO5 */
SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021
/* Apalis GPIO6 */
SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021
>;
};
pinctrl_gpio7: gpio7 {
fsl,pins = <
/* Apalis GPIO7 */
SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021
>;
};
pinctrl_gpio8: gpio8 {
fsl,pins = <
/* Apalis GPIO8 */
SC_P_MLB_DATA_LSIO_GPIO3_IO28 0x00000021
>;
};
pinctrl_gpio_keys: gpio-keys {
fsl,pins = <
/* Apalis WAKE1_MICO */
SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06000021
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020
/* ETH_RESET# */
SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020
>;
};
pinctrl_gpio_bkl_on: gpio-bkl-on {
fsl,pins = <
/* Apalis BKL_ON */
SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021
>;
};
/* Apalis I2C2 (DDC) */
pinctrl_lpi2c0: lpi2c0grp {
fsl,pins = <
SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022
SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022
>;
};
pinctrl_cam1_gpios: cam1gpiosgrp {
fsl,pins = <
/* Apalis CAM1_D7 */
SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021
/* Apalis CAM1_D6 */
SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021
/* Apalis CAM1_D5 */
SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021
/* Apalis CAM1_D4 */
SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021
/* Apalis CAM1_D3 */
SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021
/* Apalis CAM1_D2 */
SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021
/* Apalis CAM1_D1 */
SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021
/* Apalis CAM1_D0 */
SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021
/* Apalis CAM1_PCLK */
SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021
/* Apalis CAM1_MCLK */
SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021
/* Apalis CAM1_VSYNC */
SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021
/* Apalis CAM1_HSYNC */
SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021
>;
};
pinctrl_dap1_gpios: dap1gpiosgrp {
fsl,pins = <
/* Apalis DAP1_MCLK */
SC_P_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021
/* Apalis DAP1_D_OUT */
SC_P_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021
/* Apalis DAP1_RESET */
SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
/* Apalis DAP1_BIT_CLK */
SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021
/* Apalis DAP1_D_IN */
SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021
/* Apalis DAP1_SYNC */
SC_P_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021
/* Wi-Fi_I2S_EN# */
SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021
>;
};
pinctrl_esai0_gpios: esai0gpiosgrp {
fsl,pins = <
/* Apalis LCD1_G1 */
SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021
/* Apalis LCD1_G2 */
SC_P_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021
>;
};
pinctrl_fec2_gpios: fec2gpiosgrp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
/* Apalis LCD1_R1 */
SC_P_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021
/* Apalis LCD1_R0 */
SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021
/* Apalis LCD1_G0 */
SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021
/* Apalis LCD1_R7 */
SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021
/* Apalis LCD1_DE */
SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021
/* Apalis LCD1_HSYNC */
SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021
/* Apalis LCD1_VSYNC */
SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021
/* Apalis LCD1_PCLK */
SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021
/* Apalis LCD1_R6 */
SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021
/* Apalis LCD1_R5 */
SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021
/* Apalis LCD1_R4 */
SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021
/* Apalis LCD1_R3 */
SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021
/* Apalis LCD1_R2 */
SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021
>;
};
pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio {
fsl,pins = <
/* Apalis TS_2 */
SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021
>;
};
pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
fsl,pins = <
/* Apalis LCD1_G6 */
SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021
/* Apalis LCD1_G7 */
SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021
>;
};
pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
fsl,pins = <
/* Apalis TS_4 */
SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021
>;
};
pinctrl_mlb_gpios: mlbgpiosgrp {
fsl,pins = <
/* Apalis TS_1 */
SC_P_MLB_CLK_LSIO_GPIO3_IO27 0x00000021
>;
};
pinctrl_qspi1a_gpios: qspi1agpiosgrp {
fsl,pins = <
/* Apalis LCD1_B0 */
SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
/* Apalis LCD1_B1 */
SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021
/* Apalis LCD1_B2 */
SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021
/* Apalis LCD1_B3 */
SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021
/* Apalis LCD1_B5 */
SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021
/* Apalis LCD1_B7 */
SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021
/* Apalis LCD1_B4 */
SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021
/* Apalis LCD1_B6 */
SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021
>;
};
pinctrl_sim0_gpios: sim0gpiosgrp {
fsl,pins = <
/* Apalis LCD1_G5 */
SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021
/* Apalis LCD1_G3 */
SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021
/* Apalis TS_5 */
SC_P_SIM0_IO_LSIO_GPIO0_IO02 0x00000021
/* Apalis LCD1_G4 */
SC_P_SIM0_RST_LSIO_GPIO0_IO01 0x00000021
>;
};
pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
fsl,pins = <
/* Apalis TS_6 */
SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021
>;
};
pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
fsl,pins = <
/* Apalis TS_3 */
SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021
>;
};
/* On-module I2C */
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
SC_P_GPT0_CLK_DMA_I2C1_SCL 0x04000020
SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020
>;
};
/* Apalis I2C1 */
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
SC_P_GPT1_CLK_DMA_I2C2_SCL 0x04000020
SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020
>;
};
/* Apalis I2C3 (CAM) */
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
SC_P_SIM0_PD_DMA_I2C3_SCL 0x04000020
SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020
>;
};
/* Apalis UART3 */
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_DMA_UART0_RX 0x06000020
SC_P_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
/* Apalis UART1 */
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
SC_P_UART1_RX_DMA_UART1_RX 0x06000020
SC_P_UART1_TX_DMA_UART1_TX 0x06000020
SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
>;
};
pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
fsl,pins = <
/* Apalis UART1_DTR */
SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021
/* Apalis UART1_DSR */
SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021
/* Apalis UART1_DCD */
SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021
/* Apalis UART1_RI */
SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021
>;
};
/* Apalis UART4 */
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020
SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020
>;
};
/* Apalis UART2 */
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020
SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020
SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020
SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020
>;
};
/* Apalis PWM3 */
pinctrl_gpio_pwm0: gpiopwm0grp {
fsl,pins = <
SC_P_UART0_RTS_B_LSIO_GPIO0_IO22 0x00000021
>;
};
/* Apalis PWM4 */
pinctrl_gpio_pwm1: gpiopwm1grp {
fsl,pins = <
SC_P_UART0_CTS_B_LSIO_GPIO0_IO23 0x00000021
>;
};
/* Apalis PWM1 */
pinctrl_gpio_pwm2: gpiopwm2grp {
fsl,pins = <
SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19 0x00000021
>;
};
/* Apalis PWM2 */
pinctrl_gpio_pwm3: gpiopwm3grp {
fsl,pins = <
SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16 0x00000021
>;
};
/* Apalis BKL1_PWM */
pinctrl_gpio_pwm_bkl: gpiopwmbklgrp {
fsl,pins = <
SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00 0x00000021
>;
};
/* Apalis USBH_EN */
pinctrl_gpio_usbh_en: gpiousbhen {
fsl,pins = <
SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x06000060
>;
};
/* Apalis USBH_OC# */
pinctrl_gpio_usbh_oc_n: gpiousbhocn {
fsl,pins = <
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x06000060
>;
};
/* Apalis USBO1_EN */
pinctrl_gpio_usbo1_en: gpiousbo1en {
fsl,pins = <
SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000060
>;
};
/* Apalis USBO1_OC# */
pinctrl_gpio_usbo1_oc_n: gpiousbo1ocn {
fsl,pins = <
SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x06000060
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_sata1_act: sata1actgrp {
fsl,pins = <
/* Apalis SATA1_ACT# */
SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
>;
};
pinctrl_mmc1_cd: mmc1cdgrp {
fsl,pins = <
/* Apalis MMC1_CD# */
SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021
SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021
SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021
SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021
/* On-module PMIC use */
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_sd1_cd: sd1cdgrp {
fsl,pins = <
/* Apalis SD1_CD# */
SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
/* On-module PMIC use */
SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
fsl,magic-packet;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 11 1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
};
/* Apalis I2C2 (DDC) */
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c0>;
clock-frequency = <100000>;
status = "okay";
};
/* On-module I2C */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
};
/* Apalis I2C1 */
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
};
/* Apalis I2C3 (CAM) */
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
};
/* Apalis UART3 */
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
/* Apalis UART1 */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
/* Apalis UART4 */
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
/* Apalis UART2 */
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* Apalis MMC1 */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
bus-width = <8>;
cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
status = "okay";
};
/* Apalis SD1 */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
bus-width = <4>;
cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
status = "okay";
};

155
arch/arm/dts/fsl-imx8qm.dtsi
View File

@ -22,9 +22,18 @@
ethernet0 = &fec1;
ethernet1 = &fec2;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
serial4 = &lpuart4;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
};
memory@80000000 {
@ -193,9 +202,103 @@
power-domains = <&pd_dma>;
wakeup-irq = <345>;
};
pd_dma_lpuart1: PD_DMA_UART1 {
reg = <SC_R_UART_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <346>;
};
pd_dma_lpuart2: PD_DMA_UART2 {
reg = <SC_R_UART_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <347>;
};
pd_dma_lpuart3: PD_DMA_UART3 {
reg = <SC_R_UART_3>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <348>;
};
pd_dma_lpuart4: PD_DMA_UART4 {
reg = <SC_R_UART_4>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <349>;
};
};
};
i2c0: i2c@5a800000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a800000 0x0 0x4000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C0_CLK>,
<&clk IMX8QM_I2C0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c0>;
status = "disabled";
};
i2c1: i2c@5a810000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a810000 0x0 0x4000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C1_CLK>,
<&clk IMX8QM_I2C1_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c1>;
status = "disabled";
};
i2c2: i2c@5a820000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a820000 0x0 0x4000>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C2_CLK>,
<&clk IMX8QM_I2C2_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c2>;
status = "disabled";
};
i2c3: i2c@5a830000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a830000 0x0 0x4000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C3_CLK>,
<&clk IMX8QM_I2C3_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c3>;
status = "disabled";
};
i2c4: i2c@5a840000 {
compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x0 0x5a840000 0x0 0x4000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QM_I2C4_CLK>,
<&clk IMX8QM_I2C4_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
assigned-clock-rates = <24000000>;
power-domains = <&pd_dma_lpi2c4>;
status = "disabled";
};
gpio0: gpio@5d080000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d080000 0x0 0x10000>;
@ -297,6 +400,58 @@
status = "disabled";
};
lpuart1: serial@5a070000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a070000 0x0 0x1000>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_UART1_CLK>,
<&clk IMX8QM_UART1_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART1_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart1>;
status = "disabled";
};
lpuart2: serial@5a080000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a080000 0x0 0x1000>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_UART2_CLK>,
<&clk IMX8QM_UART2_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART2_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart2>;
status = "disabled";
};
lpuart3: serial@5a090000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a090000 0x0 0x1000>;
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_UART3_CLK>,
<&clk IMX8QM_UART3_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART3_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart3>;
status = "disabled";
};
lpuart4: serial@5a0a0000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a0a0000 0x0 0x1000>;
interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_UART4_CLK>,
<&clk IMX8QM_UART4_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART4_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart4>;
status = "disabled";
};
usdhc1: usdhc@5b010000 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;

117
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi Normal file
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@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 Toradex AG
*/
&{/imx8qx-pm} {
u-boot,dm-spl;
};
&mu {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&pd_lsio {
u-boot,dm-spl;
};
&pd_lsio_gpio0 {
u-boot,dm-spl;
};
&pd_lsio_gpio1 {
u-boot,dm-spl;
};
&pd_lsio_gpio2 {
u-boot,dm-spl;
};
&pd_lsio_gpio3 {
u-boot,dm-spl;
};
&pd_lsio_gpio4 {
u-boot,dm-spl;
};
&pd_lsio_gpio5 {
u-boot,dm-spl;
};
&pd_lsio_gpio6 {
u-boot,dm-spl;
};
&pd_lsio_gpio7 {
u-boot,dm-spl;
};
&pd_conn {
u-boot,dm-spl;
};
&pd_conn_sdch0 {
u-boot,dm-spl;
};
&pd_conn_sdch1 {
u-boot,dm-spl;
};
&pd_conn_sdch2 {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpio6 {
u-boot,dm-spl;
};
&gpio7 {
u-boot,dm-spl;
};
&lpuart3 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};

328
arch/arm/dts/fsl-imx8qxp-colibri.dts Normal file
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@ -0,0 +1,328 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 Toradex AG
*/
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
#include "fsl-imx8qxp-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX8QXP";
compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
chosen {
bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
stdout-path = &lpuart3;
};
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1_reg>;
regulator-name = "usbh_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
colibri-imx8qxp {
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
>;
};
pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
fsl,pins = <
SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */
SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */
SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */
SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */
SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061
>;
};
pinctrl_gpio_bl_on: gpio-bl-on {
fsl,pins = <
SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000040
>;
};
pinctrl_hog0: hog0grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */
>;
};
pinctrl_hog1: hog1grp {
fsl,pins = <
SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */
SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */
SC_P_CSI_D07_CI_PI_D09 0x00000061
SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */
SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */
SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */
SC_P_CSI_D02_CI_PI_D04 0x00000061
SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */
SC_P_CSI_D06_CI_PI_D08 0x00000061
SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */
SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */
SC_P_CSI_D03_CI_PI_D05 0x00000061
SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */
SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */
SC_P_CSI_D00_CI_PI_D02 0x00000061
SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */
SC_P_CSI_D01_CI_PI_D03 0x00000061
SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */
SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */
SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */
SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */
SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */
SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */
SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */
SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */
SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */
SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */
>;
};
pinctrl_hog2: hog2grp {
fsl,pins = <
SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */
SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */
SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */
SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */
>;
};
/* Off Module I2C */
pinctrl_i2c1: i2c1grp {
fsl,pins = <
SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021
SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021
>;
};
/*INT*/
pinctrl_usb3503a: usb3503a-grp {
fsl,pins = <
SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
>;
};
pinctrl_usbc_det: usbc-det {
fsl,pins = <
SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040
>;
};
pinctrl_usbh1_reg: usbh1-reg {
fsl,pins = <
SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lpuart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&fec1 {
phy-handle = <&ethphy0>;
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
reg = <2>;
};
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&usdhc1 {
bus-width = <8>;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
status = "okay";
};
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2015 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "imx6q-dhcom-som.dtsi"
/ {
model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
chosen {
stdout-path = &uart1;
};
clk_ext_audio_codec: clock-codec {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_ext>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c2 {
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
pinctrl_hog: hog-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0
>;
};
pinctrl_audmux_ext: audmux-ext-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_enet_1G: enet-1G-grp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x000b0
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x000b1
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x000b1
>;
};
pinctrl_pcie: pcie-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
>;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&sata {
status = "okay";
};
&usdhc3 {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+)
/*
* Copyright (C) 2015 DH electronics GmbH
* Copyright (C) 2018 Marek Vasut <marex@denx.de>
*/
#include "imx6q.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
mmc0 = &usdhc2;
mmc1 = &usdhc3;
mmc2 = &usdhc4;
mmc3 = &usdhc1;
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_3p3v: regulator-3P3V {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash@0 { /* S25FL116K */
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
m25p,fast-read;
};
};
&ecspi2 {
cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_100M>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
reg = <0>;
max-speed = <100>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
reset-post-delay-us = <1000>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic_hw300>;
reg = <0x3c>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <787500>;
regulator-max-microvolt = <1527272>;
lltc,fb-voltage-divider = <100000 110000>;
regulator-suspend-mem-microvolt = <1040000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1885714>;
regulator-max-microvolt = <3657142>;
lltc,fb-voltage-divider = <100000 28000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <787500>;
regulator-max-microvolt = <1527272>;
lltc,fb-voltage-divider = <100000 110000>;
regulator-suspend-mem-microvolt = <980000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <855571>;
regulator-max-microvolt = <1659291>;
lltc,fb-voltage-divider = <100000 93100>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <3240306>;
regulator-max-microvolt = <3240306>;
lltc,fb-voltage-divider = <102000 29400>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <2484708>;
regulator-max-microvolt = <2484708>;
lltc,fb-voltage-divider = <100000 41200>;
regulator-boot-on;
regulator-always-on;
};
};
};
touchscreen@49 { /* TSC2004 */
compatible = "ti,tsc2004";
reg = <0x49>;
vio-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc2004_hw300>;
interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
status = "disabled";
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
rtc@56 {
compatible = "rv3029c2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_hw300>;
reg = <0x56>;
interrupt-parent = <&gpio7>;
interrupts = <12 2>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_base>;
pinctrl_hog_base: hog-base-grp {
fsl,pins = <
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
>;
};
pinctrl_ecspi2: ecspi2-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
>;
};
pinctrl_enet_100M: enet-100M-grp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
>;
};
pinctrl_flexcan1: flexcan1-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pmic_hw300: pmic-hw300-grp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0
>;
};
pinctrl_rtc_hw300: rtc-hw300-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120B0
>;
};
pinctrl_tsc2004_hw300: tsc2004-hw300-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120B0
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
>;
};
pinctrl_uart4: uart4-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
>;
};
pinctrl_usbh1: usbh1-grp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120B0
>;
};
pinctrl_usbotg: usbotg-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120B0
>;
};
pinctrl_usdhc3: usdhc3-grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120B0
>;
};
pinctrl_usdhc4: usdhc4-grp {
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
>;
};
};
&reg_arm {
vin-supply = <&sw3_reg>;
};
&reg_soc {
vin-supply = <&sw1_reg>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usb_h1_vbus>;
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
dr_mode = "otg";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
fsl,wp-controller;
keep-power-in-suspend;
status = "disabled";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
non-removable;
bus-width = <8>;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};

797
arch/arm/dts/imx6q-novena.dts Normal file
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@ -0,0 +1,797 @@
/*
* Copyright 2015 Sutajio Ko-Usagi PTE LTD
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
/dts-v1/;
#include "imx6q.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Kosagi Novena Dual/Quad";
compatible = "kosagi,imx6q-novena", "fsl,imx6q";
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0>;
};
aliases {
mmc0 = &usdhc3;
mmc1 = &usdhc2;
};
chosen {
stdout-path = &uart2;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 10000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight_novena>;
power-supply = <&reg_lvds_lcd>;
brightness-levels = <0 3 6 12 16 24 32 48 64 96 128 192 255>;
default-brightness-level = <12>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys_novena>;
user-button {
label = "User Button";
gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
lid {
label = "Lid";
gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds_novena>;
heartbeat {
label = "novena:white:panel";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
};
panel: panel {
compatible = "innolux,n133hse-ea1", "simple-panel";
backlight = <&backlight>;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_audio_codec: regulator-audio-codec {
compatible = "regulator-fixed";
regulator-name = "es8328-power";
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <400000>;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_display: regulator-display {
compatible = "regulator-fixed";
regulator-name = "lcd-display-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lvds_lcd: regulator-lvds-lcd {
compatible = "regulator-fixed";
regulator-name = "lcd-lvds-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "pcie-bus-power";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_sata: regulator-sata {
compatible = "regulator-fixed";
regulator-name = "sata-power";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <10000>;
gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
};
sound {
compatible = "fsl,imx-audio-es8328";
model = "imx-audio-es8328";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-amp-supply = <&reg_audio_codec>;
jack-gpio = <&gpio5 15 GPIO_ACTIVE_HIGH>;
audio-routing =
"Speaker", "LOUT2",
"Speaker", "ROUT2",
"Speaker", "audio-amp",
"Headphone", "ROUT1",
"Headphone", "LOUT1",
"LINPUT1", "Mic Jack",
"RINPUT1", "Mic Jack",
"Mic Jack", "Mic Bias";
mux-int-port = <0x1>;
mux-ext-port = <0x3>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_novena>;
status = "okay";
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3_novena>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_novena>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
rxc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
txc-skew-ps = <3000>;
txen-skew-ps = <0>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <3000>;
txd1-skew-ps = <3000>;
txd2-skew-ps = <3000>;
txd3-skew-ps = <3000>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi_novena>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_novena>;
status = "okay";
accel: mma8452@1c {
compatible = "fsl,mma8452";
reg = <0x1c>;
};
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
sbs_battery: bq20z75@b {
compatible = "sbs,sbs-battery";
reg = <0x0b>;
sbs,i2c-retry-count = <50>;
};
touch: stmpe811@44 {
compatible = "st,stmpe811";
reg = <0x44>;
irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_stmpe_novena>;
vio-supply = <&reg_3p3v>;
vcc-supply = <&reg_3p3v>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <1>;
st,touch-det-delay = <2>;
st,settling = <2>;
st,fraction-z = <7>;
st,i-drive = <1>;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_novena>;
status = "okay";
pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
reg_sw1a: sw1a {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
reg_sw1c: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
};
reg_sw2: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_sw3a: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
reg_sw3b: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
reg_sw4: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
reg_swbst: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
regulator-boot-on;
};
reg_snvs: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
reg_vref: vrefddr {
regulator-boot-on;
regulator-always-on;
};
reg_vgen1: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
reg_vgen2: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
reg_vgen3: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
reg_vgen4: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen5: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_vgen6: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_novena>;
status = "okay";
codec: es8328@11 {
compatible = "everest,es8328";
reg = <0x11>;
DVDD-supply = <&reg_audio_codec>;
AVDD-supply = <&reg_audio_codec>;
PVDD-supply = <&reg_audio_codec>;
HPVDD-supply = <&reg_audio_codec>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sound_novena>;
clocks = <&clks IMX6QDL_CLK_CKO1>;
assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
<&clks IMX6QDL_CLK_CKO1_SEL>,
<&clks IMX6QDL_CLK_PLL4_AUDIO>,
<&clks IMX6QDL_CLK_CKO1>;
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>,
<&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>,
<&clks IMX6QDL_CLK_OSC>,
<&clks IMX6QDL_CLK_CKO1_PODF>;
assigned-clock-rates = <0 0 722534400 22579200>;
};
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_novena>;
linux,keymap = <
MATRIX_KEY(1, 1, KEY_CONFIG)
>;
status = "okay";
};
&ldb {
fsl,dual-channel;
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
fsl,panel = <&panel>;
status = "okay";
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_novena>;
reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};
&pwm1 {
status = "okay";
};
&sata {
target-supply = <&reg_sata>;
fsl,transmit-level-mV = <1025>;
fsl,transmit-boost-mdB = <0>;
fsl,transmit-atten-16ths = <8>;
status = "okay";
};
&ssi1 {
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_novena>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_novena>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_novena>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
dr_mode = "otg";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_novena>;
disable-over-current;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_swbst>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_novena>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_novena>;
bus-width = <4>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl_audmux_novena: audmuxgrp-novena {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_backlight_novena: backlightgrp-novena {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b1
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
>;
};
pinctrl_ecspi3_novena: ecspi3grp-novena {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
>;
};
pinctrl_enet_novena: enetgrp-novena {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b028
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b028
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
/* Ethernet reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1
>;
};
pinctrl_fpga_gpio: fpgagpiogrp-novena {
fsl,pins = <
/* FPGA power */
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1
/* Reset */
MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
/* FPGA GPIOs */
MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1
MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1
MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1
MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1
MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1
MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1
MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1
MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1
MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1
>;
};
pinctrl_fpga_eim: fpgaeimgrp-novena {
fsl,pins = <
/* FPGA power */
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b1
/* Reset */
MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
/* FPGA GPIOs */
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0f1
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0f1
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0f1
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0f1
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0f1
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0f1
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0f1
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0f1
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0f1
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0f1
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0f1
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0f1
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0f1
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0f1
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0f1
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0f1
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0f1
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0f1
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0f1
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0f1
MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0f1
MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0f1
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0f1
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0f1
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb0f1
MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0f1
>;
};
pinctrl_gpio_keys_novena: gpiokeysgrp-novena {
fsl,pins = <
/* User button */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
/* PCIe Wakeup */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1f0e0
/* Lid switch */
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
>;
};
pinctrl_hdmi_novena: hdmigrp-novena {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1
>;
};
pinctrl_i2c1_novena: i2c1grp-novena {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2_novena: i2c2grp-novena {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3_novena: i2c3grp-novena {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_kpp_novena: kppgrp-novena {
fsl,pins = <
/* Front panel button */
MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x1b0b1
/* Fake column driver, not connected */
MX6QDL_PAD_KEY_COL1__KEY_COL1 0x1b0b1
>;
};
pinctrl_leds_novena: ledsgrp-novena {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b1
>;
};
pinctrl_pcie_novena: pciegrp-novena {
fsl,pins = <
/* Reset */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1
/* Power On */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
/* Wifi kill */
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1
>;
};
pinctrl_sata_novena: satagrp-novena {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b1
>;
};
pinctrl_senoko_novena: senokogrp-novena {
fsl,pins = <
/* Senoko IRQ line */
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13048
/* Senoko reset line */
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1
>;
};
pinctrl_sound_novena: soundgrp-novena {
fsl,pins = <
/* Audio power regulator */
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1
/* Headphone plug */
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
>;
};
pinctrl_stmpe_novena: stmpegrp-novena {
fsl,pins = <
/* Touchscreen interrupt */
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1
>;
};
pinctrl_uart2_novena: uart2grp-novena {
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3_novena: uart3grp-novena {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4_novena: uart4grp-novena {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg_novena: usbotggrp-novena {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc2_novena: usdhc2grp-novena {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
/* Write protect */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
/* Card detect */
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1
>;
};
pinctrl_usdhc3_novena: usdhc3grp-novena {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
>;
};
};

4
arch/arm/dts/imx6qdl-u-boot.dtsi
View File

@ -4,6 +4,10 @@
*/
/ {
aliases {
usb0 = &usbotg;
};
soc {
u-boot,dm-spl;

578
arch/arm/dts/imx6sx-softing-vining-2000.dts Normal file
View File

@ -0,0 +1,578 @@
/*
* Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"
/ {
model = "Softing VIN|ING 2000";
compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
aliases {
mmc0 = &usdhc4;
mmc1 = &usdhc2;
};
chosen {
stdout-path = &uart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_peri_3v3: regulator-peri_3v3 {
compatible = "regulator-fixed";
regulator-name = "peri_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
pwmleds {
compatible = "pwm-leds";
red {
label = "red";
max-brightness = <255>;
pwms = <&pwm6 0 50000>;
};
green {
label = "green";
max-brightness = <255>;
pwms = <&pwm2 0 50000>;
};
blue {
label = "blue";
max-brightness = <255>;
pwms = <&pwm1 0 50000>;
};
};
};
&adc1 {
vref-supply = <&reg_peri_3v3>;
status = "okay";
};
&cpu0 {
/*
* This board has a shared rail of reg_arm and reg_soc (supplied by
* sw1a_reg) which is modeled below, but still this module behaves
* unstable without higher voltages. Hence, set higher voltages here.
*/
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1175000
198000 1175000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC uV */
996000 1250000
792000 1175000
396000 1175000
198000 1175000
>;
};
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_peri_3v3>;
phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
phy-reset-duration = <5>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet0-phy@0 {
reg = <0>;
max-speed = <100>;
interrupt-parent = <&gpio2>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-supply = <&reg_peri_3v3>;
phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
phy-reset-duration = <5>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet1-phy@0 {
reg = <0>;
max-speed = <100>;
interrupt-parent = <&gpio2>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
proximity: sx9500@28 {
compatible = "semtech,sx9500";
reg = <0x28>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sx9500>;
interrupt-parent = <&gpio2>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
};
pmic: pfuze100@8 {
compatible = "fsl,pfuze200";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1
MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1
MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1
MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9
MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038
/* LAN8720 PHY Reset */
MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0
/* MDIO */
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9
/* IRQ from PHY */
MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0
MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038
/* LAN8720 PHY Reset */
MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0
/* MDIO */
MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9
MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9
/* IRQ from PHY */
MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
/* reset external uC */
MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0
/* IRQ from external uC */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0
/* overcurrent detection */
MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1
MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1
>;
};
pinctrl_pwm1: pwm1grp-1 {
fsl,pins = <
/* blue LED */
MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp-1 {
fsl,pins = <
/* green LED */
MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm6: pwm6grp-1 {
fsl,pins = <
/* red LED */
MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1
>;
};
pinctrl_sx9500: sx9500grp {
fsl,pins = <
/* Reset */
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838
/* IRQ */
MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
fsl,pins = <
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000
MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9
>;
};
pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
fsl,pins = <
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068
>;
};
pinctrl_usdhc4_100mhz: usdhc4-100mhz {
fsl,pins = <
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
>;
};
pinctrl_usdhc4_200mhz: usdhc4-200mhz {
fsl,pins = <
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";
};
&reg_arm {
vin-supply = <&sw1a_reg>;
};
&reg_soc {
vin-supply = <&sw1a_reg>;
};
&snvs_poweroff {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
status = "okay";
};
&usdhc4 {
/* hs200-mode is currently unsupported because Vccq is on 3.1V, but
* not on necessary 1.8V.
*/
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
bus-width = <8>;
keep-power-in-suspend;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};

7
arch/arm/dts/imx6ul-phycore-segin.dts
View File

@ -16,7 +16,8 @@
/dts-v1/;
#include "imx6ul-pcl063.dtsi"
#include "imx6ul.dtsi"
#include "pcl063-common.dtsi"
/ {
model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
@ -24,6 +25,10 @@
"fsl,imx6ul";
};
&gpmi {
status = "okay";
};
&i2c1 {
i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";

2
arch/arm/dts/imx6ull-colibri.dts
View File

@ -220,7 +220,7 @@
/* Colibri USBC */
&usbotg1 {
dr_mode = "otg";
dr_mode = "host";
srp-disable;
hnp-disable;
adp-disable;

70
arch/arm/dts/imx6ull-phycore-segin.dts Normal file
View File

@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "pcl063-common.dtsi"
/ {
model = "Phytec phyBOARD-i.MX6ULL-Segin SBC";
compatible = "phytec,phyboard-imx6ull-segin", "phytec,imx6ull-pcl063",
"fsl,imx6ull";
};
&i2c1 {
i2c_rtc: rtc@68 {
compatible = "microcrystal,rv4162";
reg = <0x68>;
status = "okay";
};
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
};

34
arch/arm/dts/imx6ull-u-boot.dtsi Normal file
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
*/
/ {
soc {
u-boot,dm-spl;
};
};
&aips1 {
u-boot,dm-spl;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};

45
arch/arm/dts/imx7-colibri-emmc.dts
View File

@ -15,11 +15,30 @@
mmc0 = &usdhc3;
mmc1 = &usdhc1;
display1 = &lcdif;
usb0 = &usbotg1; /* required for ums */
};
chosen {
stdout-path = &uart1;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_reg>;
regulator-name = "VCC_USB[1-4]";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
vin-supply = <&reg_5v0>;
};
};
&usdhc3 {
@ -46,4 +65,30 @@
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
};
pinctrl_usbh_reg: gpio-usbh-vbus {
fsl,pins = <
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
>;
};
};
/* Colibri USBC */
&usbotg1 {
/*
* usbotg1 on Colibri iMX7 can function in both host/otg modes.
* Gadget stack currently does not look at this at all while
* the host stack refuses to bind/load if it is not set to host
* (it obviously won't be enumerated during usb start invocation
* if dr_mode = "otg")
*/
dr_mode = "host";
status = "okay";
};
/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};

48
arch/arm/dts/imx7-colibri-rawnand.dts
View File

@ -13,6 +13,28 @@
chosen {
stdout-path = &uart1;
};
aliases {
usb0 = &usbotg1; /* required for ums */
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_reg>;
regulator-name = "VCC_USB[1-4]";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
vin-supply = <&reg_5v0>;
};
};
&gpmi {
@ -43,4 +65,30 @@
MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
>;
};
pinctrl_usbh_reg: gpio-usbh-vbus {
fsl,pins = <
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
>;
};
};
/* Colibri USBC */
&usbotg1 {
/*
* usbotg1 on Colibri iMX7 can function in both host/otg modes.
* Gadget stack currently does not look at this at all while
* the host stack refuses to bind/load if it is not set to host
* (it obviously won't be enumerated during usb start invocation
* if dr_mode = "otg")
*/
dr_mode = "host";
status = "okay";
};
/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};

33
arch/arm/dts/imx6ul-pcl063.dtsi → arch/arm/dts/pcl063-common.dtsi
View File

@ -7,10 +7,6 @@
* Author: Christian Hemp <c.hemp@phytec.de>
*/
/dts-v1/;
#include "imx6ul.dtsi"
/ {
model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
@ -47,7 +43,7 @@
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
@ -99,6 +95,18 @@
status = "okay";
};
&usdhc2 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
@ -170,4 +178,19 @@
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};

637
arch/arm/include/asm/arch-imx/imx-regs.h
View File

@ -1,637 +0,0 @@
#ifndef _IMX_REGS_H
#define _IMX_REGS_H
#define ARCH_MXC
/* ------------------------------------------------------------------------
* Motorola IMX system registers
* ------------------------------------------------------------------------
*
*/
#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
# ifndef __ASSEMBLY__
# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
# define __REG(x) (x)
# define __REG2(x,y) ((x)+(y))
#endif
#define IMX_IO_BASE 0x00200000
/*
* Register BASEs, based on OFFSETs
*
*/
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
#define I2C1_BASE_ADDR (0x17000 + IMX_IO_BASE)
#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
/* Watchdog Registers*/
#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
/* SYSCTRL Registers */
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
/* Chip Select Registers */
#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
/* SDRAM controller registers */
#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
/* PLL registers */
#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
#define CSCR_SPLL_RESTART (1<<22)
#define CSCR_MPLL_RESTART (1<<21)
#define CSCR_SYSTEM_SEL (1<<16)
#define CSCR_BCLK_DIV (0xf<<10)
#define CSCR_MPU_PRESC (1<<15)
#define CSCR_SPEN (1<<1)
#define CSCR_MPEN (1<<0)
#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
/*
* GPIO Module and I/O Multiplexer
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
*/
#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
#define GPIO_PORT_MAX 3
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_MASK (0x3 << 5)
#define GPIO_PORT_SHIFT 5
#define GPIO_PORTA (0<<5)
#define GPIO_PORTB (1<<5)
#define GPIO_PORTC (2<<5)
#define GPIO_PORTD (3<<5)
#define GPIO_OUT (1<<7)
#define GPIO_IN (0<<7)
#define GPIO_PUEN (1<<8)
#define GPIO_PF (0<<9)
#define GPIO_AF (1<<9)
#define GPIO_OCR_SHIFT 10
#define GPIO_OCR_MASK (3<<10)
#define GPIO_AIN (0<<10)
#define GPIO_BIN (1<<10)
#define GPIO_CIN (2<<10)
#define GPIO_DR (3<<10)
#define GPIO_AOUT_SHIFT 12
#define GPIO_AOUT_MASK (3<<12)
#define GPIO_AOUT (0<<12)
#define GPIO_AOUT_ISR (1<<12)
#define GPIO_AOUT_0 (2<<12)
#define GPIO_AOUT_1 (3<<12)
#define GPIO_BOUT_SHIFT 14
#define GPIO_BOUT_MASK (3<<14)
#define GPIO_BOUT (0<<14)
#define GPIO_BOUT_ISR (1<<14)
#define GPIO_BOUT_0 (2<<14)
#define GPIO_BOUT_1 (3<<14)
#define GPIO_GIUS (1<<16)
/* assignements for GPIO alternate/primary functions */
/* FIXME: This list is not completed. The correct directions are
* missing on some (many) pins
*/
#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
/*
* PWM controller
*/
#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */
#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */
#define PWMC_SWR (0x01<<16) /* Software Reset */
#define PWMC_CLKSRC (0x01<<15) /* Clock Source */
#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */
#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */
#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */
#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */
#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */
#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */
#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
/*
* DMA Controller
*/
#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
/* TODO: define DMA_REQ lines */
#define DCR_DRST (1<<1)
#define DCR_DEN (1<<0)
#define DBTOCR_EN (1<<15)
#define DBTOCR_CNT(x) ((x) & 0x7fff )
#define CNTR_CNT(x) ((x) & 0xffffff )
#define CCR_DMOD_LINEAR ( 0x0 << 12 )
#define CCR_DMOD_2D ( 0x1 << 12 )
#define CCR_DMOD_FIFO ( 0x2 << 12 )
#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
#define CCR_SMOD_LINEAR ( 0x0 << 10 )
#define CCR_SMOD_2D ( 0x1 << 10 )
#define CCR_SMOD_FIFO ( 0x2 << 10 )
#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
#define CCR_MDIR_DEC (1<<9)
#define CCR_MSEL_B (1<<8)
#define CCR_DSIZ_32 ( 0x0 << 6 )
#define CCR_DSIZ_8 ( 0x1 << 6 )
#define CCR_DSIZ_16 ( 0x2 << 6 )
#define CCR_SSIZ_32 ( 0x0 << 4 )
#define CCR_SSIZ_8 ( 0x1 << 4 )
#define CCR_SSIZ_16 ( 0x2 << 4 )
#define CCR_REN (1<<3)
#define CCR_RPT (1<<2)
#define CCR_FRC (1<<1)
#define CCR_CEN (1<<0)
#define RTOR_EN (1<<15)
#define RTOR_CLK (1<<14)
#define RTOR_PSC (1<<13)
/*
* LCD Controller
*/
#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
#define SIZE_YMAX(y) ( (y) & 0x1ff )
#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
#define VPW_VPW(x) ( (x) & 0x3ff )
#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
#define CPOS_CC1 (1<<31)
#define CPOS_CC0 (1<<30)
#define CPOS_OP (1<<28)
#define CPOS_CXP(x) (((x) & 3ff) << 16)
#define CPOS_CYP(y) ((y) & 0x1ff)
#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
#define LCWHB_BK_EN (1<<31)
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
#define LCWHB_BD(x) ((x) & 0xff)
#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
#define PCR_TFT (1<<31)
#define PCR_COLOR (1<<30)
#define PCR_PBSIZ_1 (0<<28)
#define PCR_PBSIZ_2 (1<<28)
#define PCR_PBSIZ_4 (2<<28)
#define PCR_PBSIZ_8 (3<<28)
#define PCR_BPIX_1 (0<<25)
#define PCR_BPIX_2 (1<<25)
#define PCR_BPIX_4 (2<<25)
#define PCR_BPIX_8 (3<<25)
#define PCR_BPIX_12 (4<<25)
#define PCR_BPIX_16 (4<<25)
#define PCR_PIXPOL (1<<24)
#define PCR_FLMPOL (1<<23)
#define PCR_LPPOL (1<<22)
#define PCR_CLKPOL (1<<21)
#define PCR_OEPOL (1<<20)
#define PCR_SCLKIDLE (1<<19)
#define PCR_END_SEL (1<<18)
#define PCR_END_BYTE_SWAP (1<<17)
#define PCR_REV_VS (1<<16)
#define PCR_ACD_SEL (1<<15)
#define PCR_ACD(x) (((x) & 0x7f) << 8)
#define PCR_SCLK_SEL (1<<7)
#define PCR_SHARP (1<<6)
#define PCR_PCD(x) ((x) & 0x3f)
#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
#define HCR_H_WAIT_2(x) ((x) & 0xff)
#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
#define VCR_V_WAIT_2(x) ((x) & 0xff)
#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
#define POS_POS(x) ((x) & 1f)
#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
#define LSCR1_GRAY1(x) (((x) & 0xf))
#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
#define PWMR_LDMSK (1<<15)
#define PWMR_SCR1 (1<<10)
#define PWMR_SCR0 (1<<9)
#define PWMR_CC_EN (1<<8)
#define PWMR_PW(x) ((x) & 0xff)
#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
#define DMACR_BURST (1<<31)
#define DMACR_HM(x) (((x) & 0xf) << 16)
#define DMACR_TM(x) ((x) &0xf)
#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
#define RMCR_LCDC_EN (1<<1)
#define RMCR_SELF_REF (1<<0)
#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
#define LCDICR_INT_SYN (1<<2)
#define LCDICR_INT_CON (1)
#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
#define LCDISR_UDR_ERR (1<<3)
#define LCDISR_ERR_RES (1<<2)
#define LCDISR_EOF (1<<1)
#define LCDISR_BOF (1<<0)
/*
* UART Module
*/
#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */
#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */
#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */
#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */
#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */
#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */
#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */
#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */
#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */
#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */
#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */
#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */
#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */
#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */
#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */
#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */
#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */
#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */
#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */
#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */
#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */
#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */
#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */
/* UART Control Register Bit Fields.*/
#define URXD_CHARRDY (1<<15)
#define URXD_ERR (1<<14)
#define URXD_OVRRUN (1<<13)
#define URXD_FRMERR (1<<12)
#define URXD_BRK (1<<11)
#define URXD_PRERR (1<<10)
#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
#define UCR1_IREN (1<<7) /* Infrared interface enable */
#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
#define UCR1_SNDBRK (1<<4) /* Send break */
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
#define UCR1_DOZE (1<<1) /* Doze */
#define UCR1_UARTEN (1<<0) /* UART enabled */
#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
#define UCR2_CTSC (1<<13) /* CTS pin control */
#define UCR2_CTS (1<<12) /* Clear to send */
#define UCR2_ESCEN (1<<11) /* Escape enable */
#define UCR2_PREN (1<<8) /* Parity enable */
#define UCR2_PROE (1<<7) /* Parity odd/even */
#define UCR2_STPB (1<<6) /* Stop */
#define UCR2_WS (1<<5) /* Word size */
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
#define UCR2_TXEN (1<<2) /* Transmitter enabled */
#define UCR2_RXEN (1<<1) /* Receiver enabled */
#define UCR2_SRST (1<<0) /* SW reset */
#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
#define UCR3_PARERREN (1<<12) /* Parity enable */
#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
#define UCR3_DSR (1<<10) /* Data set ready */
#define UCR3_DCD (1<<9) /* Data carrier detect */
#define UCR3_RI (1<<8) /* Ring indicator */
#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
#define UCR3_BPEN (1<<0) /* Preset registers enable */
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
#define UCR4_INVR (1<<9) /* Inverted infrared reception */
#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
#define UCR4_IRSC (1<<5) /* IR special case */
#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
#define USR1_RTSS (1<<14) /* RTS pin status */
#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
#define USR1_RTSD (1<<12) /* RTS delta */
#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
#define USR2_IDLE (1<<12) /* Idle condition */
#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
#define USR2_WAKE (1<<7) /* Wake */
#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
#define USR2_TXDC (1<<3) /* Transmitter complete */
#define USR2_BRCD (1<<2) /* Break condition */
#define USR2_ORE (1<<1) /* Overrun error */
#define USR2_RDR (1<<0) /* Recv data ready */
#define UTS_FRCPERR (1<<13) /* Force parity error */
#define UTS_LOOP (1<<12) /* Loop tx and rx */
#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
#define UTS_TXFULL (1<<4) /* TxFIFO full */
#define UTS_RXFULL (1<<3) /* RxFIFO full */
#define UTS_SOFTRST (1<<0) /* Software reset */
/* General purpose timers registers */
#define TCTL1 __REG(IMX_TIM1_BASE)
#define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
#define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
#define TCR1 __REG(IMX_TIM1_BASE + 0xc)
#define TCN1 __REG(IMX_TIM1_BASE + 0x10)
#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
#define TCTL2 __REG(IMX_TIM2_BASE)
#define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
#define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
#define TCR2 __REG(IMX_TIM2_BASE + 0xc)
#define TCN2 __REG(IMX_TIM2_BASE + 0x10)
#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)
/* General purpose timers bitfields */
#define TCTL_SWR (1<<15) /* Software reset */
#define TCTL_FRR (1<<8) /* Freerun / restart */
#define TCTL_CAP (3<<6) /* Capture Edge */
#define TCTL_OM (1<<5) /* output mode */
#define TCTL_IRQEN (1<<4) /* interrupt enable */
#define TCTL_CLKSOURCE (7<<1) /* Clock source */
#define TCTL_TEN (1) /* Timer enable */
#define TPRER_PRES (0xff) /* Prescale */
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
#endif /* _IMX_REGS_H */

2
arch/arm/include/asm/arch-imx8/imx-regs.h
View File

@ -6,6 +6,8 @@
#ifndef __ASM_ARCH_IMX8_REGS_H__
#define __ASM_ARCH_IMX8_REGS_H__
#define ARCH_MXC
#define LPUART_BASE 0x5A060000
#define GPT1_BASE_ADDR 0x5D140000

2
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -6,6 +6,8 @@
#ifndef __ASM_ARCH_IMX8M_REGS_H__
#define __ASM_ARCH_IMX8M_REGS_H__
#define ARCH_MXC
#include <asm/mach-imx/regs-lcdif.h>
#define ROM_VERSION_A0 0x800

18
arch/arm/include/asm/arch-mx7/clock.h
View File

@ -175,6 +175,24 @@ enum clk_root_index {
CLK_ROOT_MAX,
};
#if (CONFIG_CONS_INDEX == 0)
#define UART_CLK_ROOT UART1_CLK_ROOT
#elif (CONFIG_CONS_INDEX == 1)
#define UART_CLK_ROOT UART2_CLK_ROOT
#elif (CONFIG_CONS_INDEX == 2)
#define UART_CLK_ROOT UART3_CLK_ROOT
#elif (CONFIG_CONS_INDEX == 3)
#define UART_CLK_ROOT UART4_CLK_ROOT
#elif (CONFIG_CONS_INDEX == 4)
#define UART_CLK_ROOT UART5_CLK_ROOT
#elif (CONFIG_CONS_INDEX == 5)
#define UART_CLK_ROOT UART6_CLK_ROOT
#elif (CONFIG_CONS_INDEX == 6)
#define UART_CLK_ROOT UART7_CLK_ROOT
#else
#error "Invalid IMX UART ID for serial console is defined"
#endif
struct clk_root_setting {
enum clk_root_index root;
u32 setting;

2
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
View File

@ -8,6 +8,8 @@
#include <linux/sizes.h>
#define ARCH_MXC
#define CAAM_SEC_SRAM_BASE (0x26000000)
#define CAAM_SEC_SRAM_SIZE (SZ_32K)
#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)

93
arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S Normal file
View File

@ -0,0 +1,93 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#include <config.h>
#define ROM_API_TABLE_BASE_ADDR_LEGACY 0x180
#define ROM_VERSION_OFFSET 0x80
#define ROM_API_HWCNFG_SETUP_OFFSET 0x08
plugin_start:
push {r0-r4, lr}
imx7ulp_ddr_setting
imx7ulp_clock_gating
imx7ulp_qos_setting
normal_boot:
/*
* The following is to fill in those arguments for this ROM function
* pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
* This function is used to copy data from the storage media into DDR.
* start - Initial (possibly partial) image load address on entry.
* Final image load address on exit.
* bytes - Initial (possibly partial) image size on entry.
* Final image size on exit.
* boot_data - Initial @ref ivt Boot Data load address.
*/
adr r0, boot_data2
adr r1, image_len2
adr r2, boot_data2
/*
* check the _pu_irom_api_table for the address
*/
before_calling_rom___pu_irom_hwcnfg_setup:
ldr r3, =ROM_VERSION_OFFSET
ldr r4, [r3]
ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
blx r4
after_calling_rom___pu_irom_hwcnfg_setup:
/*
* To return to ROM from plugin, we need to fill in these argument.
* Here is what need to do:
* Need to construct the parameters for this function before return to ROM:
* plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
*/
pop {r0-r4, lr}
push {r5}
ldr r5, boot_data2
str r5, [r0]
ldr r5, image_len2
str r5, [r1]
ldr r5, second_ivt_offset
str r5, [r2]
mov r0, #1
pop {r5}
/* return back to ROM code */
bx lr
/* make the following data right in the end of the output*/
.ltorg
#define FLASH_OFFSET 0x400
/*
* second_ivt_offset is the offset from the "second_ivt_header" to
* "image_copy_start", which involves FLASH_OFFSET, plus the first
* ivt_header, the plugin code size itself recorded by "ivt2_header"
*/
second_ivt_offset: .long (ivt2_header + 0x2C + FLASH_OFFSET)
/*
* The following is the second IVT header plus the second boot data
*/
ivt2_header: .long 0x0
app2_code_jump_v: .long 0x0
reserv3: .long 0x0
dcd2_ptr: .long 0x0
boot_data2_ptr: .long 0x0
self_ptr2: .long 0x0
app_code_csf2: .long 0x0
reserv4: .long 0x0
boot_data2: .long 0x0
image_len2: .long 0x0
plugin2: .long 0x0

2
arch/arm/mach-imx/Kconfig
View File

@ -29,7 +29,7 @@ config IMX_BOOTAUX
config USE_IMXIMG_PLUGIN
bool "Use imximage plugin code"
depends on ARCH_MX7 || ARCH_MX6
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP
help
i.MX6/7 supports DCD and Plugin. Enable this configuration
to use Plugin, otherwise DCD will be used.

13
arch/arm/mach-imx/Makefile
View File

@ -92,7 +92,9 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
ifeq ($(CONFIG_ARCH_IMX8), y)
CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
IMAGE_TYPE := imx8image
ifeq ($(CONFIG_SPL_BUILD),y)
SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi)
endif
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
@ -110,7 +112,16 @@ u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
$(call if_changed,mkimage)
ifeq ($(CONFIG_OF_SEPARATE),y)
ifeq ($(CONFIG_MULTI_DTB_FIT),y)
MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
-T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE)
u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log
u-boot-dtb.imx: u-boot-fit-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE
ifeq ($(DEPFILE_EXISTS),0)
$(call if_changed,mkimage)
endif
else ifeq ($(CONFIG_OF_SEPARATE),y)
MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
-T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE)
u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log

2
arch/arm/mach-imx/cpu.c
View File

@ -285,7 +285,7 @@ u32 get_ahb_clk(void)
void arch_preboot_os(void)
{
#if defined(CONFIG_PCIE_IMX)
#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
imx_pcie_remove();
#endif
#if defined(CONFIG_SATA)

18
arch/arm/mach-imx/imx8/Kconfig
View File

@ -27,8 +27,13 @@ choice
prompt "i.MX8 board select"
optional
config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
config TARGET_APALIS_IMX8
bool "Support Apalis iMX8 module"
select BOARD_LATE_INIT
select IMX8QM
config TARGET_COLIBRI_IMX8X
bool "Support Colibri iMX8X module"
select BOARD_LATE_INIT
select IMX8QXP
@ -37,9 +42,16 @@ config TARGET_IMX8QM_MEK
select BOARD_LATE_INIT
select IMX8QM
config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BOARD_LATE_INIT
select IMX8QXP
endchoice
source "board/freescale/imx8qxp_mek/Kconfig"
source "board/freescale/imx8qm_mek/Kconfig"
source "board/freescale/imx8qxp_mek/Kconfig"
source "board/toradex/apalis-imx8/Kconfig"
source "board/toradex/colibri-imx8x/Kconfig"
endif

44
arch/arm/mach-imx/imx8/cpu.c
View File

@ -11,6 +11,7 @@
#include <dm/lists.h>
#include <dm/uclass.h>
#include <errno.h>
#include <thermal.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx/cpu.h>
@ -573,15 +574,50 @@ const char *get_core_name(void)
return "?";
}
#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
static int cpu_imx_get_temp(void)
{
struct udevice *thermal_dev;
int cpu_tmp, ret;
ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
&thermal_dev);
if (!ret) {
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
if (ret)
return 0xdeadbeef;
} else {
return 0xdeadbeef;
}
return cpu_tmp;
}
#else
static int cpu_imx_get_temp(void)
{
return 0;
}
#endif
int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
{
struct cpu_imx_platdata *plat = dev_get_platdata(dev);
int ret;
if (size < 100)
return -ENOSPC;
snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
plat->type, plat->rev, plat->name, plat->freq_mhz);
ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
buf = buf + ret;
size = size - ret;
ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
}
snprintf(buf + ret, size - ret, "\n");
return 0;
}
@ -623,8 +659,10 @@ static ulong imx8_get_cpu_rate(void)
{
ulong rate;
int ret;
int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
SC_R_A53 : SC_R_A72;
ret = sc_pm_get_clock_rate(-1, SC_R_A35, SC_PM_CLK_CPU,
ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
(sc_pm_clock_rate_t *)&rate);
if (ret) {
printf("Could not read CPU frequency: %d\n", ret);

18
arch/arm/mach-imx/mx6/Kconfig
View File

@ -455,6 +455,18 @@ config TARGET_PCL063
select DM_THERMAL
select SUPPORT_SPL
config TARGET_PCL063_ULL
bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)"
select MX6ULL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_SERIAL
select DM_THERMAL
select SUPPORT_SPL
config TARGET_SECOMX6
bool "secomx6 boards"
@ -498,8 +510,8 @@ config TARGET_UDOO_NEO
select SUPPORT_SPL
imply CMD_DM
config TARGET_SAMTEC_VINING_2000
bool "samtec VIN|ING 2000"
config TARGET_SOFTING_VINING_2000
bool "Softing VIN|ING 2000"
select BOARD_LATE_INIT
select DM
select DM_THERMAL
@ -580,7 +592,7 @@ source "board/phytec/pfla02/Kconfig"
source "board/phytec/pcl063/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/samtec/vining_2000/Kconfig"
source "board/softing/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"

2
arch/arm/mach-imx/mx6/opos6ul.c
View File

@ -192,6 +192,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refreshes commands per refresh cycle */
};
static struct mx6_ddr3_cfg mem_ddr = {

2
arch/arm/mach-imx/mx7/clock.c
View File

@ -53,7 +53,7 @@ static u32 get_ipg_clk(void)
u32 imx_get_uartclk(void)
{
return get_root_clk(UART1_CLK_ROOT);
return get_root_clk(UART_CLK_ROOT);
}
u32 imx_get_fecclk(void)

43
arch/arm/mach-imx/mx7/soc.c
View File

@ -164,15 +164,6 @@ u32 __weak get_board_rev(void)
}
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* enable all periherial can be accessed in nosec mode */
static void init_csu(void)
{
int i = 0;
for (i = 0; i < CSU_NUM_REGS; i++)
writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
}
static void imx_enet_mdio_fixup(void)
{
struct iomuxc_gpr_base_regs *gpr_regs =
@ -191,6 +182,26 @@ static void imx_enet_mdio_fixup(void)
}
}
static void init_cpu_basic(void)
{
imx_enet_mdio_fixup();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();
#endif
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* enable all periherial can be accessed in nosec mode */
static void init_csu(void)
{
int i = 0;
for (i = 0; i < CSU_NUM_REGS; i++)
writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
}
static void imx_gpcv2_init(void)
{
u32 val, i;
@ -269,12 +280,7 @@ int arch_cpu_init(void)
/* Disable PDE bit of WMCR register */
imx_wdog_disable_powerdown();
imx_enet_mdio_fixup();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();
#endif
init_cpu_basic();
#if CONFIG_IS_ENABLED(IMX_RDC)
isolate_resource();
@ -286,6 +292,13 @@ int arch_cpu_init(void)
return 0;
}
#else
int arch_cpu_init(void)
{
init_cpu_basic();
return 0;
}
#endif
#ifdef CONFIG_ARCH_MISC_INIT

3
board/armadeus/opos6uldev/board.c
View File

@ -3,7 +3,6 @@
* Copyright (C) 2018 Armadeus Systems
*/
#include <asm/arch/clock.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
@ -49,8 +48,6 @@ int setup_lcd(void)
struct gpio_desc backlight;
int ret;
enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Set Brightness to high */

81
board/dhelectronics/dh_imx6/dh_imx6.c
View File

@ -6,6 +6,8 @@
*/
#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
@ -18,6 +20,8 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
#include <ahci.h>
#include <dwc_ahsata.h>
#include <environment.h>
#include <errno.h>
#include <fsl_esdhc.h>
@ -167,6 +171,9 @@ int board_eth_init(bd_t *bis)
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
gpio_request(IMX_GPIO_NR(5, 0), "PHY-reset");
gpio_request(IMX_GPIO_NR(1, 7), "VIO");
setup_fec_clock();
eth_phy_reset();
@ -186,64 +193,10 @@ int board_eth_init(bd_t *bis)
}
#endif
#ifdef CONFIG_FSL_ESDHC
#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 16)
#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 8)
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{ USDHC2_BASE_ADDR },
{ USDHC3_BASE_ADDR },
{ USDHC4_BASE_ADDR },
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
return gpio_get_value(USDHC2_CD_GPIO);
case USDHC3_BASE_ADDR:
return !gpio_get_value(USDHC3_CD_GPIO);
case USDHC4_BASE_ADDR:
return 1; /* eMMC/uSDHC4 is always present */
}
return 0;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 SD interface
* mmc1 micro SD
* mmc2 eMMC
*/
gpio_direction_input(USDHC2_CD_GPIO);
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
gpio_request(IMX_GPIO_NR(3, 31), "USB-VBUS");
/*
* Set daisy chain for otg_pin_id on MX6Q.
* For MX6DL, this bit is reserved.
@ -319,16 +272,6 @@ int board_early_init_f(void)
return 0;
}
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
if (bus == 0 && cs == 0)
return IMX_GPIO_NR(2, 30);
else
return -1;
}
#endif
int board_init(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@ -351,10 +294,6 @@ int board_init(void)
}
#endif
#ifdef CONFIG_SATA
setup_sata();
#endif
setup_dhcom_mac_from_fuse();
return 0;
@ -379,6 +318,10 @@ static int board_get_hwcode(void)
{
int hw_code;
gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
gpio_direction_input(HW_CODE_BIT_0);
gpio_direction_input(HW_CODE_BIT_1);
gpio_direction_input(HW_CODE_BIT_2);

4
board/freescale/imx8mq_evk/spl.c
View File

@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
extern struct dram_timing_info dram_timing_b0;
void spl_dram_init(void)
static void spl_dram_init(void)
{
/* ddr init */
if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
@ -38,7 +38,7 @@ void spl_dram_init(void)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
struct i2c_pads_info i2c_pad_info1 = {
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,

44
board/freescale/mx6sabresd/mx6sabresd.c
View File

@ -287,49 +287,6 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int ret;
int i;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 SD2
* mmc1 SD3
* mmc2 eMMC
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc2_pads);
gpio_request(USDHC2_CD_GPIO, "USDHC2 CD");
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
SETUP_IOMUX_PADS(usdhc3_pads);
gpio_request(USDHC3_CD_GPIO, "USDHC3 CD");
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
#else
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned reg = readl(&psrc->sbmr1) >> 11;
/*
@ -363,7 +320,6 @@ int board_mmc_init(bd_t *bis)
}
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
#endif

77
board/kosagi/novena/novena.c
View File

@ -6,6 +6,9 @@
*/
#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <ahci.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
@ -20,6 +23,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
#include <dwc_ahsata.h>
#include <environment.h>
#include <fsl_esdhc.h>
#include <i2c.h>
@ -35,6 +39,7 @@
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <stdio_dev.h>
#include <video_console.h>
#include "novena.h"
@ -83,6 +88,8 @@ int drv_keyboard_init(void)
.tstc = novena_gpio_button_tstc,
};
gpio_request(NOVENA_BUTTON_GPIO, "button");
error = input_init(&button_input, 0);
if (error) {
debug("%s: Cannot set up input\n", __func__);
@ -99,60 +106,6 @@ int drv_keyboard_init(void)
}
#endif
/*
* SDHC
*/
#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{ USDHC3_BASE_ADDR, 0, 4 }, /* Micro SD */
{ USDHC2_BASE_ADDR, 0, 4 }, /* Big SD */
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
/* There is no CD for a microSD card, assume always present. */
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
return 1;
else
return !gpio_get_value(NOVENA_SD_CD);
}
int board_mmc_getwp(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
/* There is no WP for a microSD card, assume always read-write. */
if (cfg->esdhc_base == USDHC3_BASE_ADDR)
return 0;
else
return gpio_get_value(NOVENA_SD_WP);
}
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int index;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
/* Big SD write-protect and card-detect */
gpio_direction_input(NOVENA_SD_WP);
gpio_direction_input(NOVENA_SD_CD);
for (index = 0; index < ARRAY_SIZE(usdhc_cfg); index++) {
status = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (status)
return status;
}
return status;
}
#endif
int board_early_init_f(void)
{
#if defined(CONFIG_VIDEO_IPUV3)
@ -167,17 +120,25 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SATA
setup_sata();
#endif
return 0;
}
int board_late_init(void)
{
#if defined(CONFIG_VIDEO_IPUV3)
struct udevice *con;
char buf[DISPLAY_OPTIONS_BANNER_LENGTH];
int ret;
setup_display_lvds();
ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con);
if (ret)
return ret;
display_options_get_banner(false, buf, sizeof(buf));
vidconsole_position_cursor(con, 0, 0);
vidconsole_put_string(con, buf);
#endif
return 0;
}

3
board/kosagi/novena/video.c
View File

@ -270,6 +270,7 @@ static void enable_lvds(struct display_info_t const *dev)
return;
/* ITE IT6251 power enable. */
gpio_request(NOVENA_ITE6251_PWR_GPIO, "ite6251-power");
gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
mdelay(10);
gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
@ -447,6 +448,8 @@ void setup_display_lvds(void)
/* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
ret = it6251_init();
if (!ret) {
gpio_request(NOVENA_BACKLIGHT_PWR_GPIO, "backlight-power");
gpio_request(NOVENA_BACKLIGHT_PWM_GPIO, "backlight-pwm");
/* Backlight power enable. */
gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
/* PWM backlight pin, always on for full brightness. */

3
board/logicpd/imx6/imx6logic.c
View File

@ -152,7 +152,8 @@ int board_late_init(void)
if (is_mx6dq()) {
env_set("board_rev", "MX6DQ");
env_set("fdt_file", "imx6q-logicpd.dtb");
if (!env_get("fdt_file"))
env_set("fdt_file", "imx6q-logicpd.dtb");
}
return 0;

13
board/phytec/pcl063/Kconfig
View File

@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
default "pcl063"
endif
if TARGET_PCL063_ULL
config SYS_BOARD
default "pcl063"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "pcl063_ull"
endif

6
board/phytec/pcl063/MAINTAINERS
View File

@ -1,8 +1,14 @@
PCL063 BOARD
M: Martyn Welch <martyn.welch@collabora.com>
M: Parthiban Nallathambi <parthitce@gmail.com>
S: Maintained
F: arch/arm/dts/imx6ul-pcl063.dtsi
F: arch/arm/dts/imx6ul-phycore-segin.dts
F: arch/arm/dts/imx6ull-phycore-segin.dts
F: arch/arm/dts/pcl063-common.dtsi
F: arch/arm/dts/imx6ull-u-boot.dtsi
F: board/phytec/pcl063/
F: configs/phycore_pcl063_defconfig
F: configs/phycore_pcl063_ull_defconfig
F: include/configs/pcl063.h
F: include/configs/pcl063_ull.h

5
board/phytec/pcl063/pcl063.c
View File

@ -200,7 +200,10 @@ int board_init(void)
int checkboard(void)
{
puts("Board: PHYTEC phyCORE-i.MX6UL\n");
u32 cpurev = get_cpu_rev();
printf("Board: PHYTEC phyCORE-i.MX%s\n",
get_imx_type((cpurev & 0xFF000) >> 12));
return 0;
}

74
board/phytec/pcl063/spl.c
View File

@ -13,6 +13,7 @@
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <fsl_esdhc.h>
/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#ifndef CONFIG_NAND_MXS
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#endif
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{
.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4,
},
#ifndef CONFIG_NAND_MXS
{
.esdhc_base = USDHC2_BASE_ADDR,
.max_bus_width = 8,
},
#endif
};
int board_mmc_getcd(struct mmc *mmc)
@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
int i, ret;
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
#ifndef CONFIG_NAND_MXS
case 1:
SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
#endif
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
void board_boot_order(u32 *spl_boot_list)
{
u32 bmode = imx6_src_get_boot_mode();
u8 boot_dev = BOOT_DEVICE_MMC1;
switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
case IMX6_BMODE_SD:
case IMX6_BMODE_ESD:
boot_dev = BOOT_DEVICE_MMC1;
break;
case IMX6_BMODE_MMC:
case IMX6_BMODE_EMMC:
boot_dev = BOOT_DEVICE_MMC2;
break;
default:
/* Default - BOOT_DEVICE_MMC1 */
printf("Wrong board boot order\n");
break;
}
spl_boot_list[0] = boot_dev;
}
#endif /* CONFIG_FSL_ESDHC */
void board_init_f(ulong dummy)

4
board/samtec/vining_2000/Kconfig → board/softing/vining_2000/Kconfig
View File

@ -1,10 +1,10 @@
if TARGET_SAMTEC_VINING_2000
if TARGET_SOFTING_VINING_2000
config SYS_BOARD
default "vining_2000"
config SYS_VENDOR
default "samtec"
default "softing"
config SYS_CONFIG_NAME
default "vining_2000"

4
board/samtec/vining_2000/MAINTAINERS → board/softing/vining_2000/MAINTAINERS
View File

@ -1,6 +1,6 @@
VINING_2000 BOARD
M: Ingo Schroeck <open-source@samtec.de>
M: Silvio Fricke <open-source@softing.de>
S: Maintained
F: board/samtec/vining_2000/
F: board/softing/vining_2000/
F: include/configs/vining_2000.h
F: configs/vining_2000_defconfig

1
board/samtec/vining_2000/Makefile → board/softing/vining_2000/Makefile
View File

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2016 samtec automotive software & electronics gmbh
# Copyright (C) 2017-2019 softing automotive electronics gmbH
obj-y := vining_2000.o

1
board/samtec/vining_2000/imximage.cfg → board/softing/vining_2000/imximage.cfg
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 samtec automotive software & electronics gmbh
* Copyright (C) 2017-2019 softing automotive electronics gmbH
*/
#define __ASSEMBLY__

93
board/samtec/vining_2000/vining_2000.c → board/softing/vining_2000/vining_2000.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 samtec automotive software & electronics gmbh
* Copyright (C) 2017-2019 softing automotive electronics gmbH
*
* Author: Christoph Fritz <chf.fritz@googlemail.com>
*/
@ -57,6 +58,9 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST)
#define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
PAD_CTL_PKE)
@ -67,34 +71,6 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
@ -116,11 +92,6 @@ static iomux_v3_cfg_t const pwm_led_pads[] = {
MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#define PHY_RESET IMX_GPIO_NR(5, 9)
int board_eth_init(bd_t *bis)
@ -152,6 +123,7 @@ int board_eth_init(bd_t *bis)
goto eth_fail;
/* reset phy */
gpio_request(PHY_RESET, "PHY-reset");
gpio_direction_output(PHY_RESET, 0);
mdelay(16);
gpio_set_value(PHY_RESET, 1);
@ -437,66 +409,11 @@ int board_late_init(void)
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_usb();
return 0;
}
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC4_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == USDHC4_BASE_ADDR)
return 1;
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
return !gpio_get_value(USDHC2_CD_GPIO);
return -EINVAL;
}
int board_mmc_init(bd_t *bis)
{
int ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 USDHC4
* mmc1 USDHC2
*/
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
if (ret) {
printf("Warning: failed to initialize USDHC4\n");
return ret;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
if (ret) {
printf("Warning: failed to initialize USDHC2\n");
return ret;
}
return 0;
}
int board_init(void)
{
/* Address of boot parameters */

9
board/technexion/pico-imx6ul/MAINTAINERS
View File

@ -5,13 +5,6 @@ S: Maintained
F: board/technexion/pico-imx6ul/
F: include/configs/pico-imx6ul.h
F: configs/pico-imx6ul_defconfig
TechNexion PICO-HOBBIT-IMX6UL
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: configs/pico-dwarf-imx6ul_defconfig
F: configs/pico-hobbit-imx6ul_defconfig
TechNexion PICO-PI-IMX6UL
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: configs/pico-pi-imx6ul_defconfig

10
board/technexion/pico-imx7d/MAINTAINERS
View File

@ -1,16 +1,10 @@
TechNexion PICO-IMX7D board
M: Vanessa Maegima <vanessa.maegima@nxp.com>
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: board/technexion/pico-imx7d/
F: include/configs/pico-imx7d.h
F: configs/pico-imx7d_defconfig
TechNexion PICO-HOBBIT-IMX7
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: configs/pico-imx7d_bl33_defconfig
F: configs/pico-hobbit-imx7d_defconfig
TechNexion PICO-PI-IMX7
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: configs/pico-pi-imx7d_defconfig

44
board/technexion/pico-imx7d/README.pico-imx7d_BL33 Normal file
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@ -0,0 +1,44 @@
This document describes the instruction to build and flash ATF/OPTEE/U-Boot on
pico-imx7d board. U-Boot is loaded as part of FIP image by ATF in this setup.
The boot sequence is ATF -> OPTEE -> U-Boot -> Linux. U-Boot is in non-secure
world in this case.
- Build u-boot
Set environment variable of CROSS_COMPILE for your toolchain and ARCH=arm
$ make pico-imx7d_bl33_defconfig
$ make all
- Download and build OPTEE
$ git clone git@github.com:OP-TEE/optee_os.git
$ make PLATFORM=imx PLATFORM_FLAVOR=mx7dpico_mbl CFG_BOOT_SECONDARY_REQUEST=y ARCH=arm
- Download and build ATF
$ git clone https://git.linaro.org/landing-teams/working/mbl/arm-trusted-firmware.git -b linaro-imx7
$ make DEBUG=1 PLAT=picopi ARCH=aarch32 ARM_ARCH_MAJOR=7 \
CROSS_COMPILE=arm-linux-gnueabihf- LOG_LEVEL=50 V=1 \
CRASH_REPORTING=1 AARCH32_SP=optee all
Save file content in this link to file pico-imx7d.cfg:
http://git.linaro.org/landing-teams/working/mbl/u-boot.git/tree/board/technexion/pico-imx7d/pico-imx7d.cfg?h=linaro-imx
$ u-boot/tools/mkimage -n pico-imx7d.cfg -T imximage -e 0x9df00000 -d \
build/picopi/debug/bl2.bin bl2.imx
- Create FIP image
Create a fiptool_images/ folder in ATF folder, copy u-boot.bin in u-boot
folder and tee*.bin in optee out/arm-plat-imx/core/tee/ folder to
fiptool_images. Run below command in ATF folder to generate FIP image.
$ make -C tools/fiptool/
$ tools/fiptool/fiptool create --tos-fw fiptool_images/tee-header_v2.bin \
--tos-fw-extra1 fiptool_images/tee-pager_v2.bin \
--tos-fw-extra2 fiptool_images/tee-pageable_v2.bin \
--nt-fw fiptool_images/u-boot.bin \
fip.bin
- Burn the images to eMMC for test.
Run below command in atf folder:
$ dd if=build/picopi/debug/bl2.bin.imx of=/dev/disk/by-id/usb-<your device> bs=1024 seek=1;sync
$ dd if=fip.bin of=/dev/disk/by-id/usb-<your device> bs=1024 seek=1;sync
- Test
Just boot up your board and wait for u-boot start up after ATF's log.
For booting Linux in FIT image, please reference the FIT files in
u-boot doc/uImage.FIT/ folder.

12
board/technexion/pico-imx7d/pico-imx7d.c
View File

@ -63,6 +63,11 @@ int dram_init(void)
{
gd->ram_size = imx_ddr_size();
/* Subtract the defined OPTEE runtime firmware length */
#ifdef CONFIG_OPTEE_TZDRAM_SIZE
gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
#endif
return 0;
}
@ -80,8 +85,11 @@ int power_init_board(void)
p = pmic_get("PFUZE3000");
ret = pmic_probe(p);
if (ret)
return ret;
if (ret) {
printf("Warning: Cannot find PMIC PFUZE3000\n");
printf("\tPower consumption is not optimized.\n");
return 0;
}
pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);

30
board/toradex/apalis-imx8/Kconfig Normal file
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@ -0,0 +1,30 @@
if TARGET_APALIS_IMX8
config SYS_BOARD
default "apalis-imx8"
config SYS_VENDOR
default "toradex"
config SYS_CONFIG_NAME
default "apalis-imx8"
config TDX_CFG_BLOCK
default y
config TDX_HAVE_MMC
default y
config TDX_CFG_BLOCK_DEV
default "0"
config TDX_CFG_BLOCK_PART
default "1"
# Toradex config block in eMMC, at the end of 1st "boot sector"
config TDX_CFG_BLOCK_OFFSET
default "-512"
source "board/toradex/common/Kconfig"
endif

9
board/toradex/apalis-imx8/MAINTAINERS Normal file
View File

@ -0,0 +1,9 @@
Apalis iMX8
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8-apalis.dts
F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi
F: board/toradex/apalis-imx8/
F: configs/apalis-imx8qm_defconfig
F: include/configs/apalis-imx8.h

6
board/toradex/apalis-imx8/Makefile Normal file
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@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2019 Toradex
#
obj-y += apalis-imx8.o

66
board/toradex/apalis-imx8/README Normal file
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@ -0,0 +1,66 @@
U-Boot for the Toradex Apalis iMX8QM V1.0B Module
Quick Start
===========
- Build the ARM trusted firmware binary
- Get scfw_tcm.bin and ahab-container.img
- Build U-Boot
- Load U-Boot binary using uuu
- Flash U-Boot binary into the eMMC
- Boot
Get and Build the ARM Trusted Firmware
======================================
$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
$ cd imx-atf/
$ make PLAT=imx8qm bl31
Get scfw_tcm.bin and ahab-container.img
=======================================
$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
$ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
$ chmod +x firmware-imx-8.0.bin
$ ./firmware-imx-8.0.bin
Copy the following binaries to the U-Boot folder:
$ cp imx-atf/build/imx8qm/release/bl31.bin .
$ cp u-boot/u-boot.bin .
Copy the following firmware to the U-Boot folder:
$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
Build U-Boot
============
$ make apalis-imx8qm_defconfig
$ make u-boot-dtb.imx
Load the U-Boot Binary Using UUU
================================
Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
Put the module into USB recovery aka serial downloader mode, connect USB device
to your host and execute uuu:
sudo ./uuu u-boot/u-boot-dtb.imx
Flash the U-Boot Binary into the eMMC
=====================================
Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
load mmc 1:1 $loadaddr u-boot-dtb.imx
setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
mmc dev 0 1
mmc write ${loadaddr} 0x0 ${blkcnt}
Boot

149
board/toradex/apalis-imx8/apalis-imx8.c Normal file
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@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Toradex
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <environment.h>
#include <errno.h>
#include <linux/libfdt.h>
#include "../common/tdx-cfg-block.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
static iomux_cfg_t uart1_pads[] = {
SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate;
sc_err_t err = 0;
/* Power up UART1 */
err = sc_pm_set_resource_power_mode(-1, SC_R_UART_1, SC_PM_PW_MODE_ON);
if (err != SC_ERR_NONE)
return 0;
/* Set UART3 clock root to 80 MHz */
rate = 80000000;
err = sc_pm_set_clock_rate(-1, SC_R_UART_1, SC_PM_CLK_PER, &rate);
if (err != SC_ERR_NONE)
return 0;
/* Enable UART1 clock root */
err = sc_pm_clock_enable(-1, SC_R_UART_1, SC_PM_CLK_PER, true, false);
if (err != SC_ERR_NONE)
return 0;
setup_iomux_uart();
return 0;
}
#if IS_ENABLED(CONFIG_DM_GPIO)
static void board_gpio_init(void)
{
/* TODO */
}
#else
static inline void board_gpio_init(void) {}
#endif
#if IS_ENABLED(CONFIG_FEC_MXC)
#include <miiphy.h>
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
void build_info(void)
{
u32 sc_build = 0, sc_commit = 0;
/* Get SCFW build and commit id */
sc_misc_build_info(-1, &sc_build, &sc_commit);
if (!sc_build) {
printf("SCFW does not support build info\n");
sc_commit = 0; /* Display 0 if build info not supported */
}
printf("Build: SCFW %x\n", sc_commit);
}
int checkboard(void)
{
puts("Model: Toradex Apalis iMX8\n");
build_info();
print_bootinfo();
return 0;
}
int board_init(void)
{
board_gpio_init();
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(ulong addr)
{
/* TODO */
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
return ft_common_board_setup(blob, bd);
}
#endif
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* TODO move to common */
env_set("board_name", "Apalis iMX8QM");
env_set("board_rev", "v1.0");
#endif
return 0;
}

24
board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 Toradex
*
* Refer doc/README.imx8image for more details about how-to configure
* and create imx8image boot image
*/
#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM EMMC_FASTBOOT 0x400
/* SoC type IMX8QM */
SOC_TYPE IMX8QM
/* Append seco container image */
APPEND mx8qm-ahab-container.img
/* Create the 2nd container */
CONTAINER
/* Add scfw image with exec attribute */
IMAGE SCU mx8qm-apalis-scfw-tcm.bin
/* Add ATF image with exec attribute */
IMAGE A35 bl31.bin 0x80000000
/* Add U-Boot image with load attribute */
DATA A35 u-boot-dtb.bin 0x80020000

49
board/toradex/apalis_imx6/apalis_imx6.c
View File

@ -1131,52 +1131,3 @@ U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
.platdata = &mxc_serial_plat,
};
#if CONFIG_IS_ENABLED(AHCI)
static int sata_imx_probe(struct udevice *dev)
{
int i, err;
for (i = 0; i < APALIS_IMX6_SATA_INIT_RETRIES; i++) {
err = setup_sata();
if (err) {
printf("SATA setup failed: %d\n", err);
return err;
}
udelay(100);
err = dwc_ahsata_probe(dev);
if (!err)
break;
/* There is no device on the SATA port */
if (sata_dm_port_status(0, 0) == 0)
break;
/* There's a device, but link not established. Retry */
device_remove(dev, DM_REMOVE_NORMAL);
}
return 0;
}
struct ahci_ops sata_imx_ops = {
.port_status = dwc_ahsata_port_status,
.reset = dwc_ahsata_bus_reset,
.scan = dwc_ahsata_scan,
};
static const struct udevice_id sata_imx_ids[] = {
{ .compatible = "fsl,imx6q-ahci" },
{ }
};
U_BOOT_DRIVER(sata_imx) = {
.name = "dwc_ahci",
.id = UCLASS_AHCI,
.of_match = sata_imx_ids,
.ops = &sata_imx_ops,
.probe = sata_imx_probe,
};
#endif /* AHCI */

30
board/toradex/colibri-imx8x/Kconfig Normal file
View File

@ -0,0 +1,30 @@
if TARGET_COLIBRI_IMX8X
config SYS_BOARD
default "colibri-imx8x"
config SYS_VENDOR
default "toradex"
config SYS_CONFIG_NAME
default "colibri-imx8x"
config TDX_CFG_BLOCK
default y
config TDX_HAVE_MMC
default y
config TDX_CFG_BLOCK_DEV
default "0"
config TDX_CFG_BLOCK_PART
default "1"
# Toradex config block in eMMC, at the end of 1st "boot sector"
config TDX_CFG_BLOCK_OFFSET
default "-512"
source "board/toradex/common/Kconfig"
endif

9
board/toradex/colibri-imx8x/MAINTAINERS Normal file
View File

@ -0,0 +1,9 @@
Colibri iMX8X
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
S: Maintained
F: arch/arm/dts/fsl-imx8x-colibri.dts
F: arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi
F: board/toradex/colibri-imx8x/
F: configs/colibri-imx8qxp_defconfig
F: include/configs/colibri-imx8x.h

6
board/toradex/colibri-imx8x/Makefile Normal file
View File

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2019 Toradex
#
obj-y += colibri-imx8x.o

66
board/toradex/colibri-imx8x/README Normal file
View File

@ -0,0 +1,66 @@
U-Boot for the Toradex Colibri iMX8QXP V1.0B Module
Quick Start
===========
- Build the ARM trusted firmware binary
- Get scfw_tcm.bin and ahab-container.img
- Build U-Boot
- Load U-Boot binary using uuu
- Flash U-Boot binary into the eMMC
- Boot
Get and Build the ARM Trusted Firmware
======================================
$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
$ cd imx-atf/
$ make PLAT=imx8qxp bl31
Get scfw_tcm.bin and ahab-container.img
=======================================
$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
$ chmod +x firmware-imx-8.0.bin
$ ./firmware-imx-8.0.bin
Copy the following binaries to the U-Boot folder:
$ cp imx-atf/build/imx8qxp/release/bl31.bin .
$ cp u-boot/u-boot.bin .
Copy the following firmware to the U-Boot folder:
$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
Build U-Boot
============
$ make colibri-imx8qxp_defconfig
$ make u-boot-dtb.imx
Load the U-Boot Binary Using UUU
================================
Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
Put the module into USB recovery aka serial downloader mode, connect USB device
to your host and execute uuu:
sudo ./uuu u-boot/u-boot-dtb.imx
Flash the U-Boot Binary into the eMMC
=====================================
Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
load mmc 1:1 $loadaddr u-boot-dtb.imx
setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
mmc dev 0 1
mmc write ${loadaddr} 0x0 ${blkcnt}
Boot

24
board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg Normal file
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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 Toradex
*
* Refer doc/README.imx8image for more details about how-to configure
* and create imx8image boot image
*/
#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM EMMC_FASTBOOT 0x400
/* SoC type IMX8QX */
SOC_TYPE IMX8QX
/* Append seco container image */
APPEND mx8qx-ahab-container.img
/* Create the 2nd container */
CONTAINER
/* Add scfw image with exec attribute */
IMAGE SCU mx8qx-colibri-scfw-tcm.bin
/* Add ATF image with exec attribute */
IMAGE A35 bl31.bin 0x80000000
/* Add U-Boot image with load attribute */
DATA A35 u-boot-dtb.bin 0x80020000

160
board/toradex/colibri-imx8x/colibri-imx8x.c Normal file
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@ -0,0 +1,160 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Toradex
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <environment.h>
#include <errno.h>
#include <linux/libfdt.h>
#include "../common/tdx-cfg-block.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
static iomux_cfg_t uart3_pads[] = {
SC_P_FLEXCAN2_RX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_FLEXCAN2_TX | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
/* Transceiver FORCEOFF# signal, mux to use pull-up */
SC_P_QSPI0B_DQS | MUX_MODE_ALT(4) | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate;
sc_err_t err = 0;
/*
* This works around that having only UART3 up the baudrate is 1.2M
* instead of 115.2k. Set UART0 clock root to 80 MHz
*/
rate = 80000000;
err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
if (err != SC_ERR_NONE)
return 0;
/* Power up UART3 */
err = sc_pm_set_resource_power_mode(-1, SC_R_UART_3, SC_PM_PW_MODE_ON);
if (err != SC_ERR_NONE)
return 0;
/* Set UART3 clock root to 80 MHz */
rate = 80000000;
err = sc_pm_set_clock_rate(-1, SC_R_UART_3, SC_PM_CLK_PER, &rate);
if (err != SC_ERR_NONE)
return 0;
/* Enable UART3 clock root */
err = sc_pm_clock_enable(-1, SC_R_UART_3, SC_PM_CLK_PER, true, false);
if (err != SC_ERR_NONE)
return 0;
setup_iomux_uart();
return 0;
}
#if IS_ENABLED(CONFIG_DM_GPIO)
static void board_gpio_init(void)
{
/* TODO */
}
#else
static inline void board_gpio_init(void) {}
#endif
#if IS_ENABLED(CONFIG_FEC_MXC)
#include <miiphy.h>
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
void build_info(void)
{
u32 sc_build = 0, sc_commit = 0;
/* Get SCFW build and commit id */
sc_misc_build_info(-1, &sc_build, &sc_commit);
if (!sc_build) {
printf("SCFW does not support build info\n");
sc_commit = 0; /* Display 0 if build info not supported */
}
printf("Build: SCFW %x\n", sc_commit);
}
int checkboard(void)
{
puts("Model: Toradex Colibri iMX8X\n");
build_info();
print_bootinfo();
return 0;
}
int board_init(void)
{
board_gpio_init();
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(ulong addr)
{
/* TODO */
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
return ft_common_board_setup(blob, bd);
}
#endif
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* TODO move to common */
env_set("board_name", "Colibri iMX8QXP");
env_set("board_rev", "v1.0");
#endif
return 0;
}

3
board/wandboard/Makefile
View File

@ -2,4 +2,5 @@
#
# (C) Copyright 2013 Freescale Semiconductor, Inc.
obj-y := wandboard.o spl.o
obj-y := wandboard.o
obj-$(CONFIG_SPL_BUILD) += spl.o

3
board/wandboard/spl.c
View File

@ -20,7 +20,6 @@
#include <asm/arch/sys_proto.h>
#include <spl.h>
#if defined(CONFIG_SPL_BUILD)
#include <asm/arch/mx6-ddr.h>
/*
* Driving strength:
@ -513,5 +512,3 @@ int board_mmc_init(bd_t *bis)
return 0;
}
#endif

1
common/spl/Kconfig
View File

@ -28,6 +28,7 @@ config SPL_FRAMEWORK
config SPL_SIZE_LIMIT
int "Maximum size of SPL image"
depends on SPL
default 69632 if ARCH_MX6
default 0
help
Specifies the maximum length of the U-Boot SPL image.

56
configs/apalis-imx8qm_defconfig Normal file
View File

@ -0,0 +1,56 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_APALIS_IMX8=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg"
CONFIG_LOG=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_DM_GPIO=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC_SHARE_MDIO=y
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_SCU_THERMAL=y
# CONFIG_EFI_LOADER is not set

1
configs/apalis-tk1_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA124=y
CONFIG_TARGET_APALIS_TK1=y

1
configs/apalis_imx6_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y

1
configs/apalis_t30_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA30=y
CONFIG_TARGET_APALIS_T30=y

1
configs/colibri-imx6ull_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_COLIBRI_IMX6ULL=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISTRO_DEFAULTS=y

54
configs/colibri-imx8qxp_defconfig Normal file
View File

@ -0,0 +1,54 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_COLIBRI_IMX8X=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg"
CONFIG_LOG=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_CMD_CPU=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_DM_GPIO=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC_SHARE_MDIO=y
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_SCU_THERMAL=y
# CONFIG_EFI_LOADER is not set

1
configs/colibri_imx6_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y

2
configs/colibri_imx7_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX7=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SECURE_BOOT=y
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_NR_DRAM_BANKS=1
@ -63,6 +64,7 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RN5T567=y
CONFIG_DM_USB=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y

10
configs/colibri_imx7_emmc_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX7=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SECURE_BOOT=y
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_TARGET_COLIBRI_IMX7_EMMC=y
@ -66,3 +67,12 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_USB=y
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_USB_DEV=0
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000

1
configs/colibri_pxa270_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_COLIBRI_PXA270=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_USE_BOOTARGS=y

1
configs/colibri_t20_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x00110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA20=y
CONFIG_TARGET_COLIBRI_T20=y

1
configs/colibri_t30_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_SYS_TEXT_BASE=0x80110000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TEGRA30=y
CONFIG_TARGET_COLIBRI_T30=y

2
configs/colibri_vf_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_VF610=y
CONFIG_SYS_TEXT_BASE=0x3f401000
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_COLIBRI_VF=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y

15
configs/dh_imx6_defconfig
View File

@ -10,9 +10,13 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
@ -37,25 +41,35 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SCSI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="dh"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
@ -63,4 +77,3 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y
CONFIG_OF_LIBFDT=y

8
configs/mx6sabreauto_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_MX6SABREAUTO=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
@ -11,7 +12,6 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_NXP_BOARD_REVISION=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
@ -26,6 +26,9 @@ CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@ -55,7 +58,6 @@ CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
@ -70,6 +72,8 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

3
configs/mx6sabresd_defconfig
View File

@ -66,7 +66,6 @@ CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
@ -83,6 +82,8 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_PCI=y
CONFIG_DM_REGULATOR=y
CONFIG_SPI=y

18
configs/novena_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_KOSAGI_NOVENA=y
CONFIG_SPL_MMC_SUPPORT=y
@ -13,6 +14,7 @@ CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
@ -29,6 +31,7 @@ CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@ -40,15 +43,25 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-novena"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_DWC_AHSATA=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
@ -58,8 +71,7 @@ CONFIG_USB_ETH_CDC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

54
configs/phycore_pcl063_ull_defconfig Normal file
View File

@ -0,0 +1,54 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PCL063_ULL=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
# CONFIG_CMD_DEKBLOB is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_CACHE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Phytec"
CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_LZO=y

66
configs/pico-imx7d_bl33_defconfig Normal file
View File

@ -0,0 +1,66 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_PICO_IMX7D=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PXE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DFU_MMC=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_CONS_INDEX=4
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_OPTEE_TZDRAM_SIZE=0x2000000

20
configs/vining_2000_defconfig
View File

@ -1,10 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_TARGET_SAMTEC_VINING_2000=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_SOFTING_VINING_2000=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_NR_DRAM_BANKS=1
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/samtec/vining_2000/imximage.cfg"
CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg"
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SUPPORT_RAW_INITRD=y
@ -18,6 +21,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -31,15 +35,25 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6sx-softing-vining-2000"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_OF_LIBFDT=y

18
drivers/clk/imx/clk-imx8qm.c
View File

@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk)
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC2_IPG_CLK:
case IMX8QM_SDHC2_CLK:
case IMX8QM_SDHC2_DIV:
resource = SC_R_SDHC_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART0_IPG_CLK:
case IMX8QM_UART0_CLK:
resource = SC_R_UART_0;
@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC2_IPG_CLK:
case IMX8QM_SDHC2_CLK:
case IMX8QM_SDHC2_DIV:
resource = SC_R_SDHC_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET0_IPG_CLK:
case IMX8QM_ENET0_AHB_CLK:
case IMX8QM_ENET0_REF_DIV:
@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC2_IPG_CLK:
case IMX8QM_SDHC2_CLK:
case IMX8QM_SDHC2_DIV:
resource = SC_R_SDHC_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET0_IPG_CLK:
case IMX8QM_ENET0_AHB_CLK:
case IMX8QM_ENET0_REF_DIV:

9
drivers/crypto/fsl/jr.c
View File

@ -578,8 +578,6 @@ int sec_init_idx(uint8_t sec_idx)
{
ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
uint32_t mcr = sec_in32(&sec->mcfgr);
uint32_t jrown_ns;
int i;
int ret = 0;
#ifdef CONFIG_FSL_CORENET
@ -635,13 +633,6 @@ int sec_init_idx(uint8_t sec_idx)
#endif
#endif
/* Set ownership of job rings to non-TrustZone mode by default */
for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) {
jrown_ns = sec_in32(&sec->jrliodnr[i].ms);
jrown_ns |= JROWN_NS | JRMID_NS;
sec_out32(&sec->jrliodnr[i].ms, jrown_ns);
}
ret = jr_init(sec_idx);
if (ret < 0) {
printf("SEC initialization failed\n");

2
drivers/crypto/fsl/jr.h
View File

@ -33,8 +33,6 @@
#define JRNSLIODN_MASK 0x0fff0000
#define JRSLIODN_SHIFT 0
#define JRSLIODN_MASK 0x00000fff
#define JROWN_NS 0x00000008
#define JRMID_NS 0x00000001
#define JQ_DEQ_ERR -1
#define JQ_DEQ_TO_ERR -2

2
drivers/misc/imx8/fuse.c
View File

@ -15,13 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define FSL_ECC_WORD_START_1 0x10
#define FSL_ECC_WORD_END_1 0x10F
#ifdef CONFIG_IMX8QXP
#define FSL_ECC_WORD_START_2 0x220
#define FSL_ECC_WORD_END_2 0x31F
#define FSL_QXP_FUSE_GAP_START 0x110
#define FSL_QXP_FUSE_GAP_END 0x21F
#endif
#define FSL_SIP_OTP_READ 0xc200000A
#define FSL_SIP_OTP_WRITE 0xc200000B

2
drivers/net/fec_mxc.c
View File

@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register */
if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) {
if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);

220
drivers/pci/pcie_imx.c
View File

@ -16,6 +16,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm.h>
#include <linux/sizes.h>
#include <errno.h>
#include <asm/arch/sys_proto.h>
@ -92,6 +93,11 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
struct imx_pcie_priv {
void __iomem *dbi_base;
void __iomem *cfg_base;
};
/*
* PHY access functions
*/
@ -225,13 +231,13 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
return 0;
}
static int imx6_pcie_link_up(void)
static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
{
u32 rc, ltssm;
int rx_valid, temp;
/* link is debug bit 36, debug register 1 starts at bit 32 */
rc = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1);
rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
!(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
return -EAGAIN;
@ -243,8 +249,8 @@ static int imx6_pcie_link_up(void)
* && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
* to gen2 is stuck
*/
pcie_phy_read((void *)MX6_DBI_ADDR, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
ltssm = readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0) & 0x3F;
pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
if (rx_valid & 0x01)
return 0;
@ -254,15 +260,15 @@ static int imx6_pcie_link_up(void)
printf("transition to gen2 is stuck, reset PHY!\n");
pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
udelay(3000);
pcie_phy_read((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, &temp);
pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
pcie_phy_write((void *)MX6_DBI_ADDR, PHY_RX_OVRD_IN_LO, temp);
pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
return 0;
}
@ -270,7 +276,7 @@ static int imx6_pcie_link_up(void)
/*
* iATU region setup
*/
static int imx_pcie_regions_setup(void)
static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
{
/*
* i.MX6 defines 16MB in the AXI address map for PCIe.
@ -285,24 +291,27 @@ static int imx_pcie_regions_setup(void)
*/
/* CMD reg:I/O space, MEM space, and Bus Master Enable */
setbits_le32(MX6_DBI_ADDR | PCI_COMMAND,
setbits_le32(priv->dbi_base + PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
setbits_le32(MX6_DBI_ADDR + PCI_CLASS_REVISION,
setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
PCI_CLASS_BRIDGE_PCI << 16);
/* Region #0 is used for Outbound CFG space access. */
writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
writel(MX6_ROOT_ADDR, MX6_DBI_ADDR + PCIE_ATU_LOWER_BASE);
writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_BASE);
writel(MX6_ROOT_ADDR + MX6_ROOT_SIZE, MX6_DBI_ADDR + PCIE_ATU_LIMIT);
writel(lower_32_bits((uintptr_t)priv->cfg_base),
priv->dbi_base + PCIE_ATU_LOWER_BASE);
writel(upper_32_bits((uintptr_t)priv->cfg_base),
priv->dbi_base + PCIE_ATU_UPPER_BASE);
writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
priv->dbi_base + PCIE_ATU_LIMIT);
writel(0, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
writel(0, MX6_DBI_ADDR + PCIE_ATU_UPPER_TARGET);
writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
writel(PCIE_ATU_ENABLE, MX6_DBI_ADDR + PCIE_ATU_CR2);
writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
return 0;
}
@ -310,23 +319,24 @@ static int imx_pcie_regions_setup(void)
/*
* PCI Express accessors
*/
static uint32_t get_bus_address(pci_dev_t d, int where)
static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
pci_dev_t d, int where)
{
uint32_t va_address;
void __iomem *va_address;
/* Reconfigure Region #0 */
writel(0, MX6_DBI_ADDR + PCIE_ATU_VIEWPORT);
writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
if (PCI_BUS(d) < 2)
writel(PCIE_ATU_TYPE_CFG0, MX6_DBI_ADDR + PCIE_ATU_CR1);
writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
else
writel(PCIE_ATU_TYPE_CFG1, MX6_DBI_ADDR + PCIE_ATU_CR1);
writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
if (PCI_BUS(d) == 0) {
va_address = MX6_DBI_ADDR;
va_address = priv->dbi_base;
} else {
writel(d << 8, MX6_DBI_ADDR + PCIE_ATU_LOWER_TARGET);
va_address = MX6_IO_ADDR + SZ_16M - SZ_1M;
writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
va_address = priv->cfg_base;
}
va_address += (where & ~0x3);
@ -374,10 +384,10 @@ static void imx_pcie_fix_dabt_handler(bool set)
}
}
static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 *val)
static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
int where, u32 *val)
{
uint32_t va_address;
void __iomem *va_address;
int ret;
ret = imx_pcie_addr_valid(d);
@ -386,7 +396,7 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
return 0;
}
va_address = get_bus_address(d, where);
va_address = get_bus_address(priv, d, where);
/*
* Read the PCIe config space. We must replace the DABT handler
@ -403,17 +413,17 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
return 0;
}
static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 val)
static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
int where, u32 val)
{
uint32_t va_address = 0;
void __iomem *va_address = NULL;
int ret;
ret = imx_pcie_addr_valid(d);
if (ret)
return ret;
va_address = get_bus_address(d, where);
va_address = get_bus_address(priv, d, where);
/*
* Write the PCIe config space. We must replace the DABT handler
@ -430,7 +440,8 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
/*
* Initial bus setup
*/
static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
bool prepare_for_boot)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@ -465,12 +476,12 @@ static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
gpr12 = readl(&iomuxc_regs->gpr[12]);
if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
(gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
val = readl(priv->dbi_base + PCIE_PL_PFLR);
val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
val |= PCIE_PL_PFLR_FORCE_LINK;
imx_pcie_fix_dabt_handler(true);
writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
writel(val, priv->dbi_base + PCIE_PL_PFLR);
imx_pcie_fix_dabt_handler(false);
gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
@ -602,17 +613,17 @@ static int imx6_pcie_deassert_core_reset(void)
return 0;
}
static int imx_pcie_link_up(void)
static int imx_pcie_link_up(struct imx_pcie_priv *priv)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
uint32_t tmp;
int count = 0;
imx6_pcie_assert_core_reset(false);
imx6_pcie_assert_core_reset(priv, false);
imx6_pcie_init_phy();
imx6_pcie_deassert_core_reset();
imx_pcie_regions_setup();
imx_pcie_regions_setup(priv);
/*
* By default, the subordinate is set equally to the secondary
@ -621,9 +632,9 @@ static int imx_pcie_link_up(void)
* Force the PCIe RC subordinate to 0xff, otherwise no downstream
* devices will be detected if the enumeration is applied strictly.
*/
tmp = readl(MX6_DBI_ADDR + 0x18);
tmp = readl(priv->dbi_base + 0x18);
tmp |= (0xff << 16);
writel(tmp, MX6_DBI_ADDR + 0x18);
writel(tmp, priv->dbi_base + 0x18);
/*
* FIXME: Force the PCIe RC to Gen1 operation
@ -631,15 +642,15 @@ static int imx_pcie_link_up(void)
* up, otherwise no downstream devices are detected. After the
* link is up, a managed Gen1->Gen2 transition can be initiated.
*/
tmp = readl(MX6_DBI_ADDR + 0x7c);
tmp = readl(priv->dbi_base + 0x7c);
tmp &= ~0xf;
tmp |= 0x1;
writel(tmp, MX6_DBI_ADDR + 0x7c);
writel(tmp, priv->dbi_base + 0x7c);
/* LTSSM enable, starting link. */
setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
while (!imx6_pcie_link_up()) {
while (!imx6_pcie_link_up(priv)) {
udelay(10);
count++;
if (count >= 4000) {
@ -647,8 +658,8 @@ static int imx_pcie_link_up(void)
puts("PCI: pcie phy link never came up\n");
#endif
debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0),
readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1));
readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
return -EINVAL;
}
}
@ -656,6 +667,30 @@ static int imx_pcie_link_up(void)
return 0;
}
#if !CONFIG_IS_ENABLED(DM_PCI)
static struct imx_pcie_priv imx_pcie_priv = {
.dbi_base = (void __iomem *)MX6_DBI_ADDR,
.cfg_base = (void __iomem *)MX6_ROOT_ADDR,
};
static struct imx_pcie_priv *priv = &imx_pcie_priv;
static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 *val)
{
struct imx_pcie_priv *priv = hose->priv_data;
return imx_pcie_read_cfg(priv, d, where, val);
}
static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 val)
{
struct imx_pcie_priv *priv = hose->priv_data;
return imx_pcie_write_cfg(priv, d, where, val);
}
void imx_pcie_init(void)
{
/* Static instance of the controller. */
@ -665,6 +700,8 @@ void imx_pcie_init(void)
memset(&pcc, 0, sizeof(pcc));
hose->priv_data = priv;
/* PCI I/O space */
pci_set_region(&hose->regions[0],
MX6_IO_ADDR, MX6_IO_ADDR,
@ -691,7 +728,7 @@ void imx_pcie_init(void)
imx_pcie_write_config);
/* Start the controller. */
ret = imx_pcie_link_up();
ret = imx_pcie_link_up(priv);
if (!ret) {
pci_register_hose(hose);
@ -701,7 +738,7 @@ void imx_pcie_init(void)
void imx_pcie_remove(void)
{
imx6_pcie_assert_core_reset(true);
imx6_pcie_assert_core_reset(priv, true);
}
/* Probe function. */
@ -709,3 +746,86 @@ void pci_init_board(void)
{
imx_pcie_init();
}
#else
static int imx_pcie_dm_read_config(struct udevice *dev, pci_dev_t bdf,
uint offset, ulong *value,
enum pci_size_t size)
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
u32 tmpval;
int ret;
ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
if (ret)
return ret;
*value = pci_conv_32_to_size(tmpval, offset, size);
return 0;
}
static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
uint offset, ulong value,
enum pci_size_t size)
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
u32 tmpval, newval;
int ret;
ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
if (ret)
return ret;
newval = pci_conv_size_to_32(tmpval, value, offset, size);
return imx_pcie_write_cfg(priv, bdf, offset, newval);
}
static int imx_pcie_dm_probe(struct udevice *dev)
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
return imx_pcie_link_up(priv);
}
static int imx_pcie_dm_remove(struct udevice *dev)
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
imx6_pcie_assert_core_reset(priv, true);
return 0;
}
static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
if (!priv->dbi_base || !priv->cfg_base)
return -EINVAL;
return 0;
}
static const struct dm_pci_ops imx_pcie_ops = {
.read_config = imx_pcie_dm_read_config,
.write_config = imx_pcie_dm_write_config,
};
static const struct udevice_id imx_pcie_ids[] = {
{ .compatible = "fsl,imx6q-pcie" },
{ }
};
U_BOOT_DRIVER(imx_pcie) = {
.name = "imx_pcie",
.id = UCLASS_PCI,
.of_match = imx_pcie_ids,
.ops = &imx_pcie_ops,
.probe = imx_pcie_dm_probe,
.remove = imx_pcie_dm_remove,
.ofdata_to_platdata = imx_pcie_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct imx_pcie_priv),
.flags = DM_FLAG_OS_PREPARE,
};
#endif

2
drivers/pinctrl/nxp/pinctrl-imx6.c
View File

@ -10,7 +10,7 @@
#include "pinctrl-imx.h"
static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info __section(".data");
/* FIXME Before reloaction, BSS is overlapped with DT area */
static struct imx_pinctrl_soc_info imx6ul_pinctrl_soc_info = {

7
drivers/power/pmic/Kconfig
View File

@ -48,6 +48,13 @@ config PMIC_AS3722
interface and is designs to cover most of the power managementment
required for a tablets or laptop.
config DM_PMIC_BD71837
bool "Enable Driver Model for PMIC BD71837"
depends on DM_PMIC
help
This config enables implementation of driver-model pmic uclass features
for PMIC BD71837. The driver implements read/write operations.
config DM_PMIC_FAN53555
bool "Enable support for OnSemi FAN53555"
depends on DM_PMIC && DM_REGULATOR && DM_I2C

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