mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-24 12:44:23 +08:00
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
This commit is contained in:
Wolfgang Denk
commit
508eb85db7
@ -58,14 +58,12 @@ static struct nand_bbt_descr delta_bbt_descr = {
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.pattern = scan_ff_pattern
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};
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static struct nand_oobinfo delta_oob = {
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.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
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static struct nand_ecclayout delta_oob = {
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.eccbytes = 6,
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.eccpos = {2, 3, 4, 5, 6, 7},
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.oobfree = { {8, 2}, {12, 4} }
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};
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/*
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* not required for Monahans DFC
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*/
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@ -541,6 +539,7 @@ int board_nand_init(struct nand_chip *nand)
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nand->cmd_ctrl = dfc_hwcontrol;
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/* nand->dev_ready = dfc_device_ready; */
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->ecc.layout = &delta_oob;
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nand->options = NAND_BUSWIDTH_16;
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nand->waitfunc = dfc_wait;
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nand->read_byte = dfc_read_byte;
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@ -549,7 +548,6 @@ int board_nand_init(struct nand_chip *nand)
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nand->write_buf = dfc_write_buf;
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nand->cmdfunc = dfc_cmdfunc;
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/* nand->autooob = &delta_oob; */
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nand->badblock_pattern = &delta_bbt_descr;
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return 0;
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}
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@ -58,14 +58,12 @@ static struct nand_bbt_descr delta_bbt_descr = {
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.pattern = scan_ff_pattern
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};
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static struct nand_oobinfo delta_oob = {
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.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
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static struct nand_ecclayout delta_oob = {
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.eccbytes = 6,
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.eccpos = {2, 3, 4, 5, 6, 7},
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.oobfree = { {8, 2}, {12, 4} }
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};
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/*
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* not required for Monahans DFC
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*/
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@ -545,6 +543,7 @@ int board_nand_init(struct nand_chip *nand)
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nand->cmd_ctrl = dfc_hwcontrol;
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/* nand->dev_ready = dfc_device_ready; */
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->ecc.layout = &delta_oob;
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nand->options = NAND_BUSWIDTH_16;
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nand->waitfunc = dfc_wait;
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nand->read_byte = dfc_read_byte;
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@ -553,7 +552,6 @@ int board_nand_init(struct nand_chip *nand)
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nand->write_buf = dfc_write_buf;
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nand->cmdfunc = dfc_cmdfunc;
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/* nand->autooob = &delta_oob; */
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nand->badblock_pattern = &delta_bbt_descr;
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return 0;
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}
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@ -88,6 +88,9 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
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}
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#ifdef CFG_NAND_HW_ECC
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#ifdef CFG_DAVINCI_BROKEN_ECC
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/* Linux-compatible ECC uses MTD defaults. */
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/* These layouts are not compatible with Linux or RBL/UBL. */
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#ifdef CFG_NAND_LARGEPAGE
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static struct nand_ecclayout davinci_nand_ecclayout = {
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.eccbytes = 12,
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@ -112,6 +115,7 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
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#else
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#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
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#endif
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#endif /* CFG_DAVINCI_BROKEN_ECC */
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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@ -150,6 +154,15 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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u_int32_t tmp;
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#ifdef CFG_DAVINCI_BROKEN_ECC
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/*
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* This is not how you should read ECCs on large page Davinci devices.
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* The region parameter gets you ECCs for flash chips on different chip
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* selects, not the 4x512 byte pages in a 2048 byte page.
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*
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* Preserved for backwards compatibility though.
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*/
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int region, n;
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struct nand_chip *this = mtd->priv;
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@ -163,9 +176,26 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
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*ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
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region++;
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}
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#else
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const int region = 1;
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tmp = nand_davinci_readecc(mtd, region);
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/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
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* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
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tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
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/* Invert so that erased block ECC is correct */
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tmp = ~tmp;
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*ecc_code++ = tmp;
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*ecc_code++ = tmp >> 8;
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*ecc_code++ = tmp >> 16;
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#endif /* CFG_DAVINCI_BROKEN_ECC */
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return(0);
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}
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#ifdef CFG_DAVINCI_BROKEN_ECC
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static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
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{
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u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
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@ -282,13 +312,14 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in
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return(-1);
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}
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}
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#endif /* CFG_DAVINCI_BROKEN_ECC */
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static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *this;
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struct nand_chip *this = mtd->priv;
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#ifdef CFG_DAVINCI_BROKEN_ECC
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int block_count = 0, i, rc;
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this = mtd->priv;
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block_count = (this->ecc.size/512);
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for (i = 0; i < block_count; i++) {
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if (memcmp(read_ecc, calc_ecc, 3) != 0) {
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@ -301,9 +332,44 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
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calc_ecc += 3;
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dat += 512;
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}
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#else
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u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
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(calc_ecc[2] << 16);
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u_int32_t diff = ecc_calc ^ ecc_nand;
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if (diff) {
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if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
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/* Correctable error */
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if ((diff >> (12 + 3)) < this->ecc.size) {
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uint8_t find_bit = 1 << ((diff >> 12) & 7);
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uint32_t find_byte = diff >> (12 + 3);
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dat[find_byte] ^= find_bit;
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MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
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"bit ECC error at offset: %d, bit: "
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"%d\n", find_byte, find_bit);
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return 1;
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} else {
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return -1;
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}
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} else if (!(diff & (diff - 1))) {
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/* Single bit ECC error in the ECC itself,
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nothing to fix */
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MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
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"ECC.\n");
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return 1;
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} else {
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/* Uncorrectable error */
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MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
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return -1;
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}
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}
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#endif /* CFG_DAVINCI_BROKEN_ECC */
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return(0);
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}
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#endif
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#endif /* CFG_NAND_HW_ECC */
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static int nand_davinci_dev_ready(struct mtd_info *mtd)
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{
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@ -370,6 +436,8 @@ int board_nand_init(struct nand_chip *nand)
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#endif
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#ifdef CFG_NAND_HW_ECC
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nand->ecc.mode = NAND_ECC_HW;
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#ifdef CFG_DAVINCI_BROKEN_ECC
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nand->ecc.layout = &davinci_nand_ecclayout;
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#ifdef CFG_NAND_LARGEPAGE
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nand->ecc.size = 2048;
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nand->ecc.bytes = 12;
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@ -379,13 +447,16 @@ int board_nand_init(struct nand_chip *nand)
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#else
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#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
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#endif
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nand->ecc.layout = &davinci_nand_ecclayout;
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#else
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nand->ecc.size = 512;
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nand->ecc.bytes = 3;
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#endif /* CFG_DAVINCI_BROKEN_ECC */
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nand->ecc.calculate = nand_davinci_calculate_ecc;
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nand->ecc.correct = nand_davinci_correct_data;
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nand->ecc.hwctl = nand_davinci_enable_hwecc;
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#else
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nand->ecc.mode = NAND_ECC_SOFT;
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#endif
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#endif /* CFG_NAND_HW_ECC */
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/* Set address of hardware control function */
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nand->cmd_ctrl = nand_davinci_hwcontrol;
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@ -174,6 +174,14 @@ More Definitions:
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define CFG_DAVINCI_BROKEN_ECC
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Versions of U-Boot <= 1.3.3 and Montavista Linux kernels
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generated bogus ECCs on large-page NAND. Both large and small page
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NAND ECCs were incompatible with the Linux davinci git tree (since
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NAND was integrated in 2.6.24).
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Turn this ON if you want backwards compatibility.
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Turn this OFF if you want U-Boot and the Linux davinci git kernel
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to use the same ECC format.
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NOTE:
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=====
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@ -95,7 +95,6 @@ static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
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.eccbytes = 3,
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.eccpos = {6, 7, 8},
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.oobfree = { {0, 5}, {9, 7} },
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.oobavail = 12,
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};
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/* Small Page FLASH with FMR[ECCM] = 1 */
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@ -103,7 +102,6 @@ static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
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.eccbytes = 3,
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.eccpos = {8, 9, 10},
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.oobfree = { {0, 5}, {6, 2}, {11, 5} },
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.oobavail = 12,
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};
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/* Large Page FLASH with FMR[ECCM] = 0 */
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@ -111,7 +109,6 @@ static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
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.eccbytes = 12,
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.eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
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.oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
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.oobavail = 48,
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};
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/* Large Page FLASH with FMR[ECCM] = 1 */
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@ -119,7 +116,48 @@ static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
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.eccbytes = 12,
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.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
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.oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
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.oobavail = 48,
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};
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/*
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* fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
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* 1, so we have to adjust bad block pattern. This pattern should be used for
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* x8 chips only. So far hardware does not support x16 chips anyway.
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*/
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static u8 scan_ff_pattern[] = { 0xff, };
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static struct nand_bbt_descr largepage_memorybased = {
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.options = 0,
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.offs = 0,
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.len = 1,
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.pattern = scan_ff_pattern,
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};
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/*
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* ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
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* interfere with ECC positions, that's why we implement our own descriptors.
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* OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
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*/
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
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static struct nand_bbt_descr bbt_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = bbt_pattern,
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};
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static struct nand_bbt_descr bbt_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = mirror_pattern,
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};
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/*=================================*/
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@ -724,7 +762,12 @@ int board_nand_init(struct nand_chip *nand)
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nand->waitfunc = fsl_elbc_wait;
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/* set up nand options */
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nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
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nand->bbt_td = &bbt_main_descr;
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nand->bbt_md = &bbt_mirror_descr;
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/* set up nand options */
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nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
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NAND_USE_FLASH_BBT;
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nand->controller = &elbc_ctrl->controller;
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nand->priv = priv;
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@ -750,9 +793,10 @@ int board_nand_init(struct nand_chip *nand)
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priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
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/* adjust Option Register and ECC to match Flash page size */
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/* Large-page-specific setup */
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if (or & OR_FCM_PGS) {
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priv->page_size = 1;
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nand->badblock_pattern = &largepage_memorybased;
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/* adjust ecc setup if needed */
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if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
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