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arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN values

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The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN
can only accept certain values, and the set of acceptable values differs
between the AArch32 and AArch64 instructions sets. The default value of
CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default
value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0
assembly so it can handle completely arbitrary values.

Signed-off-by: Thierry Reding <treding@nvidia.com>
[twarren: trimmed Thierry's patch to remove changes already present]
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, cleaned up patch, wrote description, re-wrote subject]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Thierry Reding 2015-07-22 16:44:32 -06:00 committed by Tom Warren
parent f49357baad
commit 502a2aff76
1 changed files with 2 additions and 1 deletions
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3
arch/arm/lib/crt0_64.S
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@ -74,7 +74,8 @@ zero_gd:
cmp x0, x18 cmp x0, x18
b.gt zero_gd b.gt zero_gd
#if defined(CONFIG_SYS_MALLOC_F_LEN) #if defined(CONFIG_SYS_MALLOC_F_LEN)
sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN ldr x0, =CONFIG_SYS_MALLOC_F_LEN
sub x0, x18, x0
str x0, [x18, #GD_MALLOC_BASE] str x0, [x18, #GD_MALLOC_BASE]
#endif #endif
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */