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drivers/qe: Add more SNUM number for QE

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Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
1000 mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Haiying Wang 2009-05-20 12:30:35 -04:00 committed by Kumar Gala
parent 7211fbfa18
commit 4e7b25e4fe
3 changed files with 16 additions and 5 deletions
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15
drivers/qe/qe.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
@ -108,14 +108,23 @@ static void qe_sdma_init(void)
out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
}
static u8 thread_snum[QE_NUM_OF_SNUM] = {
/* This table is a list of the serial numbers of the Threads, taken from the
* "SNUM Table" chart in the QE Reference Manual. The order is not important,
* we just need to know what the SNUMs are for the threads.
*/
static u8 thread_snum[] = {
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xa8, 0xa9,
0xb8, 0xb9, 0xc8, 0xc9,
0xd8, 0xd9, 0xe8, 0xe9
0xd8, 0xd9, 0xe8, 0xe9,
0x08, 0x09, 0x18, 0x19,
0x28, 0x29, 0x38, 0x39,
0x48, 0x49, 0x58, 0x59,
0x68, 0x69, 0x78, 0x79,
0x80, 0x81
};
static void qe_snums_init(void)

1
drivers/qe/qe.h
View File

@ -25,7 +25,6 @@
#include "common.h"
#define QE_NUM_OF_SNUM 28
#define QE_NUM_OF_BRGS 16
#define UCC_MAX_NUM 8

5
include/asm-ppc/immap_qe.h
View File

@ -3,7 +3,7 @@
* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
* Copyright (c) 2006 Freescale Semiconductor, Inc.
* Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih <gridish@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
@ -609,10 +609,13 @@ extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8323)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_MPC8569)
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
#else
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
#endif
#endif /* __IMMAP_QE_H__ */