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arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x

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This patch adds support for the common AHCI controller on the Marvell
Armada 38x.

Tested on the Marvell DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Stefan Roese 2015-06-29 14:58:13 +02:00 committed by Luka Perkov
parent 2cc1aa2e00
commit 4d991cb3c7
3 changed files with 57 additions and 0 deletions
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55
arch/arm/mach-mvebu/cpu.c
View File

@ -6,6 +6,8 @@
#include <common.h>
#include <netdev.h>
#include <ahci.h>
#include <linux/mbus.h>
#include <asm/io.h>
#include <asm/pl310.h>
#include <asm/arch/cpu.h>
@ -256,6 +258,59 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_SCSI_AHCI_PLAT
#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
static void ahci_mvebu_mbus_config(void __iomem *base)
{
const struct mbus_dram_target_info *dram;
int i;
dram = mvebu_mbus_dram_info();
for (i = 0; i < 4; i++) {
writel(0, base + AHCI_WINDOW_CTRL(i));
writel(0, base + AHCI_WINDOW_BASE(i));
writel(0, base + AHCI_WINDOW_SIZE(i));
}
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
writel((cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
base + AHCI_WINDOW_CTRL(i));
writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
writel(((cs->size - 1) & 0xffff0000),
base + AHCI_WINDOW_SIZE(i));
}
}
static void ahci_mvebu_regret_option(void __iomem *base)
{
/*
* Enable the regret bit to allow the SATA unit to regret a
* request that didn't receive an acknowlegde and avoid a
* deadlock
*/
writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
}
void scsi_init(void)
{
printf("MVEBU SATA INIT\n");
ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
ahci_init((void __iomem *)MVEBU_SATA0_BASE);
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{

1
arch/arm/mach-mvebu/include/mach/soc.h
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@ -51,6 +51,7 @@
#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define SDRAM_MAX_CS 4

1
include/configs/db-88f6820-gp.h
View File

@ -36,6 +36,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_PING
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT