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powerpc/mpc8xxx: fix DDR data width checking

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Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
York Sun 2011-06-27 13:35:25 -07:00 committed by Kumar Gala
parent f2d264b660
commit 4c99cb9190
1 changed files with 27 additions and 8 deletions
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35
arch/powerpc/cpu/mpc8xxx/ddr/options.c
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@ -423,14 +423,33 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* presuming all dimms are similar
* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
*/
if (pdimm[0].primary_sdram_width == 64)
popts->data_bus_width = 0;
else if (pdimm[0].primary_sdram_width == 32)
popts->data_bus_width = 1;
else if (pdimm[0].primary_sdram_width == 16)
popts->data_bus_width = 2;
else
panic("Error: invalid primary sdram width!\n");
#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
if (pdimm[0].n_ranks != 0) {
if ((pdimm[0].data_width >= 64) && \
(pdimm[0].data_width <= 72))
popts->data_bus_width = 0;
else if ((pdimm[0].data_width >= 32) || \
(pdimm[0].data_width <= 40))
popts->data_bus_width = 1;
else {
panic("Error: data width %u is invalid!\n",
pdimm[0].data_width);
}
}
#else
if (pdimm[0].n_ranks != 0) {
if (pdimm[0].primary_sdram_width == 64)
popts->data_bus_width = 0;
else if (pdimm[0].primary_sdram_width == 32)
popts->data_bus_width = 1;
else if (pdimm[0].primary_sdram_width == 16)
popts->data_bus_width = 2;
else {
panic("Error: primary sdram width %u is invalid!\n",
pdimm[0].primary_sdram_width);
}
}
#endif
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)