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Various changes to esd HH405 board specific files
Patch by Matthias Fuchs, 07 Feb 2006
This commit is contained in:
Stefan Roese
parent
57cac1fa54
commit
48a05a5188
@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Various changes to esd HH405 board specific files
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Patch by Matthias Fuchs, 07 Feb 2006
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* Cleanup U-Boot boot messages on ARM.
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To match the U-Boot user interface on ARM platforms to the U-Boot
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@ -229,6 +229,9 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
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/*
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* Detect epson
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*/
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lcd_reg[0] = 0x00;
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lcd_reg[1] = 0x00;
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if (lcd_reg[0] == 0x1c) {
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/*
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* Big epson detected
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File diff suppressed because it is too large
Load Diff
@ -5,6 +5,9 @@
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -31,7 +34,6 @@
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#include <pci.h>
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#include <sm501.h>
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#ifdef CONFIG_VIDEO_SM501
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#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
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@ -66,10 +68,12 @@ static const SMI_REGS init_regs_800x600 [] =
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{0x00040, SWAP32(0x00021807)},
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{0x00044, SWAP32(0x221a0a01)},
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{0x00054, SWAP32(0x00000000)},
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/* GPIO */
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{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
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/* panel control regs... */
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{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
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{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
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{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
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{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
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{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
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{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
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{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
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@ -100,10 +104,12 @@ static const SMI_REGS init_regs_1024x768 [] =
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{0x00040, SWAP32(0x00021807)},
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{0x00044, SWAP32(0x011a0a01)},
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{0x00054, SWAP32(0x00000000)},
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/* GPIO */
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{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
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/* panel control regs... */
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{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
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{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
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{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
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{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
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{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
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{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
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{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
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@ -144,10 +150,12 @@ static const SMI_REGS init_regs_800x600 [] =
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{0x00040, SWAP32(0x00021807)},
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{0x00044, SWAP32(0x221a0a01)},
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{0x00054, SWAP32(0x00000000)},
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/* GPIO */
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{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
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/* panel control regs... */
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{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
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{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
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{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
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{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
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{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
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{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
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{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
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@ -178,10 +186,12 @@ static const SMI_REGS init_regs_1024x768 [] =
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{0x00040, SWAP32(0x00021807)},
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{0x00044, SWAP32(0x011a0a01)},
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{0x00054, SWAP32(0x00000000)},
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/* GPIO */
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{0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
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/* panel control regs... */
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{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
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{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
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{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
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{0x8000C, SWAP32(0x00010000)}, /* panel fb address */
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{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
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{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
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{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
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@ -272,6 +282,9 @@ au_image_t au_image[] = {
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int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
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/*
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* Get version of HH405 board from GPIO's
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*/
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int board_revision(void)
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{
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unsigned long osrh_reg;
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@ -279,10 +292,6 @@ int board_revision(void)
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unsigned long tcr_reg;
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unsigned long value;
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/*
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* Get version of HH405 board from GPIO's
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*/
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/*
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* Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
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*/
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@ -305,15 +314,13 @@ int board_revision(void)
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if (value & 0x80000000) {
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/* Revision 1.0 or 1.1 detected */
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return 0x0101;
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return 1;
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} else {
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if (value & 0x00400000) {
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/* unused */
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return 0x0103;
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return 3;
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} else {
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/* Revision >= 2.0 detected */
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/* rev. 2.x uses four SM501 GPIOs for revision coding */
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return 0x0200;
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return 2;
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}
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}
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}
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@ -349,6 +356,38 @@ int board_early_init_f (void)
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return 0;
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}
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int cf_enable(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int i;
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volatile unsigned short *fpga_ctrl =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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volatile unsigned short *fpga_status =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
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if (gd->board_type >= 2) {
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if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
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if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
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*fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
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for (i=0; i<300; i++)
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udelay(1000);
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*fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
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for (i=0; i<20; i++)
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udelay(1000);
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}
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} else {
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*fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
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*fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
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}
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}
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return 0;
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}
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int misc_init_r (void)
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{
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@ -433,9 +472,6 @@ int misc_init_r (void)
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* Write Board revision into FPGA
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*/
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*fpga_ctrl |= gd->board_type & 0x0003;
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if (gd->board_type >= 0x0200) {
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*fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
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}
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/*
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* Setup and enable EEPROM write protection
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@ -471,7 +507,7 @@ int misc_init_r (void)
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contrast0 = simple_strtol(str, NULL, 16);
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if (contrast0 > 255) {
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printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
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contrast0 = 0;
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contrast0 = 0xffffffff;
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}
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}
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@ -544,9 +580,9 @@ int misc_init_r (void)
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*/
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*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
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/*
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* Set lcd clock (small epson)
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* Set lcd clock (small epson), enable 1-wire interface
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*/
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*fpga_ctrl |= LCD_CLK_08330;
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*fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
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lcd_setup(0, 1);
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lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
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@ -565,8 +601,10 @@ int misc_init_r (void)
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puts("VGA: SM501 with 8 MB ");
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if (strcmp(str, "ppc221") == 0) {
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printf("(800*600, %dbpp)\n", BPP);
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*lcd_backlight = 0x002d; /* max. allowed brightness */
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} else if (strcmp(str, "ppc231") == 0) {
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printf("(1024*768, %dbpp)\n", BPP);
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*lcd_backlight = 0x0000;
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} else {
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printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
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return 0;
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@ -578,6 +616,8 @@ int misc_init_r (void)
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#endif /* CONFIG_VIDEO_SM501 */
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}
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cf_enable();
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return (0);
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}
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@ -608,14 +648,7 @@ int checkboard (void)
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}
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gd->board_type = board_revision();
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printf(", Rev %ld.%ld)\n",
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(gd->board_type >> 8) & 0xff,
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gd->board_type & 0xff);
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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printf(", Rev %ld.x)\n", gd->board_type);
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return 0;
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}
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@ -637,28 +670,27 @@ long int initdram (int board_type)
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}
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile unsigned short *fpga_mode =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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volatile unsigned short *fpga_status =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
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/*
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* Assert or deassert CompactFlash Reset Pin
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*/
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if (on) { /* assert RESET */
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*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
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} else { /* release RESET */
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*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
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if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
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(gd->board_type < 2)) {
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/*
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* Assert or deassert CompactFlash Reset Pin
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*/
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if (on) { /* assert RESET */
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cf_enable();
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*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
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} else { /* release RESET */
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*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
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}
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}
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}
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#endif /* CONFIG_IDE_RESET */
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@ -778,8 +810,7 @@ void video_get_info_str (int line_number, char *info)
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strcat(str, " (Missing bd_type!");
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}
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sprintf(str2, ", Rev %ld.%ld)",
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(gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
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sprintf(str2, ", Rev %ld.x)", gd->board_type);
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strcat(str, str2);
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strcpy(info, str);
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} else {
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@ -822,7 +853,11 @@ unsigned int board_video_get_fb (void)
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devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
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if (devbusfn != -1) {
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
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return (addr & 0xfffffffe);
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addr &= 0xfffffffe;
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#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
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addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
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#endif
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return addr;
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}
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return 0;
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@ -875,3 +910,15 @@ int board_get_height (void)
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}
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#endif /* CONFIG_VIDEO_SM501 */
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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@ -5,6 +5,9 @@
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -61,9 +64,13 @@
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_NET_MULTI 1
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#undef CONFIG_HAS_ETH1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
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@ -79,6 +86,7 @@
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#else
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#define CONFIG_VIDEO_SM501_16BPP
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#endif
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#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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@ -434,9 +442,12 @@
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#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
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#define CFG_FPGA_CTRL_CF_RESET 0x0040
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#define CFG_FPGA_CTRL_PS2_PWR 0x0080
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#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */
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#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */
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#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
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#define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
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#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
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#define CFG_FPGA_STATUS_CF_DETECT 0x8000
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#define LCD_CLK_OFF 0x0000 /* Off */
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#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
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