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Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

Browse Source 
Roger Quadros <rogerq@kernel.org> says:

Sync AM62 device tree files with Linux v6.9 and
add in the missing bits in -u-boot.dtsi to get CPSW
Ethernet working.

CI testing: https://github.com/u-boot/u-boot/pull/534
This commit is contained in:
Tom Rini 2024-05-20 09:38:05 -06:00
commit 4820864a67
17 changed files with 621 additions and 101 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

126
arch/arm/dts/k3-am62-main.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family Main Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
@ -42,9 +42,8 @@
};
};
main_conf: syscon@100000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x00100000 0x00 0x20000>;
main_conf: bus@100000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x00100000 0x20000>;
@ -121,8 +120,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>,
<0x00 0x48420000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
@ -138,8 +142,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
@ -502,6 +511,9 @@
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
gpio-ranges = <&main_pmx0 0 0 32>,
<&main_pmx0 32 33 38>,
<&main_pmx0 70 72 22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
@ -520,6 +532,10 @@
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
gpio-ranges = <&main_pmx0 0 94 41>,
<&main_pmx0 41 136 6>,
<&main_pmx0 47 143 3>,
<&main_pmx0 50 149 2>;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
@ -542,10 +558,9 @@
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 57 6>;
assigned-clock-parents = <&k3_clks 57 8>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
ti,trm-icp = <0x2>;
bus-width = <8>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
@ -563,7 +578,8 @@
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
ti,trm-icp = <0x2>;
bus-width = <4>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x8>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0x0>;
@ -575,8 +591,6 @@
ti,itap-del-sel-sd-hs = <0x1>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
ti,clkbuf-sel = <0x7>;
bus-width = <4>;
status = "disabled";
};
@ -587,7 +601,8 @@
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
clock-names = "clk_ahb", "clk_xin";
ti,trm-icp = <0x2>;
bus-width = <4>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x8>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0x0>;
@ -599,7 +614,6 @@
ti,itap-del-sel-sd-hs = <0xa>;
ti,itap-del-sel-sdr12 = <0xa>;
ti,itap-del-sel-sdr25 = <0x1>;
ti,clkbuf-sel = <0x7>;
status = "disabled";
};
@ -623,6 +637,8 @@
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
snps,usb2-gadget-lpm-disable;
snps,usb2-lpm-disable;
};
};
@ -646,6 +662,8 @@
interrupt-names = "host", "peripheral";
maximum-speed = "high-speed";
dr_mode = "otg";
snps,usb2-gadget-lpm-disable;
snps,usb2-lpm-disable;
};
};
@ -675,6 +693,15 @@
};
};
gpu: gpu@fd00000 {
compatible = "ti,am62-gpu", "img,img-axe";
reg = <0x00 0x0fd00000 0x00 0x20000>;
clocks = <&k3_clks 187 0>;
clock-names = "core";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
};
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
@ -753,9 +780,10 @@
<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
<0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */
<0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */
<0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
<0x00 0x30201000 0x00 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
"ovr1", "ovr2", "vp1", "vp2", "common1";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 6>,
<&dss_vp1_clk>,
@ -965,4 +993,66 @@
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
ti_csi2rx0: ticsi2rx@30102000 {
compatible = "ti,j721e-csi2rx-shim";
dmas = <&main_bcdma 0 0x4700 0>;
dma-names = "rx0";
reg = <0x00 0x30102000 0x00 0x1000>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
cdns_csi2rx0: csi-bridge@30101000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x00 0x30101000 0x00 0x1000>;
clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
<&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy0>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi0_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi0_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi0_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi0_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
dphy0: phy@30110000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x30110000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
};

4
arch/arm/dts/k3-am62-mcu.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {

5
arch/arm/dts/k3-am62-thermal.dtsi
View File

@ -1,4 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/thermal/thermal.h>

38
arch/arm/dts/k3-am62-wakeup.dtsi
View File

@ -1,10 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/bus/ti-sysc.h>
&cbass_wakeup {
wkup_conf: syscon@43000000 {
bootph-all;
@ -21,14 +23,34 @@
};
};
wkup_uart0: serial@2b300000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x2b300000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
target-module@2b300050 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x00 0x2b300050 0x00 0x4>,
<0x00 0x2b300054 0x00 0x4>,
<0x00 0x2b300058 0x00 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
ti,no-reset-on-init;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fclk";
status = "disabled";
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x2b300000 0x100000>;
wkup_uart0: serial@0 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
wkup_i2c0: i2c@2b200000 {

4
arch/arm/dts/k3-am62.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62 SoC Family
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>

63
arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
View File

@ -215,3 +215,66 @@
};
};
#endif
&main_bcdma {
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan";
};
&main_pktdma {
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
"tchan", "rchan", "rflow";
bootph-all;
};
&mdio0_pins_default {
bootph-all;
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy0 {
bootph-all;
};
&rgmii1_pins_default {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&phy_gmii_sel {
bootph-all;
};
&cpsw_port1 {
bootph-all;
};
&cpsw_port2 {
status = "disabled";
};

66
arch/arm/dts/k3-am625-beagleplay.dts
View File

@ -1,9 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* https://beagleplay.org/
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2024 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
@ -29,7 +29,6 @@
i2c3 = &main_i2c3;
i2c4 = &wkup_i2c0;
i2c5 = &mcu_i2c0;
mdio-gpio0 = &mdio0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
mmc2 = &sdhci2;
@ -231,27 +230,6 @@
};
};
/* Workaround for errata i2329 - just use mdio bitbang */
mdio0: mdio {
compatible = "virtual,mdio-gpio";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins_default>;
gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */
<&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */
#address-cells = <1>;
#size-cells = <0>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <25>;
reset-deassert-us = <60000>; /* T2 */
};
};
};
&main_pmx0 {
@ -312,8 +290,10 @@
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */
AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */
AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */
AM62X_IOPAD(0x018c, PIN_INPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
>;
};
@ -405,7 +385,6 @@
AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */
AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */
AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */
AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */
AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
>;
@ -443,7 +422,7 @@
>;
};
console_pins_default: console-default-pins {
main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
@ -573,11 +552,13 @@
};
&usbss0 {
bootph-all;
ti,vbus-divider;
status = "okay";
};
&usb0 {
bootph-all;
dr_mode = "peripheral";
};
@ -611,8 +592,23 @@
};
&cpsw3g_mdio {
/* Workaround for errata i2329 - Use mdio bitbang */
status = "disabled";
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <25>;
reset-deassert-us = <60000>; /* T2 */
};
};
&main_gpio0 {
@ -623,7 +619,7 @@
"USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */
"EEPROM_WP", /* 10 */
"CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */
"CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */
"CC1352P7_BOOT", "CC1352P7_RSTN", "GBE_RSTN", "", "", /* 13-17 */
"USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */
"", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */
"", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */
@ -827,7 +823,6 @@
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
status = "okay";
};
@ -840,7 +835,6 @@
vmmc-supply = <&vdd_3v3_sd>;
vqmmc-supply = <&vdd_sd_dv>;
ti,driver-strength-ohm = <50>;
disable-wp;
cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
cd-debounce-delay-ms = <100>;
@ -852,12 +846,10 @@
vmmc-supply = <&wlan_en>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
bus-width = <4>;
non-removable;
ti,fails-without-test-cd;
cap-power-off-card;
keep-power-in-suspend;
ti,driver-strength-ohm = <50>;
assigned-clocks = <&k3_clks 157 158>;
assigned-clock-parents = <&k3_clks 157 160>;
#address-cells = <1>;
@ -877,7 +869,7 @@
&main_uart0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&console_pins_default>;
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};

4
arch/arm/dts/k3-am625-sk.dts
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM625 SK: https://www.ti.com/lit/zip/sprr448
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

4
arch/arm/dts/k3-am625.dtsi
View File

@ -1,10 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/pdf/spruiv7
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

201
arch/arm/dts/k3-am62a-main.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family Main Domain peripherals
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
@ -42,9 +42,8 @@
};
};
main_conf: syscon@100000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x00100000 0x00 0x20000>;
main_conf: bus@100000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
@ -101,8 +100,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>,
<0x00 0x48420000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
@ -117,8 +121,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
@ -144,6 +153,44 @@
};
};
dmss_csi: bus@4e000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
ti,sci-dev-id = <198>;
inta_main_dmss_csi: interrupt-controller@4e0a0000 {
compatible = "ti,sci-inta";
reg = <0x00 0x4e0a0000 0x00 0x8000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupt-parent = <&gic500>;
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <200>;
ti,interrupt-ranges = <0 237 8>;
ti,unmapped-event-sources = <&main_bcdma_csi>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
};
main_bcdma_csi: dma-controller@4e230000 {
compatible = "ti,am62a-dmss-bcdma-csirx";
reg = <0x00 0x4e230000 0x00 0x100>,
<0x00 0x4e180000 0x00 0x8000>,
<0x00 0x4e100000 0x00 0x10000>;
reg-names = "gcfg", "rchanrt", "ringrt";
msi-parent = <&inta_main_dmss_csi>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <199>;
ti,sci-rm-range-rchan = <0x21>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
};
};
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
reg = <0x00 0x44043000 0x00 0xfe0>;
@ -462,7 +509,7 @@
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <87>;
ti,ngpio = <92>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
@ -480,7 +527,7 @@
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <88>;
ti,ngpio = <52>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
@ -488,6 +535,24 @@
status = "disabled";
};
sdhci0: mmc@fa10000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 57 6>;
assigned-clock-parents = <&k3_clks 57 8>;
bus-width = <8>;
mmc-hs200-1_8v;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-hs200 = <0x6>;
status = "disabled";
};
sdhci1: mmc@fa00000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
@ -495,7 +560,8 @@
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
ti,trm-icp = <0x2>;
bus-width = <4>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
@ -507,8 +573,30 @@
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
no-1-8-v;
status = "disabled";
};
sdhci2: mmc@fa20000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
clock-names = "clk_ahb", "clk_xin";
bus-width = <4>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
no-1-8-v;
status = "disabled";
};
@ -876,4 +964,91 @@
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
ti_csi2rx0: ticsi2rx@30102000 {
compatible = "ti,j721e-csi2rx-shim";
dmas = <&main_bcdma_csi 0 0x5000 0>;
dma-names = "rx0";
reg = <0x00 0x30102000 0x00 0x1000>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
cdns_csi2rx0: csi-bridge@30101000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x00 0x30101000 0x00 0x1000>;
clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
<&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy0>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi0_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi0_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi0_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi0_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
dphy0: phy@30110000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x30110000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
dss: dss@30200000 {
compatible = "ti,am62a7-dss";
reg = <0x00 0x30200000 0x00 0x1000>, /* common */
<0x00 0x30202000 0x00 0x1000>, /* vidl1 */
<0x00 0x30206000 0x00 0x1000>, /* vid */
<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
<0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */
<0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */
<0x00 0x30201000 0x00 0x1000>; /* common1 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2", "common1";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 6>,
<&k3_clks 186 0>,
<&k3_clks 186 2>;
clock-names = "fck", "vp1", "vp2";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
dss_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
};

4
arch/arm/dts/k3-am62a-mcu.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {

5
arch/arm/dts/k3-am62a-thermal.dtsi
View File

@ -1,4 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/thermal/thermal.h>

4
arch/arm/dts/k3-am62a-wakeup.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {

4
arch/arm/dts/k3-am62a.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A SoC Family
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>

162
arch/arm/dts/k3-am62a7-sk.dts
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* AM62A SK: https://www.ti.com/lit/zip/sprr459
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@ -20,6 +20,7 @@
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
@ -132,6 +133,18 @@
clock-frequency = <12288000>;
};
hdmi0: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};
codec_audio: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "AM62Ax-SKEVM";
@ -181,6 +194,39 @@
};
&main_pmx0 {
main_dss0_pins_default: main-dss0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x100, PIN_OUTPUT, 0) /* (V17) VOUT0_VSYNC */
AM62AX_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (T18) VOUT0_HSYNC */
AM62AX_IOPAD(0x104, PIN_OUTPUT, 0) /* (AA22) VOUT0_PCLK */
AM62AX_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (U17) VOUT0_DE */
AM62AX_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
AM62AX_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (U21) VOUT0_DATA1 */
AM62AX_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (U20) VOUT0_DATA2 */
AM62AX_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (U19) VOUT0_DATA3 */
AM62AX_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (T19) VOUT0_DATA4 */
AM62AX_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (U18) VOUT0_DATA5 */
AM62AX_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V22) VOUT0_DATA6 */
AM62AX_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA7 */
AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */
AM62AX_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (V18) VOUT0_DATA9 */
AM62AX_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */
AM62AX_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA11 */
AM62AX_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (W20) VOUT0_DATA12 */
AM62AX_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (W19) VOUT0_DATA13 */
AM62AX_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y21) VOUT0_DATA14 */
AM62AX_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA15 */
AM62AX_IOPAD(0x05c, PIN_OUTPUT, 1) /* (P22) GPMC0_AD8.VOUT0_DATA16 */
AM62AX_IOPAD(0x060, PIN_OUTPUT, 1) /* (R19) GPMC0_AD9.VOUT0_DATA17 */
AM62AX_IOPAD(0x064, PIN_OUTPUT, 1) /* (R20) GPMC0_AD10.VOUT0_DATA18 */
AM62AX_IOPAD(0x068, PIN_OUTPUT, 1) /* (R22) GPMC0_AD11.VOUT0_DATA19 */
AM62AX_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
AM62AX_IOPAD(0x070, PIN_OUTPUT, 1) /* (R21) GPMC0_AD13.VOUT0_DATA21 */
AM62AX_IOPAD(0x074, PIN_OUTPUT, 1) /* (T20) GPMC0_AD14.VOUT0_DATA22 */
AM62AX_IOPAD(0x078, PIN_OUTPUT, 1) /* (T21) GPMC0_AD15.VOUT0_DATA23 */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
@ -218,6 +264,22 @@
>;
};
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62AX_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLKLB */
AM62AX_IOPAD(0x21c, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
AM62AX_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
AM62AX_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
AM62AX_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
AM62AX_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
AM62AX_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
>;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@ -274,6 +336,12 @@
AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
>;
};
};
&mcu_pmx0 {
@ -407,6 +475,12 @@
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio1>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"BT_EN_SOC", "MMC1_SD_EN",
@ -434,6 +508,72 @@
DRVDD-supply = <&vcc_3v3_sys>;
DVDD-supply = <&buck5>;
};
exp2: gpio@23 {
compatible = "ti,tca6424";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "", "",
"", "",
"", "",
"", "",
"WL_LT_EN", "CSI_RSTz",
"", "",
"", "",
"", "",
"SPI0_FET_SEL", "SPI0_FET_OE",
"RGMII2_BRD_CONN_DET", "CSI_SEL2",
"CSI_EN", "AUTO_100M_1000M_CONFIG",
"CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
};
sii9022: bridge-hdmi@3b {
compatible = "sil,sii9022";
reg = <0x3b>;
interrupt-parent = <&exp1>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 >;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&dpi1_out>;
};
};
port@1 {
reg = <1>;
sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&main_i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&sdhci0 {
/* eMMC */
status = "okay";
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
disable-wp;
};
&sdhci1 {
@ -442,7 +582,6 @@
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
@ -544,3 +683,20 @@
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_dss0_pins_default>;
};
&dss_ports {
/* VP2: DPI Output */
port@1 {
reg = <1>;
dpi1_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};

4
arch/arm/dts/k3-am62a7.dtsi
View File

@ -1,10 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Device Tree Source for AM62A7 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/zip/spruj16
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;

24
arch/arm/dts/k3-am62x-sk-common.dtsi
View File

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
* Common dtsi for AM62x SK and derivatives
*
* Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/leds/common.h>
@ -399,12 +399,18 @@
};
};
&main_i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&sdhci0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
@ -414,7 +420,6 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
@ -453,6 +458,7 @@
};
&usbss0 {
bootph-all;
status = "okay";
ti,vbus-divider;
};
@ -463,6 +469,7 @@
};
&usb0 {
bootph-all;
#address-cells = <1>;
#size-cells = <0>;
usb-role-switch;
@ -517,3 +524,12 @@
};
};
};
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_gpio_intr {
status = "reserved";
};