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board: phytec: am64x: Add PHYTEC phyCORE-AM64x SoM

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Add support for PHYTEC phyCORE-AM64x SoM.

Supported features:
  - 2GB DDR4 RAM
  - eMMC Flash
  - external uSD
  - OSPI NOR Flash
  - debug UART

Product page SoM: https://www.phytec.com/product/phycore-am64x

Device trees were taken from Linux v6.8-rc2.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
This commit is contained in:
Wadim Egorov 2024-02-28 09:42:16 +01:00 committed by Tom Rini
parent 9522956605
commit 46b3ff8205
20 changed files with 5710 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/Makefile
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@ -1420,7 +1420,9 @@ dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
k3-am642-r5-sk.dtb
k3-am642-r5-sk.dtb \
k3-am642-phyboard-electra-rdk.dtb \
k3-am642-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb \

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arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi Normal file
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arch/arm/dts/k3-am64-phycore-som.dtsi Normal file
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@ -0,0 +1,320 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phycore-am64x
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-AM64x";
compatible = "phytec,am64-phycore-som", "ti,am642";
aliases {
ethernet0 = &cpsw_port1;
mmc0 = &sdhci0;
rtc0 = &i2c_som_rtc;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
};
};
vcc_5v0_som: regulator-vcc-5v0-som {
/* VIN / VCC_5V0_SOM */
compatible = "regulator-fixed";
regulator-name = "VCC_5V0_SOM";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&main_pmx0 {
cpsw_mdio_pins_default: cpsw-mdio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
>;
};
cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
>;
};
eeprom_wp_pins_default: eeprom-wp-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
>;
};
leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
};
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
>;
};
rtc_pins_default: rtc-defaults-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */
>;
};
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_rgmii1_pins_default>;
};
&cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cpsw_mdio_pins_default>;
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&main_gpio0>;
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw_port2 {
status = "disabled";
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c32";
pinctrl-names = "default";
pinctrl-0 = <&eeprom_wp_pins_default>;
pagesize = <32>;
reg = <0x50>;
};
i2c_som_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&rtc_pins_default>;
interrupt-parent = <&main_gpio1>;
interrupts = <70 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
};
};
&sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
keep-power-in-suspend;
};

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arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi Normal file
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@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phycore-am64x
*/
#include "k3-am642-phycore-som-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-all;
};
};
&cbass_main {
bootph-all;
};
&dmsc {
bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
&dmss {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_reset {
bootph-all;
};
&main_bcdma {
bootph-all;
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan";
};
&main_conf {
bootph-all;
chipid@14 {
bootph-all;
};
};
&main_gpio0 {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&main_pktdma {
bootph-all;
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
"tchan", "rchan", "rflow";
};
&main_pmx0 {
bootph-all;
};
&main_timer0 {
bootph-all;
clock-frequency = <200000000>;
};
&main_uart0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_usb0_pins_default {
bootph-all;
};
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
};
};
&ospi0_pins_default {
bootph-all;
};
&sdhci0 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&usbss0 {
bootph-all;
};
&usb0 {
bootph-all;
};

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arch/arm/dts/k3-am642-phyboard-electra-rdk.dts Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phyboard-am64x
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/phy/phy.h>
#include "k3-am642.dtsi"
#include "k3-am64-phycore-som.dtsi"
#include "k3-serdes.h"
/ {
compatible = "phytec,am642-phyboard-electra-rdk",
"phytec,am64-phycore-som", "ti,am642";
model = "PHYTEC phyBOARD-Electra-AM64x RDK";
aliases {
mmc1 = &sdhci1;
serial2 = &main_uart0;
serial3 = &main_uart1;
};
chosen {
stdout-path = &main_uart0;
};
can_tc1: can-phy0 {
compatible = "ti,tcan1042";
pinctrl-names = "default";
pinctrl-0 = <&can_tc1_pins_default>;
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
};
can_tc2: can-phy1 {
compatible = "ti,tcan1042";
pinctrl-names = "default";
pinctrl-0 = <&can_tc2_pins_default>;
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>;
};
keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins_default>;
key-home {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&main_gpio0 17 GPIO_ACTIVE_HIGH>;
};
key-menu {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
led-1 {
color = <LED_COLOR_ID_RED>;
gpios = <&main_gpio0 15 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
function = LED_FUNCTION_DISK;
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&main_gpio0 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
function = LED_FUNCTION_DISK;
};
};
vcc_3v3_mmc: regulator-sd {
/* TPS22963C */
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_MMC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&main_pmx0 {
can_tc1_pins_default: can-tc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */
>;
};
can_tc2_pins_default: can-tc2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
>;
};
gpio_keys_pins_default: gpio-keys-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */
>;
};
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
>;
};
main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
>;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
>;
};
pcie0_pins_default: pcie0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
>;
};
user_leds_pins_default: user-leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
>;
};
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x51>;
};
led-controller@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-3 {
label = "red:user";
type = <PCA9532_TYPE_LED>;
};
led-4 {
label = "green:user";
type = <PCA9532_TYPE_LED>;
};
led-5 {
label = "blue:user";
type = <PCA9532_TYPE_LED>;
};
};
};
&main_mcan0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&can_tc1>;
};
&main_mcan1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&can_tc2>;
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
current-speed = <115200>;
};
&main_uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
uart-has-rtscts;
current-speed = <115200>;
};
&sdhci1 {
status = "okay";
vmmc-supply = <&vcc_3v3_mmc>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
bus-width = <4>;
ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
};
&serdes0 {
serdes0_pcie_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 1>;
};
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_USB>;
};
&usbss0 {
ti,vbus-divider;
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
dr_mode = "host";
maximum-speed = "super-speed";
phys = <&serdes0_pcie_usb_link>;
phy-names = "cdns3,usb3-phy";
};

457
arch/arm/dts/k3-am642-phycore-som-binman.dtsi Normal file
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@ -0,0 +1,457 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Based on k3-am64x-binman.dtsi
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_PHYCORE_AM64X_R5
&binman {
tiboot3-am64x_sr2-hs-phycore-som.bin {
filename = "tiboot3-am64x_sr2-hs-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl>, <&ti_sci_enc>,
<&combined_sysfw_cfg>, <&sysfw_inner_cert>;
combined;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl>;
content-sysfw = <&ti_sci_enc>;
content-sysfw-data = <&combined_sysfw_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
load = <0x70000000>;
load-sysfw = <0x44000>;
load-sysfw-data = <0x7b000>;
};
u_boot_spl: u-boot-spl {
no-expanded;
};
ti_sci_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_sysfw_cfg: combined-sysfw-cfg.bin {
filename = "combined-sysfw-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin";
type = "blob-ext";
optional;
};
};
};
&binman {
tiboot3-am64x_sr2-hs-fs-phycore-som.bin {
filename = "tiboot3-am64x_sr2-hs-fs-phycore-som.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_sci_enc_fs>,
<&combined_sysfw_cfg_fs>, <&sysfw_inner_cert_fs>;
combined;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl_fs>;
content-sysfw = <&ti_sci_enc_fs>;
content-sysfw-data = <&combined_sysfw_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
load = <0x70000000>;
load-sysfw = <0x44000>;
load-sysfw-data = <0x7b000>;
};
u_boot_spl_fs: u-boot-spl {
no-expanded;
};
ti_sci_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_sysfw_cfg_fs: combined-sysfw-cfg.bin {
filename = "combined-sysfw-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
};
};
&binman {
tiboot3-am64x-gp-phycore-som.bin {
filename = "tiboot3-am64x-gp-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_sci_gp>, <&combined_sysfw_cfg_gp>;
combined;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x70000000>;
content-sysfw = <&ti_sci_gp>;
load-sysfw = <0x44000>;
content-sysfw-data = <&combined_sysfw_cfg_gp>;
load-sysfw-data = <0x7b000>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_sci_gp: ti-sci-gp.bin {
filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin";
type = "blob-ext";
optional;
};
combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin {
filename = "combined-sysfw-cfg.bin";
type = "blob-ext";
};
};
};
#endif
#ifdef CONFIG_TARGET_PHYCORE_AM64X_A53
#define SPL_AM642_PHYBOARD_ELECTRA_DTB "spl/dts/k3-am642-phyboard-electra-rdk.dtb"
#define AM642_PHYBOARD_ELECTRA_DTB "u-boot.dtb"
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
spl_am642_phyboard_electra_dtb: blob-ext {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
am642_phyboard_electra_dtb: blob-ext {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif
#ifdef CONFIG_TARGET_PHYCORE_AM64X_A53
#define SPL_AM642_PHYBOARD_ELECTRA_DTB "spl/dts/k3-am642-phyboard-electra-rdk.dtb"
#define AM642_PHYBOARD_ELECTRA_DTB "u-boot.dtb"
&binman {
ti-spl {
insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
spl_am642_phyboard_electra_dtb: blob-ext {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&am642_phyboard_electra_dtb>;
keyfile = "custMpk.pem";
};
am642_phyboard_electra_dtb: blob-ext {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
dm {
blob-ext {
filename = "/dev/null";
};
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = SPL_AM642_PHYBOARD_ELECTRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for AM64 board";
};
fdt-0 {
description = "k3-am642-phyboard-electra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = AM642_PHYBOARD_ELECTRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am642-phyboard-electra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif /* CONFIG_TARGET_PHYCORE_AM64X_A53 */

140
arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts Normal file
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@ -0,0 +1,140 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
/dts-v1/;
#include "k3-am642-phyboard-electra-rdk.dts"
#include "k3-am64-phycore-som-ddr4-2gb.dtsi"
#include "k3-am64-ddr.dtsi"
#include "k3-am642-phyboard-electra-rdk-u-boot.dtsi"
/ {
aliases {
ethernet0 = &cpsw3g;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
vtt_supply: vtt-supply {
compatible = "regulator-fixed";
regulator-name = "vtt";
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&main_gpio0 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&cbass_mcu {
bootph-pre-ram;
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_esm {
bootph-pre-ram;
};
&main_gpio0 {
bootph-pre-ram;
};
&main_pmx0 {
bootph-pre-ram;
ddr_vtt_pins_default: ddr-vtt-default-pins {
bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0038, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN3.GPIO0_14 */
>;
};
};
/* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&main_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
* UART init failure
*/
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
};
&mcu_esm {
bootph-pre-ram;
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};

19
arch/arm/mach-k3/am64x/Kconfig
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@ -29,8 +29,27 @@ config TARGET_AM642_R5_EVM
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
config TARGET_PHYCORE_AM64X_A53
bool "PHYTEC phyCORE-AM64x running on A53"
select ARM64
select BINMAN
imply BOARD
imply SPL_BOARD
config TARGET_PHYCORE_AM64X_R5
bool "PHYTEC phyCORE-AM64x running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
endchoice
source "board/phytec/phycore_am64x/Kconfig"
source "board/ti/am64x/Kconfig"
endif

33
board/phytec/phycore_am64x/Kconfig Normal file
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@ -0,0 +1,33 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
# Author: Matt McKee <mmckee@phytec.com>
#
# Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
# Author: Wadim Egorov <w.egorov@phytec.de>
if TARGET_PHYCORE_AM64X_A53
config SYS_BOARD
default "phycore_am64x"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "phycore_am64x"
endif
if TARGET_PHYCORE_AM64X_R5
config SYS_BOARD
default "phycore_am64x"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "phycore_am64x"
endif

15
board/phytec/phycore_am64x/MAINTAINERS Normal file
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@ -0,0 +1,15 @@
phyCORE-AM64x
M: Wadim Egorov <w.egorov@phytec.de>
W: https://www.phytec.com/product/phycore-am64x
S: Maintained
F: arch/arm/dts/k3-am64-phycore-som-ddr4-2gb.dtsi
F: arch/arm/dts/k3-am64-phycore-som.dtsi
F: arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi
F: arch/arm/dts/k3-am642-phyboard-electra-rdk.dts
F: arch/arm/dts/k3-am642-phycore-som-binman.dtsi
F: arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts
F: board/phytec/phycore_am64x
F: configs/phycore_am64x_a53_defconfig
F: configs/phycore_am64x_r5_defconfig
F: doc/board/phytec/phycore-am64x.rst
F: include/configs/phycore_am64x.h

9
board/phytec/phycore_am64x/Makefile Normal file
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@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
# Author: Matt McKee <mmckee@phytec.com>
#
# Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
# Author: Wadim Egorov <w.egorov@phytec.de>
obj-y += phycore-am64x.o

36
board/phytec/phycore_am64x/board-cfg.yaml Normal file
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@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Board configuration for AM64x
#
---
board-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1
control:
subhdr:
magic: 0xC1D3
size: 7
main_isolation_enable: 0x5A
main_isolation_hostid: 0x2
secproxy:
subhdr:
magic: 0x1207
size: 7
scaling_factor: 0x1
scaling_profile: 0x1
disable_main_nav_secure_proxy: 0
msmc:
subhdr:
magic: 0xA5C3
size: 5
msmc_cache_size: 0x0
debug_cfg:
subhdr:
magic: 0x020C
size: 8
trace_dst_enables: 0x00
trace_src_enables: 0x00

50
board/phytec/phycore_am64x/phycore-am64x.c Normal file
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@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
* Author: Matt McKee <mmckee@phytec.com>
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
#include <asm/io.h>
#include <env.h>
#include <env_internal.h>
#include <spl.h>
#include <fdt_support.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
#define CTRLMMR_USB0_PHY_CTRL 0x43004008
#define CORE_VOLTAGE 0x80000000
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
u32 val;
/* Set USB PHY core voltage to 0.85V */
val = readl(CTRLMMR_USB0_PHY_CTRL);
val &= ~(CORE_VOLTAGE);
writel(val, CTRLMMR_USB0_PHY_CTRL);
/* Init DRAM size for R5/A53 SPL */
dram_init_banksize();
}
#endif

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board/phytec/phycore_am64x/phycore_am64x.env Normal file
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fdtaddr=0x88000000
loadaddr=0x82000000
scriptaddr=0x80000000
fdt_addr_r=0x88000000
kernel_addr_r=0x82000000
ramdisk_addr_r=0x88080000
fdtoverlay_addr_r=0x89000000
fdtfile=CONFIG_DEFAULT_FDT_FILE
mmcdev=1
mmcroot=2
mmcpart=1
console=ttyS2,115200n8
mmcargs=setenv bootargs console=${console} earlycon=ns16550a,mmio32,0x02800000
root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw
loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} Image
loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}
mmcboot=run mmcargs;
mmc dev ${mmcdev};
mmc rescan;
run loadimage;
run loadfdt;
booti ${loadaddr} - ${fdtaddr}

12
board/phytec/phycore_am64x/pm-cfg.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Power management configuration for AM64x
#
---
pm-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1

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board/phytec/phycore_am64x/rm-cfg.yaml Normal file
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379
board/phytec/phycore_am64x/sec-cfg.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Security configuration for AM64x
#
---
sec-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1
processor_acl_list:
subhdr:
magic: 0xF1EA
size: 164
proc_acl_entries:
- # 1
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 2
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 3
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 4
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 5
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 6
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 7
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 8
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 9
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 10
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 11
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 12
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 13
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 14
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 15
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 16
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 17
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 18
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 19
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 20
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 21
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 22
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 23
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 24
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 25
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 26
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 27
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 28
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 29
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 30
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 31
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 32
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
host_hierarchy:
subhdr:
magic: 0x8D27
size: 68
host_hierarchy_entries:
- # 1
host_id: 0
supervisor_host_id: 0
- # 2
host_id: 0
supervisor_host_id: 0
- # 3
host_id: 0
supervisor_host_id: 0
- # 4
host_id: 0
supervisor_host_id: 0
- # 5
host_id: 0
supervisor_host_id: 0
- # 6
host_id: 0
supervisor_host_id: 0
- # 7
host_id: 0
supervisor_host_id: 0
- # 8
host_id: 0
supervisor_host_id: 0
- # 9
host_id: 0
supervisor_host_id: 0
- # 10
host_id: 0
supervisor_host_id: 0
- # 11
host_id: 0
supervisor_host_id: 0
- # 12
host_id: 0
supervisor_host_id: 0
- # 13
host_id: 0
supervisor_host_id: 0
- # 14
host_id: 0
supervisor_host_id: 0
- # 15
host_id: 0
supervisor_host_id: 0
- # 16
host_id: 0
supervisor_host_id: 0
- # 17
host_id: 0
supervisor_host_id: 0
- # 18
host_id: 0
supervisor_host_id: 0
- # 19
host_id: 0
supervisor_host_id: 0
- # 20
host_id: 0
supervisor_host_id: 0
- # 21
host_id: 0
supervisor_host_id: 0
- # 22
host_id: 0
supervisor_host_id: 0
- # 23
host_id: 0
supervisor_host_id: 0
- # 24
host_id: 0
supervisor_host_id: 0
- # 25
host_id: 0
supervisor_host_id: 0
- # 26
host_id: 0
supervisor_host_id: 0
- # 27
host_id: 0
supervisor_host_id: 0
- # 28
host_id: 0
supervisor_host_id: 0
- # 29
host_id: 0
supervisor_host_id: 0
- # 30
host_id: 0
supervisor_host_id: 0
- # 31
host_id: 0
supervisor_host_id: 0
- # 32
host_id: 0
supervisor_host_id: 0
otp_config:
subhdr:
magic: 0x4081
size: 69
write_host_id: 0
otp_entry:
- # 1
host_id: 0
host_perms: 0
- # 2
host_id: 0
host_perms: 0
- # 3
host_id: 0
host_perms: 0
- # 4
host_id: 0
host_perms: 0
- # 5
host_id: 0
host_perms: 0
- # 6
host_id: 0
host_perms: 0
- # 7
host_id: 0
host_perms: 0
- # 8
host_id: 0
host_perms: 0
- # 9
host_id: 0
host_perms: 0
- # 10
host_id: 0
host_perms: 0
- # 11
host_id: 0
host_perms: 0
- # 12
host_id: 0
host_perms: 0
- # 13
host_id: 0
host_perms: 0
- # 14
host_id: 0
host_perms: 0
- # 15
host_id: 0
host_perms: 0
- # 16
host_id: 0
host_perms: 0
- # 17
host_id: 0
host_perms: 0
- # 18
host_id: 0
host_perms: 0
- # 19
host_id: 0
host_perms: 0
- # 20
host_id: 0
host_perms: 0
- # 21
host_id: 0
host_perms: 0
- # 22
host_id: 0
host_perms: 0
- # 23
host_id: 0
host_perms: 0
- # 24
host_id: 0
host_perms: 0
- # 25
host_id: 0
host_perms: 0
- # 26
host_id: 0
host_perms: 0
- # 27
host_id: 0
host_perms: 0
- # 28
host_id: 0
host_perms: 0
- # 29
host_id: 0
host_perms: 0
- # 30
host_id: 0
host_perms: 0
- # 31
host_id: 0
host_perms: 0
- # 32
host_id: 0
host_perms: 0
dkek_config:
subhdr:
magic: 0x5170
size: 12
allowed_hosts: [128, 0, 0, 0]
allow_dkek_export_tisci: 0x5A
rsvd: [0, 0, 0]
sa2ul_cfg:
subhdr:
magic: 0x23BE
size: 0
auth_resource_owner: 0
enable_saul_psil_global_config_writes: 0
rsvd: [0, 0]
sec_dbg_config:
subhdr:
magic: 0x42AF
size: 16
allow_jtag_unlock: 0x5A
allow_wildcard_unlock: 0x5A
allowed_debug_level_rsvd: 0
rsvd: 0
min_cert_rev: 0x0
jtag_unlock_hosts: [0, 0, 0, 0]
sec_handover_cfg:
subhdr:
magic: 0x608F
size: 10
handover_msg_sender: 0
handover_to_host_id: 0
rsvd: [0, 0, 0, 0]

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configs/phycore_am64x_a53_defconfig Normal file
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CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
CONFIG_K3_ATF_LOAD_ADDR=0x701c0000
CONFIG_TARGET_PHYCORE_AM64X_A53=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-phyboard-electra-rdk"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTCOMMAND="run mmcboot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SPL_MAX_SIZE=0x180000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL"
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_PCA953X=y
CONFIG_SPL_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV3028=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384

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CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
CONFIG_TARGET_PHYCORE_AM64X_R5=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7019b800
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SF_DEFAULT_MODE=0
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-phycore-som-2gb"
CONFIG_SPL_TEXT_BASE=0x70000000
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x190000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_MAX_SIZE=0x180000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x7019b800
CONFIG_SPL_BSS_MAX_SIZE=0x4000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL"
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_ESM_K3=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PHY_TI_DP83867=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_SIERRA=y
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_HOST=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384

15
include/configs/phycore_am64x.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration header file for PHYTEC phyCORE-AM64x kit
*
* Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
#ifndef __PHYCORE_AM64X_H
#define __PHYCORE_AM64X_H
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
#endif /* __PHYCORE_AM64X_H */