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ColdFire: Add MCF547x_8x related header files
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off by: John Rigby <jrigby@freescale.com>
This commit is contained in:
TsiChungLiew
parent
570c0186ae
commit
4621fc3fe7
@ -39,20 +39,20 @@ typedef struct cpm_buf_desc {
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uint cbd_bufaddr; /* Buffer address in host memory */
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} cbd_t;
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#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
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#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
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#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
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#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
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#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
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#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
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/* Buffer descriptor control/status used by Ethernet receive.
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*/
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@ -95,11 +95,8 @@ typedef struct cpm_buf_desc {
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#define BD_ENET_TX_CSL ((ushort)0x0001)
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#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
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#ifdef CONFIG_MCFFEC
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/*********************************************************************
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*
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* Fast Ethernet Controller (FEC)
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*
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*********************************************************************/
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/* FEC private information */
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struct fec_info_s {
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@ -117,8 +114,10 @@ struct fec_info_s {
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uint txIdx;
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char *txbuf;
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int initialized;
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struct fec_info_s *next;
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};
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#ifdef CONFIG_MCFFEC
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/* Register read/write struct */
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typedef struct fec {
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#ifdef CONFIG_M5272
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@ -254,90 +253,91 @@ typedef struct fec {
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u32 ieee_r_fdxfc;
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u32 ieee_r_octets_ok;
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} fec_t;
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#endif /* CONFIG_MCFFEC */
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/*********************************************************************
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* Fast Ethernet Controller (FEC)
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*********************************************************************/
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/* Bit definitions and macros for FEC_EIR */
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#define FEC_EIR_CLEAR_ALL (0xFFF80000)
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#define FEC_EIR_HBERR (0x80000000)
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#define FEC_EIR_BABR (0x40000000)
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#define FEC_EIR_BABT (0x20000000)
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#define FEC_EIR_GRA (0x10000000)
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#define FEC_EIR_TXF (0x08000000)
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#define FEC_EIR_TXB (0x04000000)
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#define FEC_EIR_RXF (0x02000000)
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#define FEC_EIR_RXB (0x01000000)
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#define FEC_EIR_MII (0x00800000)
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#define FEC_EIR_EBERR (0x00400000)
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#define FEC_EIR_LC (0x00200000)
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#define FEC_EIR_RL (0x00100000)
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#define FEC_EIR_UN (0x00080000)
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#define FEC_EIR_CLEAR_ALL (0xFFF80000)
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#define FEC_EIR_HBERR (0x80000000)
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#define FEC_EIR_BABR (0x40000000)
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#define FEC_EIR_BABT (0x20000000)
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#define FEC_EIR_GRA (0x10000000)
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#define FEC_EIR_TXF (0x08000000)
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#define FEC_EIR_TXB (0x04000000)
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#define FEC_EIR_RXF (0x02000000)
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#define FEC_EIR_RXB (0x01000000)
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#define FEC_EIR_MII (0x00800000)
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#define FEC_EIR_EBERR (0x00400000)
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#define FEC_EIR_LC (0x00200000)
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#define FEC_EIR_RL (0x00100000)
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#define FEC_EIR_UN (0x00080000)
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/* Bit definitions and macros for FEC_RDAR */
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#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
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#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for FEC_TDAR */
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#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
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#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for FEC_ECR */
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#define FEC_ECR_ETHER_EN (0x00000002)
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#define FEC_ECR_RESET (0x00000001)
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#define FEC_ECR_ETHER_EN (0x00000002)
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#define FEC_ECR_RESET (0x00000001)
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/* Bit definitions and macros for FEC_MMFR */
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#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
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#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
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#define FEC_MMFR_ST_01 (0x40000000)
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#define FEC_MMFR_OP_RD (0x20000000)
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#define FEC_MMFR_OP_WR (0x10000000)
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#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
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#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
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#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
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#define FEC_MMFR_TA_10 (0x00020000)
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#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
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#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
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#define FEC_MMFR_ST_01 (0x40000000)
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#define FEC_MMFR_OP_RD (0x20000000)
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#define FEC_MMFR_OP_WR (0x10000000)
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#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
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#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
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#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
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#define FEC_MMFR_TA_10 (0x00020000)
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/* Bit definitions and macros for FEC_MSCR */
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#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
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#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
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#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
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#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
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/* Bit definitions and macros for FEC_MIBC */
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#define FEC_MIBC_MIB_DISABLE (0x80000000)
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#define FEC_MIBC_MIB_IDLE (0x40000000)
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#define FEC_MIBC_MIB_DISABLE (0x80000000)
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#define FEC_MIBC_MIB_IDLE (0x40000000)
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/* Bit definitions and macros for FEC_RCR */
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#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
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#define FEC_RCR_FCE (0x00000020)
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#define FEC_RCR_BC_REJ (0x00000010)
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#define FEC_RCR_PROM (0x00000008)
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#define FEC_RCR_MII_MODE (0x00000004)
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#define FEC_RCR_DRT (0x00000002)
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#define FEC_RCR_LOOP (0x00000001)
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#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
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#define FEC_RCR_FCE (0x00000020)
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#define FEC_RCR_BC_REJ (0x00000010)
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#define FEC_RCR_PROM (0x00000008)
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#define FEC_RCR_MII_MODE (0x00000004)
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#define FEC_RCR_DRT (0x00000002)
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#define FEC_RCR_LOOP (0x00000001)
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/* Bit definitions and macros for FEC_TCR */
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#define FEC_TCR_RFC_PAUSE (0x00000010)
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#define FEC_TCR_TFC_PAUSE (0x00000008)
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#define FEC_TCR_FDEN (0x00000004)
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#define FEC_TCR_HBC (0x00000002)
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#define FEC_TCR_GTS (0x00000001)
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#define FEC_TCR_RFC_PAUSE (0x00000010)
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#define FEC_TCR_TFC_PAUSE (0x00000008)
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#define FEC_TCR_FDEN (0x00000004)
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#define FEC_TCR_HBC (0x00000002)
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#define FEC_TCR_GTS (0x00000001)
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/* Bit definitions and macros for FEC_PAUR */
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#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
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#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
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#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
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#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
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/* Bit definitions and macros for FEC_OPD */
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#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
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#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
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#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
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#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for FEC_TFWR */
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#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
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#define FEC_TFWR_X_WMRK_64 (0x01)
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#define FEC_TFWR_X_WMRK_128 (0x02)
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#define FEC_TFWR_X_WMRK_192 (0x03)
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#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
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#define FEC_TFWR_X_WMRK_64 (0x01)
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#define FEC_TFWR_X_WMRK_128 (0x02)
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#define FEC_TFWR_X_WMRK_192 (0x03)
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/* Bit definitions and macros for FEC_FRBR */
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#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
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#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
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/* Bit definitions and macros for FEC_FRSR */
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#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
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#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
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/* Bit definitions and macros for FEC_ERDSR */
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#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
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@ -348,8 +348,7 @@ typedef struct fec {
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/* Bit definitions and macros for FEC_EMRBR */
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#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
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#define FEC_RESET_DELAY 100
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#define FEC_RX_TOUT 100
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#define FEC_RESET_DELAY 100
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#define FEC_RX_TOUT 100
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#endif /* CONFIG_MCFFEC */
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#endif /* fec_h */
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176
include/asm-m68k/fsl_mcdmafec.h
Normal file
176
include/asm-m68k/fsl_mcdmafec.h
Normal file
@ -0,0 +1,176 @@
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/*
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* fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef fsl_mcdmafec_h
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#define fsl_mcdmafec_h
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/* Re-use of the definitions */
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#include <asm/fec.h>
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typedef struct fecdma {
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u32 rsvd0; /* 0x000 */
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u32 eir; /* 0x004 */
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u32 eimr; /* 0x008 */
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u32 rsvd1[6]; /* 0x00C - 0x023 */
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u32 ecr; /* 0x024 */
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u32 rsvd2[6]; /* 0x028 - 0x03F */
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u32 mmfr; /* 0x040 */
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u32 mscr; /* 0x044 */
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u32 rsvd3[7]; /* 0x048 - 0x063 */
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u32 mibc; /* 0x064 */
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u32 rsvd4[7]; /* 0x068 - 0x083 */
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u32 rcr; /* 0x084 */
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u32 rhr; /* 0x088 */
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u32 rsvd5[14]; /* 0x08C - 0x0C3 */
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u32 tcr; /* 0x0C4 */
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u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
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u32 palr; /* 0x0E4 */
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u32 paur; /* 0x0E8 */
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u32 opd; /* 0x0EC */
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u32 rsvd7[10]; /* 0x0F0 - 0x117 */
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u32 iaur; /* 0x118 */
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u32 ialr; /* 0x11C */
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u32 gaur; /* 0x120 */
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u32 galr; /* 0x124 */
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u32 rsvd8[7]; /* 0x128 - 0x143 */
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u32 tfwr; /* 0x144 */
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u32 rsvd9[14]; /* 0x148 - 0x17F */
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u32 fmc; /* 0x180 */
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u32 rfdr; /* 0x184 */
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u32 rfsr; /* 0x188 */
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u32 rfcr; /* 0x18C */
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u32 rlrfp; /* 0x190 */
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u32 rlwfp; /* 0x194 */
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u32 rfar; /* 0x198 */
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u32 rfrp; /* 0x19C */
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u32 rfwp; /* 0x1A0 */
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u32 tfdr; /* 0x1A4 */
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u32 tfsr; /* 0x1A8 */
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u32 tfcr; /* 0x1AC */
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u32 tlrfp; /* 0x1B0 */
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u32 tlwfp; /* 0x1B4 */
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u32 tfar; /* 0x1B8 */
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u32 tfrp; /* 0x1BC */
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u32 tfwp; /* 0x1C0 */
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u32 frst; /* 0x1C4 */
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u32 ctcwr; /* 0x1C8 */
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} fecdma_t;
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struct fec_info_dma {
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int index;
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u32 iobase;
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u32 pinmux;
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u32 miibase;
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int phy_addr;
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int dup_spd;
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char *phy_name;
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int phyname_init;
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cbd_t *rxbd; /* Rx BD */
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cbd_t *txbd; /* Tx BD */
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uint rxIdx;
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uint txIdx;
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char *txbuf;
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int initialized;
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struct fec_info_dma *next;
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u16 rxTask; /* DMA receive Task Number */
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u16 txTask; /* DMA Transmit Task Number */
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u16 rxPri; /* DMA Receive Priority */
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u16 txPri; /* DMA Transmit Priority */
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u16 rxInit; /* DMA Receive Initiator */
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u16 txInit; /* DMA Transmit Initiator */
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u16 usedTbdIdx; /* next transmit BD to clean */
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u16 cleanTbdNum; /* the number of available transmit BDs */
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};
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/* Bit definitions and macros for IEVENT */
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#define FEC_EIR_TXERR (0x00040000)
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#define FEC_EIR_RXERR (0x00020000)
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#undef FEC_EIR_CLEAR_ALL
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#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
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/* Bit definitions and macros for R_HASH */
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#define FEC_RHASH_FCE_DC (0x80000000)
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#define FEC_RHASH_MULTCAST (0x40000000)
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#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
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/* Bit definitions and macros for FEC_TFWR */
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#undef FEC_TFWR_X_WMRK
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#undef FEC_TFWR_X_WMRK_64
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#undef FEC_TFWR_X_WMRK_128
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#undef FEC_TFWR_X_WMRK_192
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#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
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#define FEC_TFWR_X_WMRK_64 (0x00)
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#define FEC_TFWR_X_WMRK_128 (0x01)
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#define FEC_TFWR_X_WMRK_192 (0x02)
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#define FEC_TFWR_X_WMRK_256 (0x03)
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#define FEC_TFWR_X_WMRK_320 (0x04)
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#define FEC_TFWR_X_WMRK_384 (0x05)
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#define FEC_TFWR_X_WMRK_448 (0x06)
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#define FEC_TFWR_X_WMRK_512 (0x07)
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#define FEC_TFWR_X_WMRK_576 (0x08)
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#define FEC_TFWR_X_WMRK_640 (0x09)
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#define FEC_TFWR_X_WMRK_704 (0x0A)
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#define FEC_TFWR_X_WMRK_768 (0x0B)
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#define FEC_TFWR_X_WMRK_832 (0x0C)
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#define FEC_TFWR_X_WMRK_896 (0x0D)
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#define FEC_TFWR_X_WMRK_960 (0x0E)
|
||||
#define FEC_TFWR_X_WMRK_1024 (0x0F)
|
||||
|
||||
/* FIFO definitions */
|
||||
/* Bit definitions and macros for FSTAT */
|
||||
#define FIFO_STAT_IP (0x80000000)
|
||||
#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
|
||||
#define FIFO_STAT_FAE (0x00800000)
|
||||
#define FIFO_STAT_RXW (0x00400000)
|
||||
#define FIFO_STAT_UF (0x00200000)
|
||||
#define FIFO_STAT_OF (0x00100000)
|
||||
#define FIFO_STAT_FR (0x00080000)
|
||||
#define FIFO_STAT_FULL (0x00040000)
|
||||
#define FIFO_STAT_ALARM (0x00020000)
|
||||
#define FIFO_STAT_EMPTY (0x00010000)
|
||||
|
||||
/* Bit definitions and macros for FCTRL */
|
||||
#define FIFO_CTRL_WCTL (0x40000000)
|
||||
#define FIFO_CTRL_WFR (0x20000000)
|
||||
#define FIFO_CTRL_FRAME (0x08000000)
|
||||
#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
|
||||
#define FIFO_CTRL_IPMASK (0x00800000)
|
||||
#define FIFO_CTRL_FAEMASK (0x00400000)
|
||||
#define FIFO_CTRL_RXWMASK (0x00200000)
|
||||
#define FIFO_CTRL_UFMASK (0x00100000)
|
||||
#define FIFO_CTRL_OFMASK (0x00080000)
|
||||
|
||||
int fecpin_setclear(struct eth_device *dev, int setclear);
|
||||
void mii_init(void);
|
||||
uint mii_send(uint mii_cmd);
|
||||
int mii_discover_phy(struct eth_device *dev);
|
||||
int mcffec_miiphy_read(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short *value);
|
||||
int mcffec_miiphy_write(char *devname, unsigned char addr,
|
||||
unsigned char reg, unsigned short value);
|
||||
|
||||
#endif /* fsl_mcdmafec_h */
|
||||
@ -273,4 +273,97 @@
|
||||
#endif
|
||||
#endif /* CONFIG_M54455 */
|
||||
|
||||
#ifdef CONFIG_M547x
|
||||
#include <asm/immap_547x_8x.h>
|
||||
#include <asm/m547x_8x.h>
|
||||
|
||||
#ifdef CONFIG_FSLDMAFEC
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC0)
|
||||
#define CFG_FEC1_IOBASE (MMAP_FEC1)
|
||||
|
||||
#define FEC0_RX_TASK 0
|
||||
#define FEC0_TX_TASK 1
|
||||
#define FEC0_RX_PRIORITY 6
|
||||
#define FEC0_TX_PRIORITY 7
|
||||
#define FEC0_RX_INIT 16
|
||||
#define FEC0_TX_INIT 17
|
||||
#define FEC1_RX_TASK 2
|
||||
#define FEC1_TX_TASK 3
|
||||
#define FEC1_RX_PRIORITY 6
|
||||
#define FEC1_TX_PRIORITY 7
|
||||
#define FEC1_RX_INIT 30
|
||||
#define FEC1_TX_INIT 31
|
||||
#endif
|
||||
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100))
|
||||
|
||||
#ifdef CONFIG_SLTTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_SLT1)
|
||||
#define CFG_TMR_BASE (MMAP_SLT0)
|
||||
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
|
||||
#define CFG_TMRINTR_NO (INT0_HI_SLT0)
|
||||
#define CFG_TMRINTR_MASK (INTC_IPRH_INT54)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (0x1E)
|
||||
#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000)
|
||||
#endif
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CFG_PCI_BAR0 (0x40000000)
|
||||
#define CFG_PCI_BAR1 (CFG_SDRAM_BASE)
|
||||
#define CFG_PCI_TBATR0 (CFG_MBAR)
|
||||
#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE)
|
||||
#endif
|
||||
#endif /* CONFIG_M547x */
|
||||
|
||||
#ifdef CONFIG_M548x
|
||||
#include <asm/immap_547x_8x.h>
|
||||
#include <asm/m547x_8x.h>
|
||||
|
||||
#ifdef CONFIG_FSLDMAFEC
|
||||
#define CFG_FEC0_IOBASE (MMAP_FEC0)
|
||||
#define CFG_FEC1_IOBASE (MMAP_FEC1)
|
||||
|
||||
#define FEC0_RX_TASK 0
|
||||
#define FEC0_TX_TASK 1
|
||||
#define FEC0_RX_PRIORITY 6
|
||||
#define FEC0_TX_PRIORITY 7
|
||||
#define FEC0_RX_INIT 16
|
||||
#define FEC0_TX_INIT 17
|
||||
#define FEC1_RX_TASK 2
|
||||
#define FEC1_TX_TASK 3
|
||||
#define FEC1_RX_PRIORITY 6
|
||||
#define FEC1_TX_PRIORITY 7
|
||||
#define FEC1_RX_INIT 30
|
||||
#define FEC1_TX_INIT 31
|
||||
#endif
|
||||
|
||||
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100))
|
||||
|
||||
/* Timer */
|
||||
#ifdef CONFIG_SLTTMR
|
||||
#define CFG_UDELAY_BASE (MMAP_SLT1)
|
||||
#define CFG_TMR_BASE (MMAP_SLT0)
|
||||
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
|
||||
#define CFG_TMRINTR_NO (INT0_HI_SLT0)
|
||||
#define CFG_TMRINTR_MASK (INTC_IPRH_INT54)
|
||||
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
|
||||
#define CFG_TMRINTR_PRI (0x1E)
|
||||
#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000)
|
||||
#endif
|
||||
|
||||
#define CFG_INTR_BASE (MMAP_INTC0)
|
||||
#define CFG_NUM_IRQS (128)
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CFG_PCI_BAR0 (CFG_MBAR)
|
||||
#define CFG_PCI_BAR1 (CFG_SDRAM_BASE)
|
||||
#define CFG_PCI_TBATR0 (CFG_MBAR)
|
||||
#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE)
|
||||
#endif
|
||||
#endif /* CONFIG_M548x */
|
||||
|
||||
#endif /* __IMMAP_H */
|
||||
|
||||
297
include/asm-m68k/immap_547x_8x.h
Normal file
297
include/asm-m68k/immap_547x_8x.h
Normal file
@ -0,0 +1,297 @@
|
||||
/*
|
||||
* MCF547x_8x Internal Memory Map
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __IMMAP_547x_8x__
|
||||
#define __IMMAP_547x_8x__
|
||||
|
||||
#define MMAP_SIU (CFG_MBAR + 0x00000000)
|
||||
#define MMAP_SDRAM (CFG_MBAR + 0x00000100)
|
||||
#define MMAP_XARB (CFG_MBAR + 0x00000240)
|
||||
#define MMAP_FBCS (CFG_MBAR + 0x00000500)
|
||||
#define MMAP_INTC0 (CFG_MBAR + 0x00000700)
|
||||
#define MMAP_GPTMR (CFG_MBAR + 0x00000800)
|
||||
#define MMAP_SLT0 (CFG_MBAR + 0x00000900)
|
||||
#define MMAP_SLT1 (CFG_MBAR + 0x00000910)
|
||||
#define MMAP_GPIO (CFG_MBAR + 0x00000A00)
|
||||
#define MMAP_PCI (CFG_MBAR + 0x00000B00)
|
||||
#define MMAP_PCIARB (CFG_MBAR + 0x00000C00)
|
||||
#define MMAP_EXTDMA (CFG_MBAR + 0x00000D00)
|
||||
#define MMAP_EPORT (CFG_MBAR + 0x00000F00)
|
||||
#define MMAP_CTM (CFG_MBAR + 0x00007F00)
|
||||
#define MMAP_MCDMA (CFG_MBAR + 0x00008000)
|
||||
#define MMAP_SCPCI (CFG_MBAR + 0x00008400)
|
||||
#define MMAP_UART0 (CFG_MBAR + 0x00008600)
|
||||
#define MMAP_UART1 (CFG_MBAR + 0x00008700)
|
||||
#define MMAP_UART2 (CFG_MBAR + 0x00008800)
|
||||
#define MMAP_UART3 (CFG_MBAR + 0x00008900)
|
||||
#define MMAP_DSPI (CFG_MBAR + 0x00008A00)
|
||||
#define MMAP_I2C (CFG_MBAR + 0x00008F00)
|
||||
#define MMAP_FEC0 (CFG_MBAR + 0x00009000)
|
||||
#define MMAP_FEC1 (CFG_MBAR + 0x00009800)
|
||||
#define MMAP_CAN0 (CFG_MBAR + 0x0000A000)
|
||||
#define MMAP_CAN1 (CFG_MBAR + 0x0000A800)
|
||||
#define MMAP_USBD (CFG_MBAR + 0x0000B000)
|
||||
#define MMAP_SRAM (CFG_MBAR + 0x00010000)
|
||||
#define MMAP_SRAMCFG (CFG_MBAR + 0x0001FF00)
|
||||
#define MMAP_SEC (CFG_MBAR + 0x00020000)
|
||||
|
||||
#include <asm/coldfire/flexbus.h>
|
||||
|
||||
typedef struct siu {
|
||||
u32 mbar; /* 0x00 */
|
||||
u32 drv; /* 0x04 */
|
||||
u32 rsvd1[2]; /* 0x08 - 0x1F */
|
||||
u32 sbcr; /* 0x10 */
|
||||
u32 rsvd2[3]; /* 0x14 - 0x1F */
|
||||
u32 cs0cfg; /* 0x20 */
|
||||
u32 cs1cfg; /* 0x24 */
|
||||
u32 cs2cfg; /* 0x28 */
|
||||
u32 cs3cfg; /* 0x2C */
|
||||
u32 rsvd3[2]; /* 0x30 - 0x37 */
|
||||
u32 secsacr; /* 0x38 */
|
||||
u32 rsvd4[2]; /* 0x3C - 0x43 */
|
||||
u32 rsr; /* 0x44 */
|
||||
u32 rsvd5[2]; /* 0x48 - 0x4F */
|
||||
u32 jtagid; /* 0x50 */
|
||||
} siu_t;
|
||||
|
||||
typedef struct sdram {
|
||||
u32 mode; /* 0x00 */
|
||||
u32 ctrl; /* 0x04 */
|
||||
u32 cfg1; /* 0x08 */
|
||||
u32 cfg2; /* 0x0c */
|
||||
} sdram_t;
|
||||
|
||||
typedef struct xlb_arb {
|
||||
u32 cfg; /* 0x240 */
|
||||
u32 ver; /* 0x244 */
|
||||
u32 sr; /* 0x248 */
|
||||
u32 imr; /* 0x24c */
|
||||
u32 adrcap; /* 0x250 */
|
||||
u32 sigcap; /* 0x254 */
|
||||
u32 adrto; /* 0x258 */
|
||||
u32 datto; /* 0x25c */
|
||||
u32 busto; /* 0x260 */
|
||||
u32 prien; /* 0x264 */
|
||||
u32 pri; /* 0x268 */
|
||||
} xlbarb_t;
|
||||
|
||||
typedef struct int0_ctrl {
|
||||
u32 iprh0; /* 0x00 */
|
||||
u32 iprl0; /* 0x04 */
|
||||
u32 imrh0; /* 0x08 */
|
||||
u32 imrl0; /* 0x0C */
|
||||
u32 frch0; /* 0x10 */
|
||||
u32 frcl0; /* 0x14 */
|
||||
u8 irlr; /* 0x18 */
|
||||
u8 iacklpr; /* 0x19 */
|
||||
u16 res1; /* 0x1A - 0x1B */
|
||||
u32 res2[9]; /* 0x1C - 0x3F */
|
||||
u8 icr0[64]; /* 0x40 - 0x7F */
|
||||
u32 res3[24]; /* 0x80 - 0xDF */
|
||||
u8 swiack0; /* 0xE0 */
|
||||
u8 res4[3]; /* 0xE1 - 0xE3 */
|
||||
u8 Lniack0_1; /* 0xE4 */
|
||||
u8 res5[3]; /* 0xE5 - 0xE7 */
|
||||
u8 Lniack0_2; /* 0xE8 */
|
||||
u8 res6[3]; /* 0xE9 - 0xEB */
|
||||
u8 Lniack0_3; /* 0xEC */
|
||||
u8 res7[3]; /* 0xED - 0xEF */
|
||||
u8 Lniack0_4; /* 0xF0 */
|
||||
u8 res8[3]; /* 0xF1 - 0xF3 */
|
||||
u8 Lniack0_5; /* 0xF4 */
|
||||
u8 res9[3]; /* 0xF5 - 0xF7 */
|
||||
u8 Lniack0_6; /* 0xF8 */
|
||||
u8 resa[3]; /* 0xF9 - 0xFB */
|
||||
u8 Lniack0_7; /* 0xFC */
|
||||
u8 resb[3]; /* 0xFD - 0xFF */
|
||||
} int0_t;
|
||||
|
||||
typedef struct gptmr {
|
||||
u8 ocpw;
|
||||
u8 octict;
|
||||
u8 ctrl;
|
||||
u8 mode;
|
||||
|
||||
u16 pre; /* Prescale */
|
||||
u16 cnt;
|
||||
|
||||
u16 pwmwidth;
|
||||
u8 pwmop; /* Output Polarity */
|
||||
u8 pwmld; /* Immediate Update */
|
||||
|
||||
u16 cap; /* Capture internal counter */
|
||||
u8 ovfpin; /* Ovf and Pin */
|
||||
u8 intr; /* Interrupts */
|
||||
} gptmr_t;
|
||||
|
||||
typedef struct slt {
|
||||
u32 tcnt; /* 0x00 */
|
||||
u32 cr; /* 0x04 */
|
||||
u32 cnt; /* 0x08 */
|
||||
u32 sr; /* 0x0C */
|
||||
} slt_t;
|
||||
|
||||
typedef struct gpio {
|
||||
/* Port Output Data Registers */
|
||||
u8 podr_fbctl; /*0x00 */
|
||||
u8 podr_fbcs; /*0x01 */
|
||||
u8 podr_dma; /*0x02 */
|
||||
u8 rsvd1; /*0x03 */
|
||||
u8 podr_fec0h; /*0x04 */
|
||||
u8 podr_fec0l; /*0x05 */
|
||||
u8 podr_fec1h; /*0x06 */
|
||||
u8 podr_fec1l; /*0x07 */
|
||||
u8 podr_feci2c; /*0x08 */
|
||||
u8 podr_pcibg; /*0x09 */
|
||||
u8 podr_pcibr; /*0x0A */
|
||||
u8 rsvd2; /*0x0B */
|
||||
u8 podr_psc3psc2; /*0x0C */
|
||||
u8 podr_psc1psc0; /*0x0D */
|
||||
u8 podr_dspi; /*0x0E */
|
||||
u8 rsvd3; /*0x0F */
|
||||
|
||||
/* Port Data Direction Registers */
|
||||
u8 pddr_fbctl; /*0x10 */
|
||||
u8 pddr_fbcs; /*0x11 */
|
||||
u8 pddr_dma; /*0x12 */
|
||||
u8 rsvd4; /*0x13 */
|
||||
u8 pddr_fec0h; /*0x14 */
|
||||
u8 pddr_fec0l; /*0x15 */
|
||||
u8 pddr_fec1h; /*0x16 */
|
||||
u8 pddr_fec1l; /*0x17 */
|
||||
u8 pddr_feci2c; /*0x18 */
|
||||
u8 pddr_pcibg; /*0x19 */
|
||||
u8 pddr_pcibr; /*0x1A */
|
||||
u8 rsvd5; /*0x1B */
|
||||
u8 pddr_psc3psc2; /*0x1C */
|
||||
u8 pddr_psc1psc0; /*0x1D */
|
||||
u8 pddr_dspi; /*0x1E */
|
||||
u8 rsvd6; /*0x1F */
|
||||
|
||||
/* Port Pin Data/Set Data Registers */
|
||||
u8 ppdsdr_fbctl; /*0x20 */
|
||||
u8 ppdsdr_fbcs; /*0x21 */
|
||||
u8 ppdsdr_dma; /*0x22 */
|
||||
u8 rsvd7; /*0x23 */
|
||||
u8 ppdsdr_fec0h; /*0x24 */
|
||||
u8 ppdsdr_fec0l; /*0x25 */
|
||||
u8 ppdsdr_fec1h; /*0x26 */
|
||||
u8 ppdsdr_fec1l; /*0x27 */
|
||||
u8 ppdsdr_feci2c; /*0x28 */
|
||||
u8 ppdsdr_pcibg; /*0x29 */
|
||||
u8 ppdsdr_pcibr; /*0x2A */
|
||||
u8 rsvd8; /*0x2B */
|
||||
u8 ppdsdr_psc3psc2; /*0x2C */
|
||||
u8 ppdsdr_psc1psc0; /*0x2D */
|
||||
u8 ppdsdr_dspi; /*0x2E */
|
||||
u8 rsvd9; /*0x2F */
|
||||
|
||||
/* Port Clear Output Data Registers */
|
||||
u8 pclrr_fbctl; /*0x30 */
|
||||
u8 pclrr_fbcs; /*0x31 */
|
||||
u8 pclrr_dma; /*0x32 */
|
||||
u8 rsvd10; /*0x33 */
|
||||
u8 pclrr_fec0h; /*0x34 */
|
||||
u8 pclrr_fec0l; /*0x35 */
|
||||
u8 pclrr_fec1h; /*0x36 */
|
||||
u8 pclrr_fec1l; /*0x37 */
|
||||
u8 pclrr_feci2c; /*0x38 */
|
||||
u8 pclrr_pcibg; /*0x39 */
|
||||
u8 pclrr_pcibr; /*0x3A */
|
||||
u8 rsvd11; /*0x3B */
|
||||
u8 pclrr_psc3psc2; /*0x3C */
|
||||
u8 pclrr_psc1psc0; /*0x3D */
|
||||
u8 pclrr_dspi; /*0x3E */
|
||||
u8 rsvd12; /*0x3F */
|
||||
|
||||
/* Pin Assignment Registers */
|
||||
u16 par_fbctl; /*0x40 */
|
||||
u8 par_fbcs; /*0x42 */
|
||||
u8 par_dma; /*0x43 */
|
||||
u16 par_feci2cirq; /*0x44 */
|
||||
u16 rsvd13; /*0x46 */
|
||||
u16 par_pcibg; /*0x48 */
|
||||
u16 par_pcibr; /*0x4A */
|
||||
u8 par_psc3; /*0x4C */
|
||||
u8 par_psc2; /*0x4D */
|
||||
u8 par_psc1; /*0x4E */
|
||||
u8 par_psc0; /*0x4F */
|
||||
u16 par_dspi; /*0x50 */
|
||||
u8 par_timer; /*0x52 */
|
||||
u8 rsvd14; /*0x53 */
|
||||
} gpio_t;
|
||||
|
||||
typedef struct pci {
|
||||
u32 idr; /* 0x00 Device Id / Vendor Id */
|
||||
u32 scr; /* 0x04 Status / command */
|
||||
u32 ccrir; /* 0x08 Class Code / Revision Id */
|
||||
u32 cr1; /* 0x0c Configuration 1 */
|
||||
u32 bar0; /* 0x10 Base address register 0 */
|
||||
u32 bar1; /* 0x14 Base address register 1 */
|
||||
u32 bar2; /* 0x18 NA */
|
||||
u32 bar3; /* 0x1c NA */
|
||||
u32 bar4; /* 0x20 NA */
|
||||
u32 bar5; /* 0x24 NA */
|
||||
u32 ccpr; /* 0x28 Cardbus CIS Pointer */
|
||||
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
|
||||
u32 erbar; /* 0x30 Expansion ROM Base Address */
|
||||
u32 cpr; /* 0x34 Capabilities Pointer */
|
||||
u32 rsvd1; /* 0x38 */
|
||||
u32 cr2; /* 0x3c Configuration 2 */
|
||||
u32 rsvd2[8]; /* 0x40 - 0x5f */
|
||||
|
||||
/* General control / status registers */
|
||||
u32 gscr; /* 0x60 Global Status / Control */
|
||||
u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
|
||||
u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
|
||||
u32 tcr1; /* 0x6c Target Control 1 Register */
|
||||
u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
|
||||
u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
|
||||
u32 iw2btar; /* 0x78 NA */
|
||||
u32 rsvd3; /* 0x7c */
|
||||
u32 iwcr; /* 0x80 Initiator Window Configuration */
|
||||
u32 icr; /* 0x84 Initiator Control */
|
||||
u32 isr; /* 0x88 Initiator Status */
|
||||
u32 tcr2; /* 0x8c NA */
|
||||
u32 tbatr0; /* 0x90 NA */
|
||||
u32 tbatr1; /* 0x94 NA */
|
||||
u32 tbatr2; /* 0x98 NA */
|
||||
u32 tbatr3; /* 0x9c NA */
|
||||
u32 tbatr4; /* 0xa0 NA */
|
||||
u32 tbatr5; /* 0xa4 NA */
|
||||
u32 intr; /* 0xa8 NA */
|
||||
u32 rsvd4[19]; /* 0xac - 0xf7 */
|
||||
u32 car; /* 0xf8 Configuration Address */
|
||||
} pci_t;
|
||||
|
||||
typedef struct pci_arbiter {
|
||||
/* Pci Arbiter Registers */
|
||||
union {
|
||||
u32 acr; /* Arbiter Control */
|
||||
u32 asr; /* Arbiter Status */
|
||||
};
|
||||
} pciarb_t;
|
||||
#endif /* __IMMAP_547x_8x__ */
|
||||
502
include/asm-m68k/m547x_8x.h
Normal file
502
include/asm-m68k/m547x_8x.h
Normal file
@ -0,0 +1,502 @@
|
||||
/*
|
||||
* mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
|
||||
*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef mcf547x_8x_h
|
||||
#define mcf547x_8x_h
|
||||
|
||||
/*********************************************************************
|
||||
* XLB Arbiter (XLB)
|
||||
*********************************************************************/
|
||||
/* Bit definitions and macros for XARB_CFG */
|
||||
#define XARB_CFG_AT (0x00000002)
|
||||
#define XARB_CFG_DT (0x00000004)
|
||||
#define XARB_CFG_BA (0x00000008)
|
||||
#define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
|
||||
#define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
|
||||
#define XARB_CFG_PLDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for XARB_SR */
|
||||
#define XARB_SR_AT (0x00000001)
|
||||
#define XARB_SR_DT (0x00000002)
|
||||
#define XARB_SR_BA (0x00000004)
|
||||
#define XARB_SR_TTM (0x00000008)
|
||||
#define XARB_SR_ECW (0x00000010)
|
||||
#define XARB_SR_TTR (0x00000020)
|
||||
#define XARB_SR_TTA (0x00000040)
|
||||
#define XARB_SR_MM (0x00000080)
|
||||
#define XARB_SR_SEA (0x00000100)
|
||||
|
||||
/* Bit definitions and macros for XARB_IMR */
|
||||
#define XARB_IMR_ATE (0x00000001)
|
||||
#define XARB_IMR_DTE (0x00000002)
|
||||
#define XARB_IMR_BAE (0x00000004)
|
||||
#define XARB_IMR_TTME (0x00000008)
|
||||
#define XARB_IMR_ECWE (0x00000010)
|
||||
#define XARB_IMR_TTRE (0x00000020)
|
||||
#define XARB_IMR_TTAE (0x00000040)
|
||||
#define XARB_IMR_MME (0x00000080)
|
||||
#define XARB_IMR_SEAE (0x00000100)
|
||||
|
||||
/* Bit definitions and macros for XARB_SIGCAP */
|
||||
#define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
|
||||
#define XARB_SIGCAP_TBST (0x00000020)
|
||||
#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
|
||||
|
||||
/* Bit definitions and macros for XARB_PRIEN */
|
||||
#define XARB_PRIEN_M0 (0x00000001)
|
||||
#define XARB_PRIEN_M2 (0x00000004)
|
||||
#define XARB_PRIEN_M3 (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for XARB_PRI */
|
||||
#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
|
||||
#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
|
||||
#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
|
||||
|
||||
/*********************************************************************
|
||||
* General Purpose I/O (GPIO)
|
||||
*********************************************************************/
|
||||
/* Bit definitions and macros for GPIO_PAR_FBCTL */
|
||||
#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
|
||||
#define GPIO_PAR_FBCTL_TA (0x0004)
|
||||
#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
|
||||
#define GPIO_PAR_FBCTL_OE (0x0040)
|
||||
#define GPIO_PAR_FBCTL_BWE0 (0x0100)
|
||||
#define GPIO_PAR_FBCTL_BWE1 (0x0400)
|
||||
#define GPIO_PAR_FBCTL_BWE2 (0x1000)
|
||||
#define GPIO_PAR_FBCTL_BWE3 (0x4000)
|
||||
#define GPIO_PAR_FBCTL_TS_GPIO (0)
|
||||
#define GPIO_PAR_FBCTL_TS_TBST (2)
|
||||
#define GPIO_PAR_FBCTL_TS_TS (3)
|
||||
#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
|
||||
#define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
|
||||
#define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_FBCS */
|
||||
#define GPIO_PAR_FBCS_CS1 (0x02)
|
||||
#define GPIO_PAR_FBCS_CS2 (0x04)
|
||||
#define GPIO_PAR_FBCS_CS3 (0x08)
|
||||
#define GPIO_PAR_FBCS_CS4 (0x10)
|
||||
#define GPIO_PAR_FBCS_CS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_DMA */
|
||||
#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
|
||||
#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
|
||||
#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
|
||||
#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
|
||||
#define GPIO_PAR_DMA_DACKx_GPIO (0)
|
||||
#define GPIO_PAR_DMA_DACKx_TOUT (2)
|
||||
#define GPIO_PAR_DMA_DACKx_DACK (3)
|
||||
#define GPIO_PAR_DMA_DREQx_GPIO (0)
|
||||
#define GPIO_PAR_DMA_DREQx_TIN (2)
|
||||
#define GPIO_PAR_DMA_DREQx_DREQ (3)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
|
||||
#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
|
||||
#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
|
||||
#define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
|
||||
#define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
|
||||
#define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
|
||||
#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
|
||||
#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
|
||||
#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
|
||||
#define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
|
||||
#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_PCIBG */
|
||||
#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
|
||||
#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
|
||||
#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
|
||||
#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
|
||||
#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_PCIBR */
|
||||
#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
|
||||
#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
|
||||
#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
|
||||
#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
|
||||
#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_PSC3 */
|
||||
#define GPIO_PAR_PSC3_TXD3 (0x04)
|
||||
#define GPIO_PAR_PSC3_RXD3 (0x08)
|
||||
#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
|
||||
#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
|
||||
#define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
|
||||
#define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
|
||||
#define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
|
||||
#define GPIO_PAR_PSC3_RTS3_RTS (0x30)
|
||||
#define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_PSC2 */
|
||||
#define GPIO_PAR_PSC2_TXD2 (0x04)
|
||||
#define GPIO_PAR_PSC2_RXD2 (0x08)
|
||||
#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
|
||||
#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
|
||||
#define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
|
||||
#define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
|
||||
#define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
|
||||
#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
|
||||
#define GPIO_PAR_PSC2_RTS2_RTS (0x30)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_PSC1 */
|
||||
#define GPIO_PAR_PSC1_TXD1 (0x04)
|
||||
#define GPIO_PAR_PSC1_RXD1 (0x08)
|
||||
#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
|
||||
#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
|
||||
#define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
|
||||
#define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
|
||||
#define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
|
||||
#define GPIO_PAR_PSC1_RTS1_RTS (0x30)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_PSC0 */
|
||||
#define GPIO_PAR_PSC0_TXD0 (0x04)
|
||||
#define GPIO_PAR_PSC0_RXD0 (0x08)
|
||||
#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
|
||||
#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
|
||||
#define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
|
||||
#define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
|
||||
#define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
|
||||
#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
|
||||
#define GPIO_PAR_PSC0_RTS0_RTS (0x30)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_DSPI */
|
||||
#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
|
||||
#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
|
||||
#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
|
||||
#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
|
||||
#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
|
||||
#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
|
||||
#define GPIO_PAR_DSPI_CS5 (0x1000)
|
||||
#define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
|
||||
#define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
|
||||
#define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
|
||||
#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
|
||||
#define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
|
||||
#define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
|
||||
#define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
|
||||
#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
|
||||
#define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
|
||||
#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
|
||||
#define GPIO_PAR_DSPI_CS0_RTS (0x0080)
|
||||
#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
|
||||
#define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
|
||||
#define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
|
||||
#define GPIO_PAR_DSPI_SCK_CTS (0x0020)
|
||||
#define GPIO_PAR_DSPI_SCK_SCK (0x0030)
|
||||
#define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
|
||||
#define GPIO_PAR_DSPI_SIN_RXD (0x0008)
|
||||
#define GPIO_PAR_DSPI_SIN_SIN (0x000C)
|
||||
#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
|
||||
#define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
|
||||
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
|
||||
|
||||
/* Bit definitions and macros for GPIO_PAR_TIMER */
|
||||
#define GPIO_PAR_TIMER_TOUT2 (0x01)
|
||||
#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
|
||||
#define GPIO_PAR_TIMER_TOUT3 (0x08)
|
||||
#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
|
||||
#define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
|
||||
#define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
|
||||
#define GPIO_PAR_TIMER_TIN3_TIN (0x30)
|
||||
#define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
|
||||
#define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
|
||||
#define GPIO_PAR_TIMER_TIN2_TIN (0x06)
|
||||
|
||||
/*********************************************************************
|
||||
* Slice Timer (SLT)
|
||||
*********************************************************************/
|
||||
#define SLT_CR_RUN (0x04000000)
|
||||
#define SLT_CR_IEN (0x02000000)
|
||||
#define SLT_CR_TEN (0x01000000)
|
||||
|
||||
#define SLT_SR_BE (0x02000000)
|
||||
#define SLT_SR_ST (0x01000000)
|
||||
|
||||
/*********************************************************************
|
||||
* Interrupt Controller (INTC)
|
||||
*********************************************************************/
|
||||
#define INT0_LO_RSVD0 (0)
|
||||
#define INT0_LO_EPORT1 (1)
|
||||
#define INT0_LO_EPORT2 (2)
|
||||
#define INT0_LO_EPORT3 (3)
|
||||
#define INT0_LO_EPORT4 (4)
|
||||
#define INT0_LO_EPORT5 (5)
|
||||
#define INT0_LO_EPORT6 (6)
|
||||
#define INT0_LO_EPORT7 (7)
|
||||
#define INT0_LO_EP0ISR (15)
|
||||
#define INT0_LO_EP1ISR (16)
|
||||
#define INT0_LO_EP2ISR (17)
|
||||
#define INT0_LO_EP3ISR (18)
|
||||
#define INT0_LO_EP4ISR (19)
|
||||
#define INT0_LO_EP5ISR (20)
|
||||
#define INT0_LO_EP6ISR (21)
|
||||
#define INT0_LO_USBISR (22)
|
||||
#define INT0_LO_USBAISR (23)
|
||||
#define INT0_LO_USB (24)
|
||||
#define INT1_LO_DSPI_RFOF_TFUF (25)
|
||||
#define INT1_LO_DSPI_RFOF (26)
|
||||
#define INT1_LO_DSPI_RFDF (27)
|
||||
#define INT1_LO_DSPI_TFUF (28)
|
||||
#define INT1_LO_DSPI_TCF (29)
|
||||
#define INT1_LO_DSPI_TFFF (30)
|
||||
#define INT1_LO_DSPI_EOQF (31)
|
||||
|
||||
#define INT0_HI_UART3 (32)
|
||||
#define INT0_HI_UART2 (33)
|
||||
#define INT0_HI_UART1 (34)
|
||||
#define INT0_HI_UART0 (35)
|
||||
#define INT0_HI_COMMTIM_TC (36)
|
||||
#define INT0_HI_SEC (37)
|
||||
#define INT0_HI_FEC1 (38)
|
||||
#define INT0_HI_FEC0 (39)
|
||||
#define INT0_HI_I2C (40)
|
||||
#define INT0_HI_PCIARB (41)
|
||||
#define INT0_HI_CBPCI (42)
|
||||
#define INT0_HI_XLBPCI (43)
|
||||
#define INT0_HI_XLBARB (47)
|
||||
#define INT0_HI_DMA (48)
|
||||
#define INT0_HI_CAN0_ERROR (49)
|
||||
#define INT0_HI_CAN0_BUSOFF (50)
|
||||
#define INT0_HI_CAN0_MBOR (51)
|
||||
#define INT0_HI_SLT1 (53)
|
||||
#define INT0_HI_SLT0 (54)
|
||||
#define INT0_HI_CAN1_ERROR (55)
|
||||
#define INT0_HI_CAN1_BUSOFF (56)
|
||||
#define INT0_HI_CAN1_MBOR (57)
|
||||
#define INT0_HI_GPT3 (59)
|
||||
#define INT0_HI_GPT2 (60)
|
||||
#define INT0_HI_GPT1 (61)
|
||||
#define INT0_HI_GPT0 (62)
|
||||
|
||||
/* Bit definitions and macros for IPRH */
|
||||
#define INTC_IPRH_INT32 (0x00000001)
|
||||
#define INTC_IPRH_INT33 (0x00000002)
|
||||
#define INTC_IPRH_INT34 (0x00000004)
|
||||
#define INTC_IPRH_INT35 (0x00000008)
|
||||
#define INTC_IPRH_INT36 (0x00000010)
|
||||
#define INTC_IPRH_INT37 (0x00000020)
|
||||
#define INTC_IPRH_INT38 (0x00000040)
|
||||
#define INTC_IPRH_INT39 (0x00000080)
|
||||
#define INTC_IPRH_INT40 (0x00000100)
|
||||
#define INTC_IPRH_INT41 (0x00000200)
|
||||
#define INTC_IPRH_INT42 (0x00000400)
|
||||
#define INTC_IPRH_INT43 (0x00000800)
|
||||
#define INTC_IPRH_INT44 (0x00001000)
|
||||
#define INTC_IPRH_INT45 (0x00002000)
|
||||
#define INTC_IPRH_INT46 (0x00004000)
|
||||
#define INTC_IPRH_INT47 (0x00008000)
|
||||
#define INTC_IPRH_INT48 (0x00010000)
|
||||
#define INTC_IPRH_INT49 (0x00020000)
|
||||
#define INTC_IPRH_INT50 (0x00040000)
|
||||
#define INTC_IPRH_INT51 (0x00080000)
|
||||
#define INTC_IPRH_INT52 (0x00100000)
|
||||
#define INTC_IPRH_INT53 (0x00200000)
|
||||
#define INTC_IPRH_INT54 (0x00400000)
|
||||
#define INTC_IPRH_INT55 (0x00800000)
|
||||
#define INTC_IPRH_INT56 (0x01000000)
|
||||
#define INTC_IPRH_INT57 (0x02000000)
|
||||
#define INTC_IPRH_INT58 (0x04000000)
|
||||
#define INTC_IPRH_INT59 (0x08000000)
|
||||
#define INTC_IPRH_INT60 (0x10000000)
|
||||
#define INTC_IPRH_INT61 (0x20000000)
|
||||
#define INTC_IPRH_INT62 (0x40000000)
|
||||
#define INTC_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for IPRL */
|
||||
#define INTC_IPRL_INT0 (0x00000001)
|
||||
#define INTC_IPRL_INT1 (0x00000002)
|
||||
#define INTC_IPRL_INT2 (0x00000004)
|
||||
#define INTC_IPRL_INT3 (0x00000008)
|
||||
#define INTC_IPRL_INT4 (0x00000010)
|
||||
#define INTC_IPRL_INT5 (0x00000020)
|
||||
#define INTC_IPRL_INT6 (0x00000040)
|
||||
#define INTC_IPRL_INT7 (0x00000080)
|
||||
#define INTC_IPRL_INT8 (0x00000100)
|
||||
#define INTC_IPRL_INT9 (0x00000200)
|
||||
#define INTC_IPRL_INT10 (0x00000400)
|
||||
#define INTC_IPRL_INT11 (0x00000800)
|
||||
#define INTC_IPRL_INT12 (0x00001000)
|
||||
#define INTC_IPRL_INT13 (0x00002000)
|
||||
#define INTC_IPRL_INT14 (0x00004000)
|
||||
#define INTC_IPRL_INT15 (0x00008000)
|
||||
#define INTC_IPRL_INT16 (0x00010000)
|
||||
#define INTC_IPRL_INT17 (0x00020000)
|
||||
#define INTC_IPRL_INT18 (0x00040000)
|
||||
#define INTC_IPRL_INT19 (0x00080000)
|
||||
#define INTC_IPRL_INT20 (0x00100000)
|
||||
#define INTC_IPRL_INT21 (0x00200000)
|
||||
#define INTC_IPRL_INT22 (0x00400000)
|
||||
#define INTC_IPRL_INT23 (0x00800000)
|
||||
#define INTC_IPRL_INT24 (0x01000000)
|
||||
#define INTC_IPRL_INT25 (0x02000000)
|
||||
#define INTC_IPRL_INT26 (0x04000000)
|
||||
#define INTC_IPRL_INT27 (0x08000000)
|
||||
#define INTC_IPRL_INT28 (0x10000000)
|
||||
#define INTC_IPRL_INT29 (0x20000000)
|
||||
#define INTC_IPRL_INT30 (0x40000000)
|
||||
#define INTC_IPRL_INT31 (0x80000000)
|
||||
|
||||
/*********************************************************************
|
||||
* General Purpose Timers (GPTMR)
|
||||
*********************************************************************/
|
||||
/* Enable and Mode Select */
|
||||
#define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
|
||||
#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
|
||||
#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
|
||||
#define GPT_CTRL_CE 0x10 /* Counter Enable */
|
||||
#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
|
||||
#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
|
||||
#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
|
||||
#define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
|
||||
#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
|
||||
#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
|
||||
#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
|
||||
#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
|
||||
|
||||
#define GPT_PWM_WIDTH(x) (x & 0xffff)
|
||||
|
||||
/* Status */
|
||||
#define GPT_STA_CAPTURE(x) (x & 0xffff)
|
||||
|
||||
#define GPT_OVFPIN_OVF(x) (x & 0x70)
|
||||
#define GPT_OVFPIN_PIN 0x01
|
||||
|
||||
#define GPT_INT_TEXP 0x08
|
||||
#define GPT_INT_PWMP 0x04
|
||||
#define GPT_INT_COMP 0x02
|
||||
#define GPT_INT_CAPT 0x01
|
||||
|
||||
/*********************************************************************
|
||||
* PCI
|
||||
*********************************************************************/
|
||||
|
||||
/* Bit definitions and macros for SCR */
|
||||
#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
|
||||
#define PCI_SCR_SE (0x40000000) /* System error signalled */
|
||||
#define PCI_SCR_MA (0x20000000) /* Master aboart received */
|
||||
#define PCI_SCR_TR (0x10000000) /* Target abort received */
|
||||
#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
|
||||
#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
|
||||
#define PCI_SCR_DP (0x01000000) /* Master data parity err */
|
||||
#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
|
||||
#define PCI_SCR_R (0x00400000) /* Reserved */
|
||||
#define PCI_SCR_66M (0x00200000) /* 66Mhz */
|
||||
#define PCI_SCR_C (0x00100000) /* Capabilities list */
|
||||
#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
|
||||
#define PCI_SCR_S (0x00000100) /* SERR enable */
|
||||
#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
|
||||
#define PCI_SCR_PER (0x00000040) /* Parity error response */
|
||||
#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
|
||||
#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
|
||||
#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
|
||||
#define PCI_SCR_B (0x00000004) /* Bus master enable */
|
||||
#define PCI_SCR_M (0x00000002) /* Memory access control */
|
||||
#define PCI_SCR_IO (0x00000001) /* I/O access control */
|
||||
|
||||
#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
|
||||
#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
|
||||
#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
|
||||
#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
|
||||
|
||||
#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
|
||||
#define PCI_BAR_BAR1(x) (x & 0xC0000000)
|
||||
#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
|
||||
#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
|
||||
#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
|
||||
|
||||
#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
|
||||
#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
|
||||
#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
|
||||
#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
|
||||
|
||||
#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
|
||||
#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
|
||||
#define PCI_GSCR_SE (0x10000000) /* SERR detected */
|
||||
#define PCI_GSCR_ER (0x08000000) /* Error response detected */
|
||||
#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
|
||||
#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
|
||||
#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
|
||||
#define PCI_GSCR_PR (0x00000001) /* PCI reset */
|
||||
|
||||
#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
|
||||
#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
|
||||
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
|
||||
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
|
||||
|
||||
#define PCI_TCR1_B5E (0x00002000) /* */
|
||||
#define PCI_TCR1_B4E (0x00001000) /* */
|
||||
#define PCI_TCR1_B3E (0x00000800) /* */
|
||||
#define PCI_TCR1_B2E (0x00000400) /* */
|
||||
#define PCI_TCR1_B1E (0x00000200) /* */
|
||||
#define PCI_TCR1_B0E (0x00000100) /* */
|
||||
#define PCI_TCR1_CR (0x00000001) /* */
|
||||
|
||||
#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
|
||||
#define PCI_TBATR_BAT1(x) (x & 0xC0000000)
|
||||
#define PCI_TBATR_EN (0x00000001) /* Enable */
|
||||
|
||||
#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
|
||||
#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
|
||||
#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
|
||||
#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
|
||||
#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
|
||||
#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
|
||||
#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
|
||||
#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
|
||||
#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
|
||||
#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
|
||||
#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
|
||||
#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
|
||||
#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
|
||||
#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
|
||||
#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
|
||||
|
||||
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
|
||||
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
|
||||
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
|
||||
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
|
||||
|
||||
#define PCIARB_ACR_DS (0x80000000)
|
||||
#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
|
||||
#define PCIARB_ARC_INTMINTEN (0x00010000)
|
||||
#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
|
||||
#define PCIARB_ARC_INTMPRI (0x00000001)
|
||||
|
||||
#endif /* mcf547x_8x_h */
|
||||
Loading…
Reference in New Issue
Block a user