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MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE
Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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14
README
14
README
@ -528,20 +528,6 @@ The following options need to be configured:
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pointer. This is needed for the temporary stack before
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relocation.
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CONFIG_SYS_MIPS_CACHE_MODE
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Cache operation mode for the MIPS CPU.
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See also arch/mips/include/asm/mipsregs.h.
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Possible values are:
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CONF_CM_CACHABLE_NO_WA
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CONF_CM_CACHABLE_WA
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CONF_CM_UNCACHED
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CONF_CM_CACHABLE_NONCOHERENT
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CONF_CM_CACHABLE_CE
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CONF_CM_CACHABLE_COW
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CONF_CM_CACHABLE_CUW
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CONF_CM_CACHABLE_ACCELERATED
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CONFIG_XWAY_SWAP_BYTES
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Enable compilation of tools/xway-swap-bytes needed for Lantiq
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@ -14,10 +14,6 @@
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#include <asm/cacheops.h>
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#include <asm/cm.h>
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#ifndef CONFIG_SYS_MIPS_CACHE_MODE
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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#endif
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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@ -331,7 +327,7 @@ l1_init:
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and t0, t0, t1
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PTR_LI t1, CKSEG1
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or t0, t0, t1
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li a0, CONFIG_SYS_MIPS_CACHE_MODE
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li a0, CONF_CM_CACHABLE_NONCOHERENT
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jalr.hb t0
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/*
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@ -19,9 +19,6 @@
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/* CPU Timer rate */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
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/* Cache Configuration */
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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/*----------------------------------------------------------------------
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* Memory Layout
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*/
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@ -16,9 +16,6 @@
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/* CPU Timer rate */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000
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/* Cache Configuration */
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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/*----------------------------------------------------------------------
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* Memory Layout
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*/
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@ -3424,7 +3424,6 @@ CONFIG_SYS_MEM_TOP_HIDE
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CONFIG_SYS_MFD
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CONFIG_SYS_MHZ
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CONFIG_SYS_MII_MODE
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CONFIG_SYS_MIPS_CACHE_MODE
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CONFIG_SYS_MIPS_TIMER_FREQ
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CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
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CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
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