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arm: mx5: Add fuse supply enable in fsl_iim
Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
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MXC_CCM_CCGR5_EMI_ENFC(cg));
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}
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#ifdef CONFIG_FSL_IIM
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void enable_efuse_prog_supply(bool enable)
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{
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if (enable)
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setbits_le32(&mxc_ccm->cgpr,
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MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
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else
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clrbits_le32(&mxc_ccm->cgpr,
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MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
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}
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#endif
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/* Config main_bus_clock for periphs */
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static int config_periph_clk(u32 ref, u32 freq)
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{
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@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
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void mxc_set_sata_internal_clock(void);
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
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void enable_nfc_clk(unsigned char enable);
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void enable_efuse_prog_supply(bool enable);
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#endif /* __ASM_ARCH_CLOCK_H */
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@ -305,6 +305,9 @@ struct mxc_ccm_reg {
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/* Define the bits in register CCDR */
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#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
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/* Define the bits in register CGPR */
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#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
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/* Define the bits in register CCGRx */
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#define MXC_CCM_CCGR_CG_MASK 0x3
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#define MXC_CCM_CCGR_CG_OFF 0x0
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@ -16,6 +16,9 @@
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#ifndef CONFIG_MPC512X
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#include <asm/arch/imx-regs.h>
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#endif
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#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
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#include <asm/arch/clock.h>
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#endif
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/* FSL IIM-specific constants */
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#define STAT_BUSY 0x80
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@ -93,6 +96,10 @@ struct fsl_iim {
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} bank[8];
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};
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#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
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#define enable_efuse_prog_supply(enable)
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#endif
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static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
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const char *caller)
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{
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@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
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if (ret)
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return ret;
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enable_efuse_prog_supply(1);
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for (bit = 0; val; bit++, val >>= 1)
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if (val & 0x01) {
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ret = prog_bit(regs, bank, word, bit);
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if (ret)
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if (ret) {
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enable_efuse_prog_supply(0);
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return ret;
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}
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}
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enable_efuse_prog_supply(0);
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return 0;
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}
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