arm: mx5: Add fuse supply enable in fsl_iim

Enable fuse supply before fuse programming and disable after.

Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Sergey Alyoshin 2013-12-17 23:24:54 +04:00 committed by Stefano Babic
parent c655b816e5
commit 4611d5bab2
4 changed files with 28 additions and 1 deletions

View File

@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
MXC_CCM_CCGR5_EMI_ENFC(cg));
}
#ifdef CONFIG_FSL_IIM
void enable_efuse_prog_supply(bool enable)
{
if (enable)
setbits_le32(&mxc_ccm->cgpr,
MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
else
clrbits_le32(&mxc_ccm->cgpr,
MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
}
#endif
/* Config main_bus_clock for periphs */
static int config_periph_clk(u32 ref, u32 freq)
{

View File

@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_nfc_clk(unsigned char enable);
void enable_efuse_prog_supply(bool enable);
#endif /* __ASM_ARCH_CLOCK_H */

View File

@ -305,6 +305,9 @@ struct mxc_ccm_reg {
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
/* Define the bits in register CGPR */
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#define MXC_CCM_CCGR_CG_OFF 0x0

View File

@ -16,6 +16,9 @@
#ifndef CONFIG_MPC512X
#include <asm/arch/imx-regs.h>
#endif
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/clock.h>
#endif
/* FSL IIM-specific constants */
#define STAT_BUSY 0x80
@ -93,6 +96,10 @@ struct fsl_iim {
} bank[8];
};
#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
#define enable_efuse_prog_supply(enable)
#endif
static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
const char *caller)
{
@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
if (ret)
return ret;
enable_efuse_prog_supply(1);
for (bit = 0; val; bit++, val >>= 1)
if (val & 0x01) {
ret = prog_bit(regs, bank, word, bit);
if (ret)
if (ret) {
enable_efuse_prog_supply(0);
return ret;
}
}
enable_efuse_prog_supply(0);
return 0;
}