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net: mscc: Move mac_table_add function into different file.
Move the function mac_table_add into a different file, so it can be reused. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This commit is contained in:
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36d04f52ff
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@ -1,2 +1,2 @@
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obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o
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obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o mscc_miim.o mscc_xfer.o mscc_mac_table.o
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74
drivers/net/mscc_eswitch/mscc_mac_table.c
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74
drivers/net/mscc_eswitch/mscc_mac_table.c
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@ -0,0 +1,74 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <linux/io.h>
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#include "mscc_mac_table.h"
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#define ANA_TABLES_MACACCESS_VALID BIT(11)
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#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
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#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
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#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
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#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
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#define MACACCESS_CMD_IDLE 0
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#define MACACCESS_CMD_LEARN 1
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/* MAC table entry types.
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* ENTRYTYPE_NORMAL is subject to aging.
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* ENTRYTYPE_LOCKED is not subject to aging.
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*/
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enum macaccess_entry_type {
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ENTRYTYPE_NORMAL = 0,
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ENTRYTYPE_LOCKED,
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};
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static int vlan_wait_for_completion(void __iomem *regs,
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const unsigned long *mscc_mac_table_offset)
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{
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unsigned int val, timeout = 10;
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/* Wait for the issued mac table command to be completed, or timeout.
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* When the command read from ANA_TABLES_MACACCESS is
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* MACACCESS_CMD_IDLE, the issued command completed successfully.
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*/
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do {
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val = readl(regs +
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mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
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val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
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} while (val != MACACCESS_CMD_IDLE && timeout--);
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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int mscc_mac_table_add(void __iomem *regs,
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const unsigned long *mscc_mac_table_offset,
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const unsigned char mac[ETH_LEN], int pgid)
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{
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u32 macl = 0, mach = 0;
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/* Set the MAC address to handle and the vlan associated in a format
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* understood by the hardware.
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*/
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mach |= MAC_VID << 16;
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mach |= ((u32)mac[0]) << 8;
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mach |= ((u32)mac[1]) << 0;
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macl |= ((u32)mac[2]) << 24;
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macl |= ((u32)mac[3]) << 16;
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macl |= ((u32)mac[4]) << 8;
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macl |= ((u32)mac[5]) << 0;
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writel(macl, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACLDATA]);
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writel(mach, regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACHDATA]);
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writel(ANA_TABLES_MACACCESS_VALID |
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ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
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ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
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ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
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regs + mscc_mac_table_offset[MSCC_ANA_TABLES_MACACCESS]);
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return vlan_wait_for_completion(regs, mscc_mac_table_offset);
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}
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19
drivers/net/mscc_eswitch/mscc_mac_table.h
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19
drivers/net/mscc_eswitch/mscc_mac_table.h
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#define ETH_LEN 6
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#define MAC_VID 1
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enum mscc_regs_ana_table {
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MSCC_ANA_TABLES_MACHDATA,
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MSCC_ANA_TABLES_MACLDATA,
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MSCC_ANA_TABLES_MACACCESS,
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};
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int mscc_mac_table_add(void __iomem *regs,
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const unsigned long *mscc_mac_table_offset,
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const unsigned char mac[ETH_LEN], int pgid);
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@ -17,6 +17,7 @@
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#include "mscc_miim.h"
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#include "mscc_miim.h"
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#include "mscc_xfer.h"
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#include "mscc_xfer.h"
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#include "mscc_mac_table.h"
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#define PHY_CFG 0x0
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#define PHY_CFG 0x0
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#define PHY_CFG_ENA 0xF
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#define PHY_CFG_ENA 0xF
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@ -30,17 +31,6 @@
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#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
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#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
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#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
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#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
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#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
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#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
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#define ANA_TABLES_MACHDATA 0x8b34
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#define ANA_TABLES_MACLDATA 0x8b38
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#define ANA_TABLES_MACACCESS 0x8b3c
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#define ANA_TABLES_MACACCESS_VALID BIT(11)
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#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
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#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
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#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
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#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
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#define MACACCESS_CMD_IDLE 0
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#define MACACCESS_CMD_LEARN 1
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#define MACACCESS_CMD_GET_NEXT 4
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#define ANA_PGID(x) (0x8c00 + 4 * (x))
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#define ANA_PGID(x) (0x8c00 + 4 * (x))
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#define SYS_FRM_AGING 0x574
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#define SYS_FRM_AGING 0x574
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@ -119,19 +109,6 @@ enum ocelot_target {
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#define MAX_PORT (PORT3 - PORT0)
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#define MAX_PORT (PORT3 - PORT0)
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/* MAC table entry types.
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* ENTRYTYPE_NORMAL is subject to aging.
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* ENTRYTYPE_LOCKED is not subject to aging.
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* ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
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* ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
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*/
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enum macaccess_entry_type {
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ENTRYTYPE_NORMAL = 0,
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ENTRYTYPE_LOCKED,
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ENTRYTYPE_MACv4,
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ENTRYTYPE_MACv6,
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};
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enum ocelot_mdio_target {
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enum ocelot_mdio_target {
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MIIM,
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MIIM,
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PHY,
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PHY,
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@ -169,6 +146,12 @@ static const unsigned long ocelot_regs_qs[] = {
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[MSCC_QS_INJ_CTRL] = 0x34,
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[MSCC_QS_INJ_CTRL] = 0x34,
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};
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};
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static const unsigned long ocelot_regs_ana_table[] = {
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[MSCC_ANA_TABLES_MACHDATA] = 0x8b34,
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[MSCC_ANA_TABLES_MACLDATA] = 0x8b38,
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[MSCC_ANA_TABLES_MACACCESS] = 0x8b3c,
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};
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struct mscc_miim_dev miim[NUM_PHY];
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struct mscc_miim_dev miim[NUM_PHY];
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static int mscc_miim_reset(struct mii_dev *bus)
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static int mscc_miim_reset(struct mii_dev *bus)
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@ -388,62 +371,13 @@ static int ocelot_initialize(struct ocelot_private *priv)
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return 0;
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return 0;
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}
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}
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static inline int ocelot_vlant_wait_for_completion(struct ocelot_private *priv)
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{
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unsigned int val, timeout = 10;
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/* Wait for the issued mac table command to be completed, or timeout.
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* When the command read from ANA_TABLES_MACACCESS is
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* MACACCESS_CMD_IDLE, the issued command completed successfully.
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*/
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do {
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val = readl(priv->regs[ANA] + ANA_TABLES_MACACCESS);
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val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
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} while (val != MACACCESS_CMD_IDLE && timeout--);
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static int ocelot_mac_table_add(struct ocelot_private *priv,
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const unsigned char mac[ETH_ALEN], int pgid)
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{
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u32 macl = 0, mach = 0;
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int ret;
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/* Set the MAC address to handle and the vlan associated in a format
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* understood by the hardware.
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*/
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mach |= MAC_VID << 16;
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mach |= ((u32)mac[0]) << 8;
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mach |= ((u32)mac[1]) << 0;
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macl |= ((u32)mac[2]) << 24;
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macl |= ((u32)mac[3]) << 16;
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macl |= ((u32)mac[4]) << 8;
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macl |= ((u32)mac[5]) << 0;
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writel(macl, priv->regs[ANA] + ANA_TABLES_MACLDATA);
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writel(mach, priv->regs[ANA] + ANA_TABLES_MACHDATA);
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writel(ANA_TABLES_MACACCESS_VALID |
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ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
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ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
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ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
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priv->regs[ANA] + ANA_TABLES_MACACCESS);
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ret = ocelot_vlant_wait_for_completion(priv);
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return ret;
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}
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static int ocelot_write_hwaddr(struct udevice *dev)
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static int ocelot_write_hwaddr(struct udevice *dev)
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{
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{
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struct ocelot_private *priv = dev_get_priv(dev);
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struct ocelot_private *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
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mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
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pdata->enetaddr, PGID_UNICAST);
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writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
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writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
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@ -463,13 +397,15 @@ static int ocelot_start(struct udevice *dev)
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return ret;
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return ret;
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/* Set MAC address tables entries for CPU redirection */
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/* Set MAC address tables entries for CPU redirection */
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ocelot_mac_table_add(priv, mac, PGID_BROADCAST);
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mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac,
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PGID_BROADCAST);
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writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
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writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
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priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
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priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
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/* It should be setup latter in ocelot_write_hwaddr */
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/* It should be setup latter in ocelot_write_hwaddr */
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ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
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mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table,
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pdata->enetaddr, PGID_UNICAST);
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writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
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writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
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