armv8: ls1088ardb: support force SDHC mode by hwconfig

The BRDCFG5[SPISDHC] register field of Qixis device is used
to control SPI and SDHC signal routing.

10 = Force SDHC Mode
  - SPI_CS[0] is routed to CPLD for SDHC_VS use.
  - SPI_CS[1] is unused.
  - SPI_CS[2:3] are routed to the TDMRiser slot.

11 = Force eMMC Mode
  - SPI_CS[0:3] are routed to the eMMC card.

0X = Auto Mode
  - If SDHC_CS_B=0 (SDHC card installed): Use SDHC mode
    described above.
  - Else SDHC_CS_B=1 (no SDHC card installed): Use eMMC
    mode described above.

In default the hardware uses auto mode, but sometimes we need
to use force SDHC mode to support SD card hotplug, or SD sleep
waking up in kernel. This patch is to support force SDHC mode
by hwconfig.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Yangbo Lu 2017-11-27 15:40:17 +08:00 committed by York Sun
parent cf71338ee7
commit 44cdb5b6a1
3 changed files with 26 additions and 0 deletions

View File

@ -18,6 +18,7 @@
#include <environment.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch/ppa.h>
#include <hwconfig.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
@ -296,6 +297,23 @@ void board_retimer_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
#ifdef CONFIG_TARGET_LS1088ARDB
u8 brdcfg5;
if (hwconfig("esdhc-force-sd")) {
brdcfg5 = QIXIS_READ(brdcfg[5]);
brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
brdcfg5 |= BRDCFG5_FORCE_SD;
QIXIS_WRITE(brdcfg[5], brdcfg5);
}
#endif
return 0;
}
#endif
int board_init(void)
{
init_final_memctl_regs();

View File

@ -36,4 +36,10 @@
#define BRDCFG9_SFPTX_MASK 0x10
#define BRDCFG9_SFPTX_SHIFT 4
/* Definitions of QIXIS Registers for LS1088ARDB */
/* BRDCFG5 */
#define BRDCFG5_SPISDHC_MASK 0x0C
#define BRDCFG5_FORCE_SD 0x08
#endif

View File

@ -11,6 +11,8 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_MISC_INIT_R
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */