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mpc52xx: add common o2dnt and o2dnt2 support and configurations

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Add common code for o2dnt and o2dnt2 based boards and add different
board configuration files for O2D, O2I, O2DNT2, O2D300, O2MNT and
O3DNT boards.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Anatolij Gustschin 2012-08-31 01:29:57 +00:00 committed by Wolfgang Denk
parent d7903ae159
commit 4387cf1ae1
11 changed files with 1287 additions and 0 deletions
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9
MAINTAINERS
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@ -237,6 +237,15 @@ Wolfgang Grandegger <wg@denx.de>
IPHASE4539 MPC8260
SCM MPC8260
Anatolij Gustschin <agust@denx.de>
O2D MPC5200
O2D300 MPC5200
O2DNT2 MPC5200
O2I MPC5200
O2MNT MPC5200
O3DNT MPC5200
Rob Herring <rob.herring@calxeda.com>
highbank highbank

34
board/ifm/o2dnt2/Makefile Normal file
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@ -0,0 +1,34 @@
#
# (C) Copyright 2005-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

400
board/ifm/o2dnt2/o2dnt2.c Normal file
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@ -0,0 +1,400 @@
/*
* Partially derived from board code for digsyMTC,
* (C) Copyright 2009
* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <miiphy.h>
#include <net.h>
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
enum ifm_sensor_type {
O2DNT = 0x00, /* !< O2DNT 32MB */
O2DNT2 = 0x01, /* !< O2DNT2 64MB */
O3DNT = 0x02, /* !< O3DNT 32MB */
O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */
UNKNOWN = 0xff, /* !< Unknow sensor */
};
static enum ifm_sensor_type gt_ifm_sensor_type;
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
long control = SDRAM_CONTROL | hi_addr_bit;
/* unlock mode register */
out_be32(&sdram->ctrl, control | 0x80000000);
/* precharge all banks */
out_be32(&sdram->ctrl, control | 0x80000002);
/* auto refresh */
out_be32(&sdram->ctrl, control | 0x80000004);
/* set mode register */
out_be32(&sdram->mode, SDRAM_MODE);
/* normal operation */
out_be32(&sdram->ctrl, control);
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
*/
phys_size_t initdram(int board_type)
{
struct mpc5xxx_mmap_ctl *mmap_ctl =
(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
ulong dramsize = 0;
ulong dramsize2 = 0;
uint svr, pvr;
if (gt_ifm_sensor_type == O2DNT2) {
/* activate SDRAM CS1 */
setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
}
#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
/* setup config registers */
out_be32(&sdram->config1, SDRAM_CONFIG1);
out_be32(&sdram->config2, SDRAM_CONFIG2);
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
sdram_start(1);
test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20))
dramsize = 0;
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
out_be32(&mmap_ctl->sdram0,
(0x13 + __builtin_ffs(dramsize >> 20) - 1));
} else {
out_be32(&mmap_ctl->sdram0, 0); /* disabled */
}
/* let SDRAM CS1 start right after CS0 */
out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start(0);
test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
0x80000000);
if (!dramsize) {
sdram_start(1);
test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
0x80000000);
}
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;
} else {
dramsize2 = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize2 < (1 << 20))
dramsize2 = 0;
/* set SDRAM CS1 size according to the amount of RAM found */
if (dramsize2 > 0) {
out_be32(&mmap_ctl->sdram1, (dramsize |
(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
} else {
out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
}
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
if (dramsize >= 0x13)
dramsize = (1 << (dramsize - 0x13)) << 20;
else
dramsize = 0;
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
if (dramsize2 >= 0x13)
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
else
dramsize2 = 0;
#endif /* CONFIG_SYS_RAMBOOT */
/*
* On MPC5200B we need to set the special configuration delay in the
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
*
* "The SDelay should be written to a value of 0x00000004. It is
* required to account for changes caused by normal wafer processing
* parameters."
*/
svr = get_svr();
pvr = get_pvr();
if ((SVR_MJREV(svr) >= 2) &&
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
out_be32(&sdram->sdelay, 0x04);
return dramsize + dramsize2;
}
#define GPT_GPIO_IN 0x4
int checkboard(void)
{
struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
unsigned char board_config = 0;
int i;
/* switch gpt0 - gpt7 to input */
for (i = 0; i < 7; i++)
out_be32(&gpt[i].emsr, GPT_GPIO_IN);
/* get configuration byte on timer-port */
for (i = 0; i < 7; i++)
board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
puts("Board: ");
switch (board_config) {
case 0:
puts("O2DNT\n");
gt_ifm_sensor_type = O2DNT;
break;
case 1:
puts("O3DNT\n");
gt_ifm_sensor_type = O3DNT;
break;
case 2:
puts("O2DNT2\n");
gt_ifm_sensor_type = O2DNT2;
break;
case 64:
puts("O3DNT Minerva\n");
gt_ifm_sensor_type = O3DNT_MIN;
break;
default:
puts("Unknown\n");
gt_ifm_sensor_type = UNKNOWN;
break;
}
return 0;
}
int board_early_init_r(void)
{
struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
/*
* Now, when we are in RAM, enable flash write access for detection
* process. Note that CS_BOOT cannot be cleared when executing in flash.
*/
clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
/* disable CS_BOOT */
clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
/* enable CS0 */
setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
return 0;
}
#define MIIM_LXT971_LED_CFG_REG 0x14
#define LXT971_LED_CFG_LINK_STATUS 0x4000
#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700
#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0
#define LXT971_LED_CFG_PULSE_STRETCH 0x0002
/*
* Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
*/
void reset_phy(void)
{
/*
* Set LED configuration bits.
* It can't be done in misc_init_r() since FEC is not
* initialized at this time. Therefore we do it here.
*/
miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
LXT971_LED_CFG_LINK_STATUS |
LXT971_LED_CFG_RX_TX_ACTIVITY |
LXT971_LED_CFG_LINK_ACTIVITY |
LXT971_LED_CFG_PULSE_STRETCH);
}
#if defined(CONFIG_POST)
/*
* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
* is left open, no keypress is detected.
*/
int post_hotkeys_pressed(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
/*
* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
* CODEC or UART mode. Consumer IrDA should still be possible.
*/
clrbits_be32(&gpio->port_config, 0x07000000);
setbits_be32(&gpio->port_config, 0x03000000);
/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
setbits_be32(&gpio->simple_gpioe, 0x20000000);
/* Configure GPIO_IRDA_1 as input */
clrbits_be32(&gpio->simple_ddr, 0x20000000);
return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
}
#endif
#ifdef CONFIG_PCI
static struct pci_controller hose;
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
static void ft_adapt_flash_base(void *blob)
{
flash_info_t *dev = &flash_info[0];
int off;
struct fdt_property *prop;
int len;
u32 *reg, *reg2;
off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
if (off < 0) {
printf("Could not find fsl,mpc5200b-lpb node.\n");
return;
}
/* found compatible property */
prop = fdt_get_property_w(blob, off, "ranges", &len);
if (prop) {
reg = reg2 = (u32 *)&prop->data[0];
reg[2] = dev->start[0];
reg[3] = dev->size;
fdt_setprop(blob, off, "ranges", reg2, len);
} else
printf("Could not find ranges\n");
}
extern ulong flash_get_size(phys_addr_t base, int banknum);
/* Update the flash baseaddr settings */
int update_flash_size(int flash_size)
{
struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
flash_info_t *dev;
int i;
int size = 0;
unsigned long base = 0x0;
u32 *cs_reg = (u32 *)&mm->cs0_start;
for (i = 0; i < 2; i++) {
dev = &flash_info[i];
if (dev->size) {
/* calculate new base addr for this chipselect */
base -= dev->size;
out_be32(cs_reg, START_REG(base));
cs_reg++;
out_be32(cs_reg, STOP_REG(base, dev->size));
cs_reg++;
/* recalculate the sectoraddr in the cfi driver */
size += flash_get_size(base, i);
}
}
flash_protect_default();
gd->bd->bi_flashstart = base;
return 0;
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
void ft_board_setup(void *blob, bd_t *bd)
{
int phy_addr = CONFIG_PHY_ADDR;
char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
ft_cpu_setup(blob, bd);
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
/* Update reg property in all nor flash nodes too */
fdt_fixup_nor_flash_size(blob);
#endif
ft_adapt_flash_base(blob);
#endif
/* fix up the phy address */
do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

10
boards.cfg
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@ -482,6 +482,16 @@ TOP5200 powerpc mpc5xxx top5200 emk
cpci5200 powerpc mpc5xxx - esd
mecp5200 powerpc mpc5xxx - esd
pf5200 powerpc mpc5xxx - esd
O2D powerpc mpc5xxx o2dnt2 ifm - o2d
O2D300 powerpc mpc5xxx o2dnt2 ifm - o2d300
O2DNT2 powerpc mpc5xxx o2dnt2 ifm - o2dnt2
O2DNT2_RAMBOOT powerpc mpc5xxx o2dnt2 ifm - o2dnt2:SYS_TEXT_BASE=0x00100000
O2I powerpc mpc5xxx o2dnt2 ifm - o2i
O2MNT powerpc mpc5xxx o2dnt2 ifm - o2mnt
O2MNT_O2M110 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M110"
O2MNT_O2M112 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M112"
O2MNT_O2M113 powerpc mpc5xxx o2dnt2 ifm - o2mnt:IFM_SENSOR_TYPE="O2M113"
O3DNT powerpc mpc5xxx o2dnt2 ifm - o3dnt
digsy_mtc powerpc mpc5xxx digsy_mtc intercontrol
digsy_mtc_RAMBOOT powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:SYS_TEXT_BASE=0x00100000
digsy_mtc_rev5 powerpc mpc5xxx digsy_mtc intercontrol - digsy_mtc:DIGSY_REV5

80
include/configs/o2d.h Normal file
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@ -0,0 +1,80 @@
/*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFC000000 boot low boot high (standard configuration)
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */
#endif
/* Board specific flash config */
#define CONFIG_SYS_FLASH_BASE 0xfc000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
/*
* Include common defines for all ifm boards
*/
#include "o2dnt-common.h"
/* additional commands */
#define CONFIG_CMD_ITEST
/*
* GPIO configuration:
* CS1 SDRAM activate + no CAN + no PCI
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004
/* Other board specific configs */
#define CONFIG_SYS_BOOTCS_CFG 0x00057d01
#define CONFIG_SYS_RESET_ADDRESS 0xfc000000
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */
#define CONFIG_BOARD_NAME "o2d"
#define CONFIG_BOARD_BOOTCMD "run dhcp_boot"
#define CONFIG_BOARD_MEM_LIMIT xstr(126)
#define BOARD_POST_CRC32_END xstr(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_OLD \
CONFIG_IFM_DEFAULT_ENV_NEW \
"linbot=fc060000\0" \
"lintop=fc15ffff\0" \
"rambot=fc160000\0" \
"ramtop=fc55ffff\0" \
"jffbot=fc560000\0" \
"jfftop=fcffffff\0" \
"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"kernel_addr=0xfc060000\0" \
"ramdisk_addr=0xfc160000\0" \
"progCram=tftp ${fileaddr} ${cramfsname};" \
"erase ${rambot} ${ramtop};" \
"cp.b ${fileaddr} ${rambot} ${filesize}\0" \
"flash_for_configs=22396\0" \
"flash_mtd=run mtd_args addip addmem;" \
"bootm ${kernel_addr}\0" \
"mtd_args=setenv bootargs root=/dev/mtdblock3 " \
"rw rootfstype=cramfs\0" \
"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \
"mw f0000b04 ${IOpin};mw f0000b10 0x20\0" \
"dhcp_boot=run dhcpcmd;run flash_mtd\0" \
"hostname=IFM_SENSOR\0" \
"netretry=once\0" \
"autoload=no\0" \
"sensorType=O2D222AG\0"

84
include/configs/o2d300.h Normal file
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@ -0,0 +1,84 @@
/*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFC000000 boot low boot high (standard configuration)
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */
#endif
/* Board specific flash config */
#define CONFIG_SYS_FLASH_BASE 0xfc000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
/*
* Include common defines for all ifm boards
*/
#include "o2dnt-common.h"
/*
* GPIO configuration:
* CS1 SDRAM activate + no CAN + no PCI
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004
/* Other board specific configs */
#define CONFIG_SYS_BOOTCS_CFG 0x00057d01
#define CONFIG_SYS_RESET_ADDRESS 0xfc000000
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */
/* Use redundant environment */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#define CONFIG_BOARD_NAME "o2d300"
#define CONFIG_BOARD_BOOTCMD "run dhcp_boot"
#define CONFIG_BOARD_MEM_LIMIT xstr(126)
#define BOARD_POST_CRC32_END xstr(0x02000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_OLD \
CONFIG_IFM_DEFAULT_ENV_NEW \
"autoload=no\0" \
"dhcp_boot=run dhcpcmd;run flash_mtd\0" \
"flash_mtd=run mtd_args addip addmem;" \
"bootm ${kernel_addr}\0" \
"mtd_args=setenv bootargs root=/dev/mtdblock4 " \
"rw rootfstype=cramfs\0" \
"linbot=fc080000\0" \
"lintop=fc17ffff\0" \
"rambot=fc180000\0" \
"ramtop=fc57ffff\0" \
"jffbot=fc580000\0" \
"jfftop=fd39ffff\0" \
"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0" \
"halbot=fd3a0000\0" \
"haltop=fdf9ffff\0" \
"progHal=tftp 200000 ${halname};erase ${halbot} ${haltop};" \
"cp.b ${fileaddr} ${halbot} ${filesize}\0" \
"kernel_addr=0xfc060000\0" \
"ramdisk_addr=0xfc160000\0" \
"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \
"mw f0000b04 ${IOpin};mw f0000b10 0x20\0" \
"netretry=once\0" \
"protcmd=protect on ${linbot} ${lintop};" \
"protect on ${rambot} ${ramtop}\0" \
"o2derror=def_env\0" \
"sensorType=O2D300AA\0"

379
include/configs/o2dnt-common.h Normal file
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@ -0,0 +1,379 @@
/*
* Common configuration options for ifm camera boards
*
* (C) Copyright 2005
* Sebastien Cazaux, ifm electronic gmbh
*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __O2D_CONFIG_H
#define __O2D_CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
/* log base 2 of the above value */
#define CONFIG_SYS_CACHELINE_SHIFT 5
#endif
/*
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
CONFIG_SYS_POST_I2C)
*/
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#undef CONFIG_PCI
#define CONFIG_PCI_PNP 1
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_SYS_XLB_PIPELINING 1
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */
/*
* Supported commands
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
/* Boot low with 16 or 32 MB Flash */
#define CONFIG_SYS_LOWBOOT 1
#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
#error "CONFIG_SYS_TEXT_BASE value is invalid"
#endif
/*
* Autobooting
* Be selective on what keys can delay or stop the autoboot process
* To stop use: "++++++++++"
*/
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
"press password to stop\n", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR "++++++++++"
#undef CONFIG_AUTOBOOT_DELAY_STR
#define DEBUG_BOOTKEYS 0
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "run master"
#undef CONFIG_BOOTARGS
#define xstr(s) str(s)
#define str(s) #s
#if !defined(CONFIG_CONSOLE_DEV)
#define CONFIG_CONSOLE_DEV "ttyPSC1"
#endif
/*
* Default environment for booting old and new kernel versions
*/
#define CONFIG_IFM_DEFAULT_ENV_OLD \
"flash_self_old=run ramargs addip addmem;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs_old=run nfsargs addip addmem;" \
"bootm ${kernel_addr}\0" \
"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addmem;" \
"bootm ${kernel_addr_r}\0"
#define CONFIG_IFM_DEFAULT_ENV_NEW \
"fdt_addr_r=900000\0" \
"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \
"flash_self=run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \
"IOpin=0x64\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
"addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
"addtty=sete bootargs ${bootargs} console=" \
CONFIG_CONSOLE_DEV ",${baudrate}\0" \
"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
"kernel_addr_r=600000\0" \
"initrd_high=0x03e00000\0" \
"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
"memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
"cp.b ${fileaddr} ${linbot} ${filesize}\0" \
"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \
"cp.b ${fileaddr} ${rambot} ${filesize}\0" \
"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \
"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \
"cp.b ${fileaddr} ${jffbot} ${filesize}\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"uboname=" CONFIG_BOARD_NAME \
"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \
"progubo=tftp 200000 ${uboname};" \
"protect off ${ubobot} ${ubotop};" \
"erase ${ubobot} ${ubotop};" \
"cp.b ${fileaddr} ${ubobot} ${filesize}\0" \
"unlock=yes\0" \
"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
"setenv bootdelay 1;" \
"crc32 "xstr(CONFIG_SYS_TEXT_BASE)" " \
BOARD_POST_CRC32_END";" \
"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
#define CONFIG_BOOTCOMMAND "run post"
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration:
*
* O2DNT board is equiped with Ramtron FRAM device FM24CL16
* 16 Kib Ferroelectric Nonvolatile serial RAM memory
* organized as 2048 x 8 bits and addressable as eight I2C devices
* 0x50 ... 0x57 each 256 bytes in size
*
*/
#define CONFIG_SYS_I2C_FRAM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
/*
* There is no write delay with FRAM, write operations are performed at bus
* speed. Thus, no status polling or write delay is needed.
*/
/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */
/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
/* "Real" (hardware) sectors protection */
#define CONFIG_SYS_FLASH_PROTECTION
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
#else
/* End of used area in DPRAM */
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT 1
#endif
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_RESET_PHY_R
/*
* GPIO configuration
*/
#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */
#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */
#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */
#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x100000
/* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_HZ 1000
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
/*
* DT support
*/
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#endif /* __O2D_CONFIG_H */

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/*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFC000000 boot low boot high (standard configuration)
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */
#endif
/* Board specific flash config */
#define CONFIG_SYS_FLASH_BASE 0xfc000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
/*
* Include common defines for all ifm boards
*/
#include "o2dnt-common.h"
/* additional commands */
#define CONFIG_CMD_ITEST
/*
* GPIO configuration:
* CS1 SDRAM activate + no CAN + no PCI
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004
/* Other board specific configs */
#define CONFIG_SYS_BOOTCS_CFG 0x00057d01
#define CONFIG_SYS_RESET_ADDRESS 0xfc000000
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */
#define CONFIG_BOARD_NAME "o2dnt2"
#define CONFIG_BOARD_BOOTCMD "run flash_self"
#define CONFIG_BOARD_MEM_LIMIT xstr(126)
#define BOARD_POST_CRC32_END xstr(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_OLD \
CONFIG_IFM_DEFAULT_ENV_NEW \
"linbot=fc060000\0" \
"lintop=fc15ffff\0" \
"rambot=fc160000\0" \
"ramtop=fc55ffff\0" \
"jffbot=fc560000\0" \
"jfftop=fce5ffff\0" \
"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \
"calbot=fce60000\0" \
"caltop=fcffffff\0" \
"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};" \
"cp.b ${fileaddr} ${calbot} ${filesize}\0" \
"kernel_addr=0xfc060000\0" \
"ramdisk_addr=0xfc160000\0" \
"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \
"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"

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/*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFF000000 boot low boot high (standard configuration)
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xff000000 /* Standard: boot low */
#endif
/* Board specific flash config */
#define CONFIG_SYS_FLASH_BASE 0xff000000
#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* maximum 16MB */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 128
/*
* Include common defines for all ifm boards
*/
#include "o2dnt-common.h"
/* GPIO configuration */
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002006 /* no CAN */
/* Other board specific configs */
#define CONFIG_SYS_BOOTCS_CFG 0x00087801
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */
#define CONFIG_BOARD_NAME "o2i"
#define CONFIG_BOARD_BOOTCMD "run dhcp_boot"
#define CONFIG_BOARD_MEM_LIMIT xstr(62)
#define BOARD_POST_CRC32_END xstr(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_OLD \
CONFIG_IFM_DEFAULT_ENV_NEW \
"linbot=ff060000\0" \
"lintop=ff15ffff\0" \
"rambot=ff160000\0" \
"ramtop=ff55ffff\0" \
"jffbot=ff560000\0" \
"jfftop=ffebffff\0" \
"kernel_addr=0xff060000\0" \
"ramdisk_addr=0xff160000\0" \
"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=ff03ffff\0" \
"autoload=no\0" \
"dhcp_boot=run dhcpcmd; run flash_mtd\0" \
"hostname=IFM_SENSOR\0" \
"flash_mtd=run mtd_args addip addmem;bootm ${kernel_addr}\0" \
"mtd_args=setenv bootargs root=/dev/mtdblock3 " \
"rw rootfstype=cramfs\0" \
"sensorType=O2I100AA\0" \
"netretry=once\0" \
"master=mw f0000b00 0x00052006;mw f0000b0c ${IOpin};" \
"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"

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/*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFF000000 boot low boot high (standard configuration)
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xff000000 /* Standard: boot low */
#endif
/* Board specific flash config */
#define CONFIG_SYS_FLASH_BASE 0xff000000
#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* maximum 16MB */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 128
/*
* Include common defines for all ifm boards
*/
#include "o2dnt-common.h"
/* GPIO configuration */
#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002004 /* no CAN */
/* Other board specific configs */
#define CONFIG_NETCONSOLE
#define CONFIG_SYS_BOOTCS_CFG 0x00087801
#define CONFIG_SYS_RESET_ADDRESS 0xff000000
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */
#define CONFIG_BOARD_NAME "o2mnt"
#define CONFIG_BOARD_BOOTCMD "${newcmd}"
#define CONFIG_BOARD_MEM_LIMIT xstr(62)
#define BOARD_POST_CRC32_END xstr(0x01000000)
#ifndef CONFIG_IFM_SENSOR_TYPE
#define CONFIG_IFM_SENSOR_TYPE "O2M110"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_OLD \
CONFIG_IFM_DEFAULT_ENV_NEW \
"linbot=ff060000\0" \
"lintop=ff25ffff\0" \
"rambot=ff260000\0" \
"ramtop=ffc5ffff\0" \
"jffbot=ffc60000\0" \
"jfftop=ffffffff\0" \
"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=ff03ffff\0" \
"kernel_addr=0xff060000\0" \
"ramdisk_addr=0xff260000\0" \
"newcmd=run scrprot;run flash_ext2\0" \
"scrprot=protect on ${linbot} ${lintop};protect on ${rambot} " \
"${ramtop}\0" \
"flash_ext2=run ext2args addip addmem;bootm ${kernel_addr}\0" \
"ext2args=setenv bootargs root=/dev/mtdblock3 ro " \
"rootfstype=ext2\0" \
"pwm=mw f0000674 0x10006;mw f0000678 0x30000;" \
"mw f0000678 0x30001;mw f0000670 0x3\0" \
"master=mw f0000b00 0x00052006;mw f0000b0c $(IOpin);" \
"mw f0000b04 $(IOpin);mw f0000b10 0x24;run pwm\0" \
"sensortyp="CONFIG_IFM_SENSOR_TYPE"\0" \
"srelease=0.00\0"

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/*
* (C) Copyright 2012
* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
* 0xFC000000 boot low boot high (standard configuration)
* 0x00100000 boot from RAM (for testing only)
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */
#endif
/* Board specific flash config */
#define CONFIG_SYS_FLASH_BASE 0xfc000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 512
/*
* Include common defines for all ifm boards
*/
#include "o2dnt-common.h"
/* Additional commands */
#define CONFIG_CMD_BSP
#define CONFIG_CMD_REGINFO
/*
* GPIO configuration:
* no CAN + no PCI
*/
#define CONFIG_SYS_GPS_PORT_CONFIG 0x0000A000
/* Other board specific configs */
#define CONFIG_SYS_BOOTCS_CFG 0x00057d01
#define CONFIG_SYS_RESET_ADDRESS 0xfc000000
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */
#define CONFIG_BOARD_NAME "o3dnt"
#define CONFIG_BOARD_BOOTCMD "run flash_self"
#define CONFIG_BOARD_MEM_LIMIT xstr(62)
#define BOARD_POST_CRC32_END xstr(0x01000000)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_SETTINGS \
CONFIG_IFM_DEFAULT_ENV_OLD \
CONFIG_IFM_DEFAULT_ENV_NEW \
"linbot=fc060000\0" \
"lintop=fc15ffff\0" \
"rambot=fc160000\0" \
"ramtop=fc55ffff\0" \
"jffbot=fc560000\0" \
"jfftop=fce5ffff\0" \
"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0" \
"ubotop=fc03ffff\0" \
"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \
"calbot=fce60000\0" \
"caltop=fcffffff\0" \
"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};" \
"cp.b ${fileaddr} ${calbot} ${filesize}\0" \
"kernel_addr=0xfc060000\0" \
"ramdisk_addr=0xfc160000\0" \
"master=mw f0000b00 0x0005A006;mw f0000b0c ${IOpin};" \
"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"