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https://github.com/u-boot/u-boot.git
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x86: ivybridge: Convert lpc init code to DM PCI API
Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
cdc337ed8f
commit
4265abd413
@ -24,13 +24,13 @@
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#define ENABLE_ACPI_MODE_IN_COREBOOT 0
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#define TEST_SMM_FLASH_LOCKDOWN 0
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static int pch_enable_apic(pci_dev_t dev)
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static int pch_enable_apic(struct udevice *pch)
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{
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u32 reg32;
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int i;
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/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
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x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
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dm_pci_write_config8(pch, ACPI_CNTL, 0x80);
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writel(0, IO_APIC_INDEX);
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writel(1 << 25, IO_APIC_DATA);
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@ -66,36 +66,36 @@ static int pch_enable_apic(pci_dev_t dev)
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return 0;
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}
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static void pch_enable_serial_irqs(pci_dev_t dev)
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static void pch_enable_serial_irqs(struct udevice *pch)
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{
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u32 value;
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/* Set packet length and toggle silent mode bit for one frame. */
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value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
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#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
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x86_pci_write_config8(dev, SERIRQ_CNTL, value);
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dm_pci_write_config8(pch, SERIRQ_CNTL, value);
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#else
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x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
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dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6));
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#endif
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}
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static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
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static int pch_pirq_init(struct udevice *pch)
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{
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uint8_t route[8], *ptr;
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if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
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sizeof(route)))
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if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
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"intel,pirq-routing", route, sizeof(route)))
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return -EINVAL;
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ptr = route;
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x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
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x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++);
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dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++);
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/*
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* TODO(sjg@chromium.org): U-Boot does not set up the interrupts
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@ -104,26 +104,28 @@ static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
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return 0;
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}
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static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
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static int pch_gpi_routing(struct udevice *pch)
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{
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u8 route[16];
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u32 reg;
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int gpi;
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if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
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sizeof(route)))
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if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
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"intel,gpi-routing", route, sizeof(route)))
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return -EINVAL;
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for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
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reg |= route[gpi] << (gpi * 2);
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x86_pci_write_config32(dev, 0xb8, reg);
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dm_pci_write_config32(pch, 0xb8, reg);
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return 0;
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}
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static int pch_power_options(const void *blob, int node, pci_dev_t dev)
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static int pch_power_options(struct udevice *pch)
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{
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const void *blob = gd->fdt_blob;
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int node = pch->of_offset;
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u8 reg8;
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u16 reg16, pmbase;
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u32 reg32;
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@ -142,7 +144,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
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*/
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pwr_on = MAINBOARD_POWER_ON;
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reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
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dm_pci_read_config16(pch, GEN_PMCON_3, ®16);
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reg16 &= 0xfffe;
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switch (pwr_on) {
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case MAINBOARD_POWER_OFF:
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@ -169,7 +171,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
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reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
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x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
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dm_pci_write_config16(pch, GEN_PMCON_3, reg16);
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debug("Set power %s after power failure.\n", state);
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/* Set up NMI on errors. */
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@ -193,21 +195,22 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
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outb(reg8, 0x70);
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/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
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reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
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dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
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reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
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reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
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reg16 |= (3 << 0); /* Periodic SMI every 8s */
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#endif
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x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
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dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
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/* Set the board's GPI routing. */
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ret = pch_gpi_routing(blob, node, dev);
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ret = pch_gpi_routing(pch);
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if (ret)
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return ret;
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pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
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dm_pci_read_config16(pch, 0x40, &pmbase);
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pmbase &= 0xfffe;
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writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
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"intel,gpe0-enable", 0));
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@ -227,16 +230,16 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
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return 0;
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}
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static void pch_rtc_init(pci_dev_t dev)
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static void pch_rtc_init(struct udevice *pch)
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{
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int rtc_failed;
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u8 reg8;
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reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
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dm_pci_read_config8(pch, GEN_PMCON_3, ®8);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~RTC_BATTERY_DEAD;
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x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
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dm_pci_write_config8(pch, GEN_PMCON_3, reg8);
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}
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debug("rtc_failed = 0x%x\n", rtc_failed);
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@ -246,10 +249,10 @@ static void pch_rtc_init(pci_dev_t dev)
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}
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/* CougarPoint PCH Power Management init */
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static void cpt_pm_init(pci_dev_t dev)
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static void cpt_pm_init(struct udevice *pch)
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{
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debug("CougarPoint PM init\n");
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x86_pci_write_config8(dev, 0xa9, 0x47);
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dm_pci_write_config8(pch, 0xa9, 0x47);
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setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
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setbits_le32(RCB_REG(0x228c), 1 << 0);
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@ -290,10 +293,10 @@ static void cpt_pm_init(pci_dev_t dev)
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}
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/* PantherPoint PCH Power Management init */
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static void ppt_pm_init(pci_dev_t dev)
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static void ppt_pm_init(struct udevice *pch)
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{
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debug("PantherPoint PM init\n");
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x86_pci_write_config8(dev, 0xa9, 0x47);
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dm_pci_write_config8(pch, 0xa9, 0x47);
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setbits_le32(RCB_REG(0x2238), 1 << 0);
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setbits_le32(RCB_REG(0x228c), 1 << 0);
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setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
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@ -340,16 +343,16 @@ static void enable_hpet(void)
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clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
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}
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static void enable_clock_gating(pci_dev_t dev)
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static void enable_clock_gating(struct udevice *pch)
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{
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u32 reg32;
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u16 reg16;
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setbits_le32(RCB_REG(0x2234), 0xf);
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reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
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dm_pci_read_config16(pch, GEN_PMCON_1, ®16);
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reg16 |= (1 << 2) | (1 << 11);
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x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
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dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
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pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
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pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
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@ -429,24 +432,24 @@ static void pch_lock_smm(pci_dev_t dev)
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}
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#endif
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static void pch_disable_smm_only_flashing(pci_dev_t dev)
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static void pch_disable_smm_only_flashing(struct udevice *pch)
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{
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u8 reg8;
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debug("Enabling BIOS updates outside of SMM... ");
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reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */
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reg8 &= ~(1 << 5);
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x86_pci_write_config8(dev, 0xdc, reg8);
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dm_pci_write_config8(pch, 0xdc, reg8);
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}
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static void pch_fixups(pci_dev_t dev)
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static void pch_fixups(struct udevice *pch)
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{
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u8 gen_pmcon_2;
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/* Indicate DRAM init done for MRC S3 to know it can resume */
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gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
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dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2);
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gen_pmcon_2 |= (1 << 7);
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x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
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dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2);
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/* Enable DMI ASPM in the PCH */
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clrbits_le32(RCB_REG(0x2304), 1 << 10);
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@ -538,66 +541,66 @@ static int lpc_early_init(struct udevice *dev)
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return 0;
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}
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static int lpc_init_extra(struct pci_controller *hose, pci_dev_t dev)
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static int lpc_init_extra(struct udevice *dev)
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{
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struct udevice *pch = dev->parent;
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const void *blob = gd->fdt_blob;
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int node;
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debug("pch: lpc_init\n");
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pci_write_bar32(hose, dev, 0, 0);
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pci_write_bar32(hose, dev, 1, 0xff800000);
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pci_write_bar32(hose, dev, 2, 0xfec00000);
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pci_write_bar32(hose, dev, 3, 0x800);
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pci_write_bar32(hose, dev, 4, 0x900);
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dm_pci_write_bar32(pch, 0, 0);
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dm_pci_write_bar32(pch, 1, 0xff800000);
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dm_pci_write_bar32(pch, 2, 0xfec00000);
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dm_pci_write_bar32(pch, 3, 0x800);
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dm_pci_write_bar32(pch, 4, 0x900);
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node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
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if (node < 0)
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return -ENOENT;
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/* Set the value for PCI command register. */
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x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
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dm_pci_write_config16(pch, PCI_COMMAND, 0x000f);
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/* IO APIC initialization. */
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pch_enable_apic(dev);
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pch_enable_apic(pch);
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pch_enable_serial_irqs(dev);
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pch_enable_serial_irqs(pch);
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/* Setup the PIRQ. */
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pch_pirq_init(blob, node, dev);
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pch_pirq_init(pch);
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/* Setup power options. */
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pch_power_options(blob, node, dev);
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pch_power_options(pch);
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/* Initialize power management */
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switch (pch_silicon_type()) {
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case PCH_TYPE_CPT: /* CougarPoint */
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cpt_pm_init(dev);
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cpt_pm_init(pch);
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break;
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case PCH_TYPE_PPT: /* PantherPoint */
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ppt_pm_init(dev);
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ppt_pm_init(pch);
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break;
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default:
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printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
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PCI_FUNC(dev));
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printf("Unknown Chipset: %s\n", pch->name);
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return -ENOSYS;
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}
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/* Initialize the real time clock. */
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pch_rtc_init(dev);
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pch_rtc_init(pch);
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/* Initialize the High Precision Event Timers, if present. */
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enable_hpet();
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/* Initialize Clock Gating */
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enable_clock_gating(dev);
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enable_clock_gating(pch);
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pch_disable_smm_only_flashing(dev);
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pch_disable_smm_only_flashing(pch);
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#if CONFIG_HAVE_SMI_HANDLER
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pch_lock_smm(dev);
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#endif
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pch_fixups(dev);
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pch_fixups(pch);
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return 0;
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}
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@ -636,7 +639,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev)
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return bd82x6x_lpc_early_init(dev);
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}
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return lpc_init_extra(pci_bus_to_hose(0), PCH_LPC_DEV);
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return lpc_init_extra(dev);
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}
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static const struct udevice_id bd82x6x_lpc_ids[] = {
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