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Add TI816X evm board support
Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Change to SPDX, fix a few compiler warnings, adapt to CONFIG_OMAP_COMMON] Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
TENART Antoine
Tom Rini
parent
dcf846d5da
commit
425faf74cd
@ -945,6 +945,10 @@ Lucas Stach <dev@lynxeye.de>
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colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core)
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Antoine Tenart <atenart@adeneo-embedded.com>
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TI816X ARM ARMV7 (TI816x Soc)
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Nick Thompson <nick.thompson@gefanuc.com>
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da830evm ARM926EJS (DA830/OMAP-L137)
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37
board/ti/ti816x/Makefile
Normal file
37
board/ti/ti816x/Makefile
Normal file
@ -0,0 +1,37 @@
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#
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# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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# Antoine Tenart, <atenart@adeneo-embedded.com>
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#
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# Based on TI-PSP-04.00.02.14 :
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#
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# Copyright (C) 2009, Texas Instruments, Incorporated
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := evm.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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229
board/ti/ti816x/evm.c
Normal file
229
board/ti/ti816x/evm.c
Normal file
@ -0,0 +1,229 @@
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/*
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* evm.c
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*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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static struct module_pin_mux mmc_pin_mux[] = {
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{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
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{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
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{ -1 },
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};
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const struct dmm_lisa_map_regs evm_lisa_map_regs = {
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.dmm_lisa_map_0 = 0x00000000,
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.dmm_lisa_map_1 = 0x00000000,
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.dmm_lisa_map_2 = 0x80640300,
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.dmm_lisa_map_3 = 0xC0640320,
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};
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/*
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* DDR2 related definitions
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*/
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#ifdef CONFIG_TI816X_EVM_DDR2
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static struct ddr_data ddr2_data = {
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.datardsratio0 = ((0x40<<10) | (0x40<<0)),
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.datawdsratio0 = ((0x4A<<10) | (0x4A<<0)),
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.datawiratio0 = ((0x0<<10) | (0x0<<0)),
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.datagiratio0 = ((0x0<<10) | (0x0<<0)),
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.datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
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.datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
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.datauserank0delay = 0x1,
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.datadldiff0 = 0x0, /* depend on cpu rev, set later */
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};
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static struct cmd_control ddr2_ctrl = {
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.cmd0csratio = 0x80,
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.cmd0dldiff = 0x04, /* reset value is 0x4 */
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.cmd0iclkout = 0x00,
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.cmd1csratio = 0x80,
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.cmd1dldiff = 0x04, /* reset value is 0x4 */
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.cmd1iclkout = 0x00,
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.cmd2csratio = 0x80,
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.cmd2dldiff = 0x04, /* reset value is 0x4 */
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.cmd2iclkout = 0x00,
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};
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static struct emif_regs ddr2_emif0_regs = {
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.sdram_config = 0x43801A3A,
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.ref_ctrl = 0x10000C30,
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.sdram_tim1 = 0x0AAB15E2,
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.sdram_tim2 = 0x423631D2,
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.sdram_tim3 = 0x0080032F,
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.emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
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};
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static struct emif_regs ddr2_emif1_regs = {
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.sdram_config = 0x43801A3A,
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.ref_ctrl = 0x10000C30,
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.sdram_tim1 = 0x0AAB15E2,
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.sdram_tim2 = 0x423631D2,
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.sdram_tim3 = 0x0080032F,
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.emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
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};
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#endif
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/*
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* DDR3 related definitions
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*/
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#if defined(CONFIG_TI816X_DDR_PLL_400)
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#define RD_DQS 0x03B
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#define WR_DQS 0x0A6
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#define RD_DQS_GATE 0x12A
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#define EMIF_SDCFG 0x62A41032
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#define EMIF_SDREF 0x10000C30
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#define EMIF_TIM1 0x0CCCE524
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#define EMIF_TIM2 0x30308023
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#define EMIF_TIM3 0x009F82CF
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#define EMIF_PHYCFG 0x0000010B
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#elif defined(CONFIG_TI816X_DDR_PLL_531)
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#define RD_DQS 0x039
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#define WR_DQS 0x0B4
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#define RD_DQS_GATE 0x13D
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#define EMIF_SDCFG 0x62A51832
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#define EMIF_SDREF 0x1000102E
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#define EMIF_TIM1 0x0EF136AC
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#define EMIF_TIM2 0x30408063
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#define EMIF_TIM3 0x009F83AF
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#define EMIF_PHYCFG 0x0000010C
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#elif defined(CONFIG_TI816X_DDR_PLL_675)
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#define RD_DQS 0x039
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#define WR_DQS 0x091
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#define RD_DQS_GATE 0x196
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#define EMIF_SDCFG 0x62A63032
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#define EMIF_SDREF 0x10001491
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#define EMIF_TIM1 0x13358875
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#define EMIF_TIM2 0x5051806C
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#define EMIF_TIM3 0x009F84AF
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#define EMIF_PHYCFG 0x0000010F
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#elif defined(CONFIG_TI816X_DDR_PLL_796)
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#define RD_DQS 0x035
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#define WR_DQS 0x093
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#define RD_DQS_GATE 0x1B3
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#define EMIF_SDCFG 0x62A73832
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#define EMIF_SDREF 0x10001841
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#define EMIF_TIM1 0x1779C9FE
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#define EMIF_TIM2 0x50608074
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#define EMIF_TIM3 0x009F857F
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#define EMIF_PHYCFG 0x00000110
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#endif
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static struct ddr_data ddr3_data = {
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.datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
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.datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
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.datawiratio0 = ((0x20<<10) | 0x20<<0),
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.datagiratio0 = ((0x20<<10) | 0x20<<0),
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.datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
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.datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
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.datauserank0delay = 0x1,
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.datadldiff0 = 0x0, /* depend on cpu rev, set later */
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};
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static const struct cmd_control ddr3_ctrl = {
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.cmd0csratio = 0x100,
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.cmd0dldiff = 0x004, /* reset value is 0x4 */
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.cmd0iclkout = 0x001,
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.cmd1csratio = 0x100,
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.cmd1dldiff = 0x004, /* reset value is 0x4 */
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.cmd1iclkout = 0x001,
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.cmd2csratio = 0x100,
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.cmd2dldiff = 0x004, /* reset value is 0x4 */
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.cmd2iclkout = 0x001,
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};
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static const struct emif_regs ddr3_emif0_regs = {
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.sdram_config = EMIF_SDCFG,
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.ref_ctrl = EMIF_SDREF,
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.sdram_tim1 = EMIF_TIM1,
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.sdram_tim2 = EMIF_TIM2,
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.sdram_tim3 = EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
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};
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static const struct emif_regs ddr3_emif1_regs = {
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.sdram_config = EMIF_SDCFG,
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.ref_ctrl = EMIF_SDREF,
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.sdram_tim1 = EMIF_TIM1,
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.sdram_tim2 = EMIF_TIM2,
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.sdram_tim3 = EMIF_TIM3,
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.emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
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};
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void set_uart_mux_conf(void) {}
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void set_mux_conf_regs(void)
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{
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configure_module_pin_mux(mmc_pin_mux);
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}
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void sdram_init(void)
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{
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config_dmm(&evm_lisa_map_regs);
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#ifdef CONFIG_TI816X_EVM_DDR2
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ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
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ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
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ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
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ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
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if (CONFIG_TI816X_USE_EMIF0) {
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ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
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(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
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config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
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}
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if (CONFIG_TI816X_USE_EMIF1) {
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ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
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(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
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config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
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}
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#endif
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#ifdef CONFIG_TI816X_EVM_DDR3
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ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
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if (CONFIG_TI816X_USE_EMIF0)
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config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
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if (CONFIG_TI816X_USE_EMIF1)
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config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
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#endif
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}
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#endif /* CONFIG_SPL_BUILD */
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@ -255,6 +255,7 @@ am335x_evm_usbspl arm armv7 am335x ti
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am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT
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am43xx_evm arm armv7 am43xx ti am33xx am43xx_evm:SERIAL1,CONS_INDEX=1
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ti814x_evm arm armv7 ti814x ti am33xx
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ti816x_evm arm armv7 ti816x ti am33xx
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pcm051 arm armv7 pcm051 phytec am33xx pcm051
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sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC
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sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH
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180
include/configs/ti816x_evm.h
Normal file
180
include/configs/ti816x_evm.h
Normal file
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/*
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* ti816x_evm.h
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*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_TI816X_EVM_H
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#define __CONFIG_TI816X_EVM_H
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#define CONFIG_TI81XX
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#define CONFIG_TI816X
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_OMAP
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#define CONFIG_OMAP_COMMON
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#define CONFIG_ARCH_CPU_INIT
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#include <asm/arch/omap.h>
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
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#define CONFIG_SYS_LONGHELP /* undef save memory */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "u-boot/ti816x# "
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#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
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#define CONFIG_OF_LIBFDT
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG /* required for ramdisk support */
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#include <config_cmd_default.h> /* u-boot default commands */
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_BOOTDELAY 3 /* set negative for no autoboot */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x81000000\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc rescan;" \
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"fatload mmc 0 ${loadaddr} uImage;" \
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"bootm ${loadaddr}" \
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#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
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/* Clock Defines */
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#define V_OSCK 24000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_SYS_MAXARGS 32
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#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
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+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
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#undef CONFIG_SYS_CLKS_IN_HZ
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#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
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#define CONFIG_SYS_HZ 1000 /* 1ms clock */
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#define CONFIG_CMD_ASKEN
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#define CONFIG_CMD_ECHO
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#define CONFIG_OMAP_GPIO
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_CMD_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_FS_FAT
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/*
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* Only one of the following two options (DDR3/DDR2) should be enabled
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* CONFIG_TI816X_EVM_DDR2
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* CONFIG_TI816X_EVM_DDR3
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*/
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#define CONFIG_TI816X_EVM_DDR3
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/*
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* Supported values: 400, 531, 675 or 796 MHz
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*/
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#define CONFIG_TI816X_DDR_PLL_796
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#define CONFIG_TI816X_USE_EMIF0 1
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#define CONFIG_TI816X_USE_EMIF1 1
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#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
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#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
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#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
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#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
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#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
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#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
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GENERATED_GBL_DATA_SIZE)
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/**
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* Platform/Board specific defs
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*/
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#define CONFIG_SYS_CLK_FREQ 27000000
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#define CONFIG_SYS_TIMERBASE 0x4802E000
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#undef CONFIG_NAND_OMAP_GPMC
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/*
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* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK (48000000)
|
||||
#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* allow overwriting serial config and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SERIAL1
|
||||
#define CONFIG_SERIAL2
|
||||
#define CONFIG_SERIAL3
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
/* SPL */
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40400000
|
||||
#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
|
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
|
||||
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
|
||||
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
|
||||
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
||||
|
||||
/* Since SPL did pll and ddr initialization for us,
|
||||
* we don't need to do it twice.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
|
||||
/* Unsupported features */
|
||||
#undef CONFIG_USE_IRQ
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user