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add new CONFIG_AT91_LEGACY
* add's the new temporary CONFIG_AT91_LEGACY to all board configs This will need for backward compatiblity, while change the SoC access to c structures. If CONFIG_AT91_LEGACY is defined, the deprecated SoC is used. Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
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doc/README.at91-soc
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41
doc/README.at91-soc
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New C structure AT91 SoC access
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=================================
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The goal
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--------
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Currently the at91 arch uses hundreds of address defines and special
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at91_xxxx_write/read functions to access the SOC.
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The u-boot project perferred method is to access memory mapped hw
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regisister via a c structure.
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e.g. old
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*AT91C_PIOA_IDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
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*AT91C_PIOC_PUDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
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*AT91C_PIOC_PER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
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*AT91C_PIOC_OER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
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*AT91C_PIOC_PIO = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
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at91_sys_write(AT91_RSTC_CR,
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AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
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e.g new
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pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
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writel(pin, &pio->pioa.idr);
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writel(pin, &pio->pioa.pudr);
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writel(pin, &pio->pioa.per);
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writel(pin, &pio->pioa.oer);
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writel(pin, &pio->pioa.sodr);
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writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST |
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AT91_RSTC_CR_PERRST, &rstc->cr);
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The method for updating
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------------------------
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1. add's the temporary CONFIG_AT91_LEGACY to all at91 board configs
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2. Display a compile time warning, if the board has not been converted
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3. add new structures for SoC access
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4. Convert arch, driver and boards file to new SoC
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5. remove legacy code, if all boards and drives are ready
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@ -26,6 +26,8 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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@ -27,6 +27,8 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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/*
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* from 18.432 MHz crystal
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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#define CONFIG_DISPLAY_CPUINFO 1
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#define AT91_MAIN_CLOCK 18432000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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#ifdef CONFIG_CPUAT91_RAM
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#define CONFIG_SKIP_LOWLEVEL_INIT 1
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#define CONFIG_SKIP_RELOCATE_UBOOT 1
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
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#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */
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#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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/* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MAIN_CLOCK 179712000
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* Common stuff */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq */
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#define CONFIG_MEESC 1 /* Board is esd MEESC */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
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#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define AT91_CPU_NAME "AT91SAM9261"
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* ARM asynchronous clock */
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
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#define CONFIG_SBC35_A9G20
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#endif
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
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#define CONFIG_TNY_A9260
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#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)
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