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Merge with /home/hs/U-Boot/u-boot-dev

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This commit is contained in:
Wolfgang Denk 2006-06-10 19:27:47 +02:00
commit 4176c79964
23 changed files with 2452 additions and 150 deletions
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7
CHANGELOG
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@ -2,6 +2,13 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add MCF5282 support (without preloader)
relocate ichache_State to ram
u-boot can run from internal flash
Add EB+MCF-EV123 board support.
Add m68k Boards to MAKEALL
Patch from Jens Scharsig, 08 Aug 2005
* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
Patch by Scott McNutt, 08 Jun 2006

23
MAKEALL
View File

@ -255,29 +255,38 @@ LIST_x86="${LIST_I486}"
#########################################################################
LIST_nios=" \
ADNPESC1 ADNPESC1_base_32 \
ADNPESC1 ADNPESC1_base_32 \
ADNPESC1_DNPEVA2_base_32 \
DK1C20 DK1C20_standard_32 \
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
DK1C20 DK1C20_standard_32 \
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
"
#########################################################################
## Nios-II Systems
#########################################################################
LIST_nios2="PCI5441 PK1C20 EP1C20 EP1S10 EP1S40"
LIST_nios2=" \
EP1C20 EP1S10 EP1S40 \
PCI5441 PK1C20 \
"
#########################################################################
## MicroBlaze Systems
#########################################################################
LIST_microblaze="suzaku"
LIST_microblaze=" \
suzaku
"
#########################################################################
## ColdFire Systems
#########################################################################
LIST_coldfire="cobra5272 M5272C3 M5282EVB TASREG r5200 M5271EVB"
LIST_coldfire=" \
cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \
M5271EVB M5272C3 M5282EVB TASREG \
r5200 M5271EVB \
"
#-----------------------------------------------------------------------
@ -292,7 +301,7 @@ build_target() {
${MAKE} distclean >/dev/null
${MAKE} ${target}_config
${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
# ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
}
#-----------------------------------------------------------------------

19
Makefile
View File

@ -1300,9 +1300,6 @@ VoVPN-GW_100MHz_config: unconfig
ZPC1900_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
#========================================================================
# M68K
#========================================================================
#########################################################################
## Coldfire
#########################################################################
@ -1310,6 +1307,19 @@ ZPC1900_config: unconfig
cobra5272_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
EB+MCF-EV123_config : unconfig
@ >include/config.h
@echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk
@./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
EB+MCF-EV123_internal_config : unconfig
@ >include/config.h
@echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk
@./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
M5271EVB_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
M5272C3_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
@ -1322,9 +1332,6 @@ TASREG_config : unconfig
r5200_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 r5200
M5271EVB_config : unconfig
@./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
#########################################################################
## MPC83xx Systems
#########################################################################

162
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c Normal file
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@ -0,0 +1,162 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include "asm/m5282.h"
#include "VCxK.h"
int checkboard (void)
{
puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
puts (" Boot from Internal FLASH\n");
#endif
return 0;
}
long int initdram (int board_type)
{
int size,i;
size = 0;
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC((15 * CFG_CLK)>>4);
#ifdef CFG_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_16);
MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M
| MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
*(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
for (i=0; i < 2000; i++)
asm(" nop");
mbar_writeLong(MCFSDRAMC_DACR0, mbar_readLong(MCFSDRAMC_DACR0)
| MCFSDRAMC_DACR_IMRS);
*(unsigned int *)(CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE * 1024 * 1024;
#endif
#ifdef CFG_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_16;
MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M
| MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
*(unsigned short *)(CFG_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i=0; i < 2000; i++)
asm(" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE1 * 1024 * 1024;
#endif
return size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
int misc_init_r(void)
{
init_vcxk();
return 1;
}
/*---------------------------------------------------------------------------*/
int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
ulong source;
switch (argc) {
case 2:
source = simple_strtoul(argv[1],NULL,16);
vcxk_loadimage(source);
rcode = 0;
break;
default:
printf ("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
break;
}
return rcode;
}
/***************************************************/
U_BOOT_CMD(
vcimage, 2, 0, do_vcimage,
"vcimage - loads an image to Display\n",
"vcimage addr\n"
);
/* EOF EB+MCF-EV123c */

40
board/BuS/EB+MCF-EV123/Makefile Normal file
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@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

136
board/BuS/EB+MCF-EV123/VCxK.c Normal file
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@ -0,0 +1,136 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/m5282.h>
#include "VCxK.h"
vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
#define VCXK_BWS vcxk_bws
static ulong vcxk_driver;
ulong search_vcxk_driver(void);
void vcxk_cls(void);
void vcxk_setbrightness(short brightness);
int vcxk_request(void);
int vcxk_acknowledge_wait(void);
void vcxk_clear(void);
int init_vcxk(void)
{
VIDEO_Invert_CFG &= ~VIDEO_Invert_IO;
VIDEO_INVERT_PORT |= VIDEO_INVERT_PIN;
VIDEO_INVERT_DDR |= VIDEO_INVERT_PIN;
VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
VIDEO_REQUEST_DDR |= VIDEO_REQUEST_PIN;
VIDEO_ACKNOWLEDGE_DDR &= ~VIDEO_ACKNOWLEDGE_PIN;
vcxk_driver = search_vcxk_driver();
if (vcxk_driver)
{
/* use flash resist driver */
}
else
{
vcxk_cls();
vcxk_cls();
vcxk_setbrightness(1000);
}
VIDEO_ENABLE_DDR |= VIDEO_ENABLE_PIN;
VIDEO_ENABLE_PORT |= VIDEO_ENABLE_PIN;
VIDEO_ENABLE_PORT &= ~VIDEO_ENABLE_PIN;
return 1;
}
void vcxk_loadimage(ulong source)
{
int cnt;
vcxk_acknowledge_wait();
for (cnt=0; cnt<16384; cnt++)
{
VCXK_BWS[cnt*2] = (*(vu_char*) source);
source++;
}
vcxk_request();
}
void vcxk_cls(void)
{
vcxk_acknowledge_wait();
vcxk_clear();
vcxk_request();
}
void vcxk_clear(void)
{
int cnt;
for (cnt=0; cnt<16384; cnt++)
{
VCXK_BWS[cnt*2] = 0x00;
}
}
void vcxk_setbrightness(short brightness)
{
VCXK_BWS[0x8000]=(brightness >> 4) +2;
VCXK_BWS[0xC000]= (brightness + 23) >> 8;
VCXK_BWS[0xC001]= (brightness + 23) & 0xFF;
}
int vcxk_request(void)
{
if (vcxk_driver)
{
/* use flash resist driver */
}
else
{
VIDEO_REQUEST_PORT &= ~VIDEO_REQUEST_PIN;
VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
}
return 1;
}
int vcxk_acknowledge_wait(void)
{
if (vcxk_driver)
{
/* use flash resist driver */
}
else
{
while (!(VIDEO_ACKNOWLEDGE_PORT & VIDEO_ACKNOWLEDGE_PIN));
}
return 1;
}
ulong search_vcxk_driver(void)
{
return 0;
}
/* eof */

48
board/BuS/EB+MCF-EV123/VCxK.h Normal file
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@ -0,0 +1,48 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __VCXK_H_
#define __VCXK_H_
extern int init_vcxk(void);
void vcxk_loadimage(ulong source);
#define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
#define VIDEO_ACKNOWLEDGE_PIN 0x0001
#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT
#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR
#define VIDEO_ENABLE_PIN 0x0002
#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT
#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR
#define VIDEO_REQUEST_PIN 0x0004
#define VIDEO_Invert_CFG MCFGPIO_PEPAR
#define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2
#define VIDEO_INVERT_PORT MCFGPIO_PORTE
#define VIDEO_INVERT_DDR MCFGPIO_DDRE
#define VIDEO_INVERT_PIN MCFGPIO_PORT2
#endif

212
board/BuS/EB+MCF-EV123/cfm_flash.c Normal file
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@ -0,0 +1,212 @@
/*
* Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/m5282.h>
#include "cfm_flash.h"
#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
#if (CFG_CLK>20000000)
#define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
#else
#define CFM_CLK ((long) CFG_CLK / 400000 + 1)
#endif
#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \
(CFG_MBAR & 0xC0000000))
void cfm_flash_print_info (flash_info_t * info)
{
printf ("Freescale: ");
switch (info->flash_id & FLASH_TYPEMASK) {
case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
printf ("MCF5281 internal FLASH\n");
break;
case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
printf ("MCF5282 internal FLASH\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
}
void cfm_flash_init (flash_info_t * info)
{
int sector;
ulong protection;
MCFCFM_MCR = 0;
MCFCFM_CLKD = CFM_CLK;
debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CFG_CLK);
MCFCFM_SACC = 0;
MCFCFM_DACC = 0;
if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
puts("CFM backdoor access is enabled\n");
if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
puts("CFM securety is enabled\n");
#ifdef CONFIG_M5281
info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
(FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
info->size = 256*1024;
info->sector_count = 16;
#else
info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
(FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
info->size = 512*1024;
info->sector_count = 32;
#endif
protection = MCFCFM_PROT;
for (sector = 0; sector < info->sector_count; sector++)
{
if (sector == 0)
{
info->start[sector] = CFG_INT_FLASH_BASE;
}
else
{
info->start[sector] = info->start[sector-1] + 0x04000;
}
info->protect[sector] = protection & 1;
protection >>= 1;
}
}
int cfm_flash_readycheck(int checkblank)
{
int rc;
unsigned char state;
rc = ERR_OK;
while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
state = MCFCFM_USTAT;
if (state & MCFCFM_USTAT_ACCERR)
{
debug ("%s(): CFM access error",__FUNCTION__);
rc = ERR_PROG_ERROR;
}
if (state & MCFCFM_USTAT_PVIOL)
{
debug ("%s(): CFM protection violation",__FUNCTION__);
rc = ERR_PROTECTED;
}
if (checkblank)
{
if (!(state & MCFCFM_USTAT_BLANK))
{
debug ("%s(): CFM erras error",__FUNCTION__);
rc = ERR_NOT_ERASED;
}
}
MCFCFM_USTAT = state & 0x34; /* reset state */
return rc;
}
/* Erase 16KiB = 8 2KiB pages */
int cfm_flash_erase_sector (flash_info_t * info, int sector)
{
ulong address;
int page;
int rc;
rc= ERR_OK;
address = cmf_backdoor_address(info->start[sector]);
for (page=0; (page<8) && (rc==ERR_OK); page++)
{
*(volatile __u32*) address = 0;
MCFCFM_CMD = MCFCFM_CMD_PGERS;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(0);
if (rc==ERR_OK)
{
*(volatile __u32*) address = 0;
MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(1);
}
address += 0x800;
}
return rc;
}
int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
ulong dest, data;
rc = ERR_OK;
if (addr & 3)
{
debug ("Byte and Word alignment not supported\n");
rc = ERR_ALIGN;
}
if (cnt & 3)
{
debug ("Byte and Word transfer not supported\n");
rc = ERR_ALIGN;
}
dest = cmf_backdoor_address(addr);
while ((cnt>=4) && (rc == ERR_OK))
{
data =*((volatile u32 *) src);
*(volatile u32*) dest = data;
MCFCFM_CMD = MCFCFM_CMD_PGM;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(0);
if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
src +=4;
dest +=4;
addr +=4;
cnt -=4;
}
return rc;
}
#ifdef CFG_FLASH_PROTECTION
int cfm_flash_protect(flash_info_t * info,long sector,int prot)
{
int rc;
rc= ERR_OK;
if (prot)
{
MCFCFM_PROT |= (1<<sector);
info->protect[sector]=1;
}
else
{
MCFCFM_PROT &= ~(1<<sector);
info->protect[sector]=0;
}
return rc;
}
#endif
#endif

40
board/BuS/EB+MCF-EV123/cfm_flash.h Normal file
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@ -0,0 +1,40 @@
/*
* Basic Flash Driver for Freescale MCF 5282 internal FLASH
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CFM_FLASH_H_
#define __CFM_FLASH_H_
#define FREESCALE_MANUFACT 0xFACFFACF
#define FREESCALE_ID_MCF5281 0x5281
#define FREESCALE_ID_MCF5282 0x5282
extern void cfm_flash_print_info (flash_info_t * info);
extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
extern void cfm_flash_init (flash_info_t * info);
extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
#ifdef CFG_FLASH_PROTECTION
extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
#endif
#endif

28
board/BuS/EB+MCF-EV123/config.mk Normal file
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@ -0,0 +1,28 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk
ifndef TEXT_BASE
TEXT_BASE = 0xFE000000
endif

413
board/BuS/EB+MCF-EV123/flash.c Normal file
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@ -0,0 +1,413 @@
/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* Based On
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "cfm_flash.h"
#define PHYS_FLASH_1 CFG_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
printf ("AMD: ");
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_LV160B & FLASH_TYPEMASK):
printf ("AM29LV160B (16Bit)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
break;
case FREESCALE_MANUFACT & FLASH_VENDMASK:
cfm_flash_print_info (info);
break;
default:
printf ("Unknown Vendor ");
break;
}
puts (" Size: ");
if ((info->size >> 20) > 0)
{
printf ("%ld MiB",info->size >> 20);
}
else
{
printf ("%ld KiB",info->size >> 10);
}
printf (" in %d Sectors\n", info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 4) == 0) {
printf ("\n ");
}
printf ("%02d: %08lX%s ", i,info->start[i],
info->protect[i] ? " P" : " ");
}
printf ("\n\n");
}
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
switch (i)
{
case 1:
flash_info[i].flash_id =
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV160B & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
flashbase = PHYS_FLASH_1;
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j == 0) {
/* 1st is 16 KiB */
flash_info[i].start[j] = flashbase;
}
if ((j >= 1) && (j <= 2)) {
/* 2nd and 3rd are 8 KiB */
flash_info[i].start[j] =
flashbase + 0x4000 + 0x2000 * (j - 1);
}
if (j == 3) {
/* 4th is 32 KiB */
flash_info[i].start[j] = flashbase + 0x8000;
}
if ((j >= 4) && (j <= 34)) {
/* rest is 256 KiB */
flash_info[i].start[j] =
flashbase + 0x10000 + 0x10000 * (j - 4);
}
}
break;
case 0:
cfm_flash_init (&flash_info[i]);
break;
default:
panic ("configured to many flash banks!\n");
}
size += flash_info[i].size;
}
flash_protect (FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + 0xffff, &flash_info[0]);
return size;
}
#define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055
#define CMD_ERASE_SETUP 0x0080
#define CMD_ERASE_CONFIRM 0x0030
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
#define BIT_PROGRAM_ERROR 0x0020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define ERR_READY -1
int amd_flash_erase_sector(flash_info_t * info, int sector)
{
int state;
ulong result;
volatile u16 *addr =
(volatile u16 *) (info->start[sector]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
state = 0;
set_timer (0);
do {
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
state = ERR_TIMOUT;
}
if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
state = ERR_READY;
}
while (!state);
if (state == ERR_READY)
state = ERR_OK;
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
return state;
}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int iflag, cflag;
int sector;
int rc;
rc = ERR_OK;
if (info->flash_id == FLASH_UNKNOWN)
{
rc = ERR_UNKNOWN_FLASH_TYPE;
} /* (info->flash_id == FLASH_UNKNOWN) */
if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
{
rc = ERR_INVAL;
}
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
if (info->protect[sector])
{
putc('P'); /* protected sector will not erase */
}
else
{
/* erase on unprotected sector */
puts("E\b");
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_erase_sector(info,sector);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_erase_sector(info,sector);
break;
default:
return ERR_UNKNOWN_FLASH_VENDOR;
}
putc('.');
}
}
if (rc!=ERR_OK)
{
printf ("\n ");
flash_perror (rc);
}
else
{
printf (" done\n");
}
udelay (10000); /* allow flash to settle - wait 10 ms */
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
{
volatile u16 *addr;
ulong result;
int cflag, iflag;
int state;
/*
* Check if Flash is (sufficiently) erased
*/
addr = (volatile u16 *) dest;
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
set_timer (0);
/* wait until flash is ready */
state = 0;
do {
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
state = ERR_TIMOUT;
}
if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
state = ERR_READY;
} while (!state);
*addr = CMD_READ_ARRAY;
if (state == ERR_READY)
state = ERR_OK;
if ((*addr != data) && (state != ERR_TIMOUT))
state = ERR_PROG_ERROR;
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return state;
}
int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
ulong dest;
u16 data;
rc = ERR_OK;
if (addr & 1)
{
debug ("Byte alignment not supported\n");
rc = ERR_ALIGN;
}
if (cnt & 1)
{
debug ("Byte transfer not supported\n");
rc = ERR_ALIGN;
}
dest = addr;
while ((cnt>=2) && (rc == ERR_OK))
{
data =*((volatile u16 *) src);
rc=amd_write_word (info,dest,data);
src +=2;
dest +=2;
cnt -=2;
}
return rc;
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_write_buff(info,src,addr,cnt);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_write_buff(info,src,addr,cnt);
break;
default:
rc = ERR_UNKNOWN_FLASH_VENDOR;
}
return rc;
}
int amd_flash_protect(flash_info_t * info,long sector,int prot)
{
int rc;
rc= ERR_OK;
if (prot)
{
info->protect[sector]=1;
}
else
{
info->protect[sector]=0;
}
return rc;
}
#ifdef CFG_FLASH_PROTECTION
int flash_real_protect(flash_info_t * info,long sector,int prot)
{
int rc;
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_protect(info,sector,prot);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_protect(info,sector,prot);
break;
default:
rc = ERR_UNKNOWN_FLASH_VENDOR;
}
return rc;
}
#endif

1
board/BuS/EB+MCF-EV123/textbase.mk Normal file
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@ -0,0 +1 @@
TEXT_BASE = 0xF0000000

141
board/BuS/EB+MCF-EV123/u-boot.lds Normal file
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@ -0,0 +1,141 @@
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
common/dlmalloc.o (.text)
lib_generic/string.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset; */
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}

2
config.mk
View File

@ -112,7 +112,7 @@ OBJDUMP = $(CROSS_COMPILE)objdump
RANLIB = $(CROSS_COMPILE)RANLIB
RELFLAGS= $(PLATFORM_RELFLAGS)
DBGFLAGS= -g #-DDEBUG
DBGFLAGS= -g # -DDEBUG
OPTFLAGS= -Os #-fomit-frame-pointer
ifndef LDSCRIPT
#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug

26
cpu/mcf52x2/cpu.c
View File

@ -2,6 +2,10 @@
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* MCF5282 additionals
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -36,7 +40,8 @@
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#include <asm/immap_5282.h>
#endif
#ifdef CONFIG_M5249
@ -116,7 +121,6 @@ int checkcpu(void) {
return 0;
};
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset (void)
@ -158,11 +162,25 @@ int watchdog_init (void)
#ifdef CONFIG_M5282
int checkcpu (void)
{
puts ("CPU: Freescale Coldfire MCF5282\n");
unsigned char resetsource = MCFRESET_RSR;
printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
printf ("Reset:%s%s%s%s%s%s%s\n",
(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""
);
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
};
#endif

177
cpu/mcf52x2/cpu_init.c
View File

@ -2,6 +2,10 @@
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
* MCF5282 additionals
* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -172,7 +176,180 @@ int cpu_init_r (void)
*/
void cpu_init_f (void)
{
#ifndef CONFIG_WATCHDOG
/* disable watchdog if we aren't using it */
MCFWTM_WCR = 0;
#endif
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
/* Set up the GPIO ports */
#ifdef CFG_PEPAR
MCFGPIO_PEPAR = CFG_PEPAR;
#endif
#ifdef CFG_PFPAR
MCFGPIO_PFPAR = CFG_PFPAR;
#endif
#ifdef CFG_PJPAR
MCFGPIO_PJPAR = CFG_PJPAR;
#endif
#ifdef CFG_PSDPAR
MCFGPIO_PSDPAR = CFG_PSDPAR;
#endif
#ifdef CFG_PASPAR
MCFGPIO_PASPAR = CFG_PASPAR;
#endif
#ifdef CFG_PEHLPAR
MCFGPIO_PEHLPAR = CFG_PEHLPAR;
#endif
#ifdef CFG_PQSPAR
MCFGPIO_PQSPAR = CFG_PQSPAR;
#endif
#ifdef CFG_PTCPAR
MCFGPIO_PTCPAR = CFG_PTCPAR;
#endif
#ifdef CFG_PTDPAR
MCFGPIO_PTDPAR = CFG_PTDPAR;
#endif
#ifdef CFG_PUAPAR
MCFGPIO_PUAPAR = CFG_PUAPAR;
#endif
#ifdef CFG_DDRUA
MCFGPIO_DDRUA = CFG_DDRUA;
#endif
/* This is probably a bad place to setup chip selects, but everyone
else is doing it! */
#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
defined(CFG_CS0_WS)
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
#if (CFG_CS0_WIDTH == 8)
#define CFG_CS0_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS0_WIDTH == 16)
#define CFG_CS0_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS0_WIDTH == 32)
#define CFG_CS0_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
#endif
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
|CFG_CS0_PS
|MCFCSM_CSCR_AA;
#if (CFG_CS0_RO != 0)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
|MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
#else
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
#endif
#else
#waring "Chip Select 0 are not initialized/used"
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
defined(CFG_CS1_WS)
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
#if (CFG_CS1_WIDTH == 8)
#define CFG_CS1_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS1_WIDTH == 16)
#define CFG_CS1_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS1_WIDTH == 32)
#define CFG_CS1_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
|CFG_CS1_PS
|MCFCSM_CSCR_AA;
#if (CFG_CS1_RO != 0)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
|MCFCSM_CSMR_WP
|MCFCSM_CSMR_V;
#else
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
|MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 1 are not initialized/used"
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
defined(CFG_CS2_WS)
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
#if (CFG_CS2_WIDTH == 8)
#define CFG_CS2_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS2_WIDTH == 16)
#define CFG_CS2_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS2_WIDTH == 32)
#define CFG_CS2_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
#endif
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
|CFG_CS2_PS
|MCFCSM_CSCR_AA;
#if (CFG_CS2_RO != 0)
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
|MCFCSM_CSMR_WP
|MCFCSM_CSMR_V;
#else
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
|MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 2 are not initialized/used"
#endif
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
defined(CFG_CS3_WS)
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
#if (CFG_CS3_WIDTH == 8)
#define CFG_CS3_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS3_WIDTH == 16)
#define CFG_CS3_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS3_WIDTH == 32)
#define CFG_CS3_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
|CFG_CS3_PS
|MCFCSM_CSCR_AA;
#if (CFG_CS3_RO != 0)
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
|MCFCSM_CSMR_WP
|MCFCSM_CSMR_V;
#else
MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
|MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 3 are not initialized/used"
#endif
#endif /* CONFIG_MONITOR_IS_IN_RAM */
/* defer enabling cache until boot (see do_go) */
/* icache_enable(); */
}
/*

33
cpu/mcf52x2/fec.c
View File

@ -205,7 +205,9 @@ int eth_rx (void)
int eth_init (bd_t * bd)
{
#ifndef CFG_ENET_BD_BASE
DECLARE_GLOBAL_DATA_PTR;
#endif
int i;
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
@ -258,6 +260,10 @@ int eth_init (bd_t * bd)
#else
/* Clear multicast address hash table
*/
#ifdef CONFIG_M5282
fecp->fec_ihash_table_high = 0;
fecp->fec_ihash_table_low = 0;
#else
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
#endif
@ -273,7 +279,16 @@ int eth_init (bd_t * bd)
txIdx = 0;
if (!rtx) {
#ifdef CFG_ENET_BD_BASE
rtx = (RTXBD *) CFG_ENET_BD_BASE;
#else
rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
(((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
+0xFF)
& ~0xFF)
);
debug("set ENET_DB_BASE to %lX\n",(long) rtx);
#endif
}
/*
@ -307,18 +322,18 @@ int eth_init (bd_t * bd)
/* Enable MII mode
*/
#if 0 /* Full duplex mode */
#if 0 /* Full duplex mode */
fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
#else /* Half duplex mode */
fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
#ifdef CONFIG_M5271
fecp->fec_r_cntrl |= (PKT_MAXBUF_SIZE << 16); /* set max frame length */
#endif
#else /* Half duplex mode */
fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
fecp->fec_x_cntrl = 0;
#endif
/* Set MII speed */
fecp->fec_mii_speed = 0x0e;
fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
fecp->fec_mii_speed *= 2;
/* Configure port B for MII.
*/
@ -422,7 +437,7 @@ static void mii_discover_phy (void)
*/
udelay (10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf ("PHY type 0x%x pass %d type ", phytype, pass);

95
cpu/mcf52x2/serial.c
View File

@ -55,45 +55,75 @@ void rs_serial_setbaudrate(int port,int baudrate)
{
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
volatile unsigned char *uartp;
#ifndef CONFIG_M5271
# ifndef CONFIG_M5271
double fraction;
#endif
# endif
double clock;
if (port == 0)
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
else
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
clock = DoubleClock(baudrate); /* Set baud above */
uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
#ifndef CONFIG_M5271
fraction = ((clock - (int)clock) * 16.0) + 0.5;
uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
#endif
#endif
};
void rs_serial_init(int port,int baudrate)
{
volatile unsigned char *uartp;
/*
* Reset UART, get it into known state...
*/
if (port == 0)
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
else
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
clock = DoubleClock(baudrate); /* Set baud above */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */
uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
# ifndef CONFIG_M5271
fraction = ((clock - (int)clock) * 16.0) + 0.5;
uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
# endif
#endif
#if defined(CONFIG_M5282)
volatile unsigned char *uartp;
long clock;
switch (port) {
case 1:
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
break;
case 2:
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
break;
default:
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
}
clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */
uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */
#endif
};
void rs_serial_init (int port, int baudrate)
{
volatile unsigned char *uartp;
/*
* Reset UART, get it into known state...
*/
switch (port) {
case 1:
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
break;
#if defined(CONFIG_M5282)
case 2:
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
break;
#endif
default:
uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
}
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */
/*
* Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity.
@ -107,7 +137,7 @@ void rs_serial_init(int port,int baudrate)
/* Set clock Select Register: Tx/Rx clock is timer */
uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
rs_serial_setbaudrate(port,baudrate);
rs_serial_setbaudrate (port, baudrate);
/* Enable Tx/Rx */
uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE;
@ -169,9 +199,8 @@ void serial_putc(const char c) {
}
void serial_puts (const char *s) {
while (*s) {
while (*s)
serial_putc(*s++);
}
}
int serial_getc(void) {

103
cpu/mcf52x2/start.S
View File

@ -55,11 +55,15 @@
*/
_vectors:
#ifndef CONFIG_R5200
.long 0x00000000, _START
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_R5200)
.long 0x400
#elif defined(CONFIG_M5282)
.long _start - TEXT_BASE
#else
.long 0x00000000, 0x400 /* Flash offset is 0 until we setup CS0 */
.long _START
#endif
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@ -100,20 +104,23 @@ _vectors:
.text
#if defined(CFG_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
.long 0x00000000 /* programm/data space restriction */
.long 0x00000000 /* Flash security */
#endif
#endif
.globl _start
_start:
nop
nop
move.w #0x2700,%sr
/* if we come from a pre-loader we have no exception table and
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
move.l #CFG_FLASH_BASE, %d0
movec %d0, %VBR
#endif
#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
@ -128,20 +135,48 @@ _start:
movec %d0, %RAMBAR0
#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* Initialize IPSBAR */
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
#ifdef CONFIG_M5282
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
movec %d0, %RAMBAR0
#endif
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
move.l #(CFG_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
jmp CFG_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
movec %d0, %RAMBAR0
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
nop
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
movec %d0, %RAMBAR0
#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
#endif
/* if we come from a pre-loader we have no exception table and
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
move.l #CFG_FLASH_BASE, %d0
movec %d0, %VBR
#endif
#ifdef CONFIG_R5200
@ -218,7 +253,6 @@ relocate_code:
move.l #CFG_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
@ -229,14 +263,14 @@ relocate_code:
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
move.l %a0, %a1
move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
/*
/*
* Now clear BSS segment
*/
move.l %a0, %a1
@ -266,6 +300,23 @@ clear_bss:
cmp.l %a2, %a1
bne 7b
#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
/* patch the 3 accesspoints to 3 ichache_state */
/* quick and dirty */
move.l %a0,%d1
add.l #(icache_state - CFG_MONITOR_BASE),%d1
move.l %a0,%a1
add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
move.l %d1,(%a1)
#endif
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
@ -273,6 +324,10 @@ clear_bss:
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
defined(CFG_HALT_BEFOR_RAM_JUMP)
halt
#endif
jsr (%a1)
/*------------------------------------------------------------------------------*/
@ -327,6 +382,7 @@ icache_enable:
move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
movec %d0, %CACR /* Enable cache */
moveq #1, %d0
icache_state_access_1:
move.l %d0, icache_state
rts
#endif
@ -361,18 +417,19 @@ icache_disable:
movec %d0, %ACR0 /* Enable cache */
movec %d0, %ACR1 /* Enable cache */
moveq #0, %d0
icache_state_access_2:
move.l %d0, icache_state
rts
.globl icache_status
icache_status:
icache_state_access_3:
move.l icache_state, %d0
rts
.data
icache_state:
.long 1
.long 0 /* cache is diabled on inirialization */
/*------------------------------------------------------------------------------*/

66
doc/README.m68k
View File

@ -1,7 +1,12 @@
U-Boot for Motorola M68K
Last Update: January 12, 2004
====================================================================
History
August 08,2005; Jens Scharsig <esw@bus-elektronik.de>
MCF5282 implementation without preloader
January 12, 2004; <josef.baumgartner@telex.de>
====================================================================
This file contains status information for the port of U-Boot to the
@ -33,16 +38,8 @@ CPU specific code is located in: cpu/mcf52x2
-----------------------------
CPU specific code is located in: cpu/mcf52x2
At the moment the code isn't fully implemented and still needs a pre-loader!
The preloader must initialize the processor and then start u-boot. The board
must be configured for a pre-loader (see 4.1)
For the preloader, please see
http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
U-boot is configured to run at 0x20000 at default. This can be configured by
change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
include/configs/M5282EVB.h.
The MCF5282 Port no longer needs a preloader and can place in external or
internal FLASH.
3. SUPPORTED BOARDs
@ -67,6 +64,27 @@ Board specific code is located in: board/m5282evb
To configure the board, type: make M5272C3_config
At the moment the code isn't fully implemented and still needs a pre-loader!
The preloader must initialize the processor and then start u-boot. The board
must be configured for a pre-loader (see 4.1)
For the preloader, please see
http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
U-boot is configured to run at 0x20000 at default. This can be configured by
change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
include/configs/M5282EVB.h.
3.2 BuS EB+MCF-EV123
---------------------
Board specific code is located in: board/bus/EB+MCF-EV123
To configure the board, type:
make EB+MCF-EV123_config for external FLASH
make EB+MCF-EV123_internal_config for internal FLASH
4. CONFIGURATION OPTIONS/SETTINGS
----------------------------------
@ -80,7 +98,6 @@ be compiled in. The start address of u-boot must be adjusted in
the boards config header file (CFG_MONITOR_BASE) and Makefile
(TEXT_BASE) to the load address.
4.1 MCF5272 specific Options/Settings
-------------------------------------
@ -123,14 +140,27 @@ CFG_INT_FLASH_BASE
CFG_ENET_BD_BASE
-- defines the base addres of the FEC buffer descriptors
CFG_MFD
-- defines the PLL Multiplication Factor Devider
(see table 9-4 of MCF user manual)
CFG_RFD -- defines the PLL Reduce Frecuency Devider
(see table 9-4 of MCF user manual)
CFG_CSx_BASE -- defines the base address of chip select x
CFG_CSx_SIZE -- defines the memory size (address range) of chip select x
CFG_CSx_WIDTH -- defines the bus with of chip select x
CFG_CSx_RO -- if set to 0 chip select x is read/wirte
else chipselct is read only
CFG_CSx_WS -- defines the number of wait states of chip select x
CFG_PxDDR -- defines the contents of the Data Direction Registers
CFG_PxDAT -- defines the contents of the Data Registers
CFG_PXCNT -- defines the contents of the Port Configuration Registers
CFG_PxPAR -- defines the function of ports
5. COMPILER
-----------
To create U-Boot the gcc-2.95.3 compiler set (m68k-elf-20030314) from uClinux.org was used.
You can download it from: http://www.uclinux.org/pub/uClinux/m68k-elf-tools/
Regards,
Josef
<josef.baumgartner@telex.de>

82
include/asm-m68k/immap_5282.h
View File

@ -25,39 +25,63 @@
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
struct sys_ctrl {
uint ipsbar;
char res1[4];
uint rambar;
char res2[4];
uchar crsr;
uchar cwcr;
uchar lpicr;
uchar cwsr;
uint dmareqc;
char res3[4];
uint mpark;
/* TODO: finish these */
};
/* Fast ethernet controller registers
*/
typedef struct fec {
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res7[21]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x9e]; /* reserved */
uint fec_addr_low; /* lower 32 bits of station address */
uint fec_addr_high; /* upper 16 bits of station address */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uchar fec_fifo[960]; /* fifo RAM */
uint res1; /* reserved 1000*/
uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
uint res2; /* reserved 100c*/
uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
uint res3[3]; /* reserved 1018*/
uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
uint res4[6]; /* reserved 1028*/
uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
/*1044*/
uint res5[7]; /* reserved 1048*/
uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
uint res6[7]; /* reserved 1068*/
uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
uint res7[15]; /* reserved 1088*/
uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
uint res8[7]; /* reserved 10C8*/
uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
uint res9[10]; /* reserved 10F0*/
uint fec_ihash_table_high; /* upper 32-bits of individual hash *//* IAUR */
uint fec_ihash_table_low; /* lower 32-bits of individual hash *//* IALR */
uint fec_ghash_table_high; /* upper 32-bits of group hash *//* GAUR */
uint fec_ghash_table_low; /* lower 32-bits of group hash *//* GALR */
uint res10[7]; /* reserved 1128*/
uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
uint res11; /* reserved 1148*/
uint fec_r_bound; /* FIFO Receive Bound Register = end of *//* FRBR */
uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = *//* FRSR */
uint res12[11]; /* reserved 1154*/
uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*//* ERDSR */
uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*//* ETDSR */
uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
} fec_t;
#endif /* __IMMAP_5282__ */

525
include/asm-m68k/m5282.h
View File

@ -1,9 +1,6 @@
/*
* mcf5282.h -- Definitions for Motorola Coldfire 5282
*
* Based on mcf5282sim.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -34,27 +31,515 @@
#define INT_RAM_SIZE 65536
/* General Purpose I/O Module GPIO */
/*
* Define the 5282 SIM register set addresses.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000))
#define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001))
#define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002))
#define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003))
#define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004))
#define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005))
#define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006))
#define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007))
#define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008))
#define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009))
#define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A))
#define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B))
#define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C))
#define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D))
#define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E))
#define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F))
#define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010))
#define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011))
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
#define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014))
#define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015))
#define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016))
#define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017))
#define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018))
#define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019))
#define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A))
#define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B))
#define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C))
#define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D))
#define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E))
#define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F))
#define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020))
#define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021))
#define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022))
#define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023))
#define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024))
#define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025))
#define MCF5282_GPIO_PUAPAR 0x10005C
#define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028))
#define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029))
#define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A))
#define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028))
#define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029))
#define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A))
#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
#define MCFGPIO_PORT6 (0x40)
#define MCFGPIO_PORT5 (0x20)
#define MCFGPIO_PORT4 (0x10)
#define MCFGPIO_PORT3 (0x08)
#define MCFGPIO_PORT2 (0x04)
#define MCFGPIO_PORT1 (0x02)
#define MCFGPIO_PORT0 (0x01)
#define MCFGPIO_PORT(x) (0x01<<x)
#define MCFGPIO_DDR7 (0x80)
#define MCFGPIO_DDR6 (0x40)
#define MCFGPIO_DDR5 (0x20)
#define MCFGPIO_DDR4 (0x10)
#define MCFGPIO_DDR3 (0x08)
#define MCFGPIO_DDR2 (0x04)
#define MCFGPIO_DDR1 (0x02)
#define MCFGPIO_DDR0 (0x01)
#define MCFGPIO_DDR(x) (0x01<<x)
#define MCFGPIO_Px7 (0x80)
#define MCFGPIO_Px6 (0x40)
#define MCFGPIO_Px5 (0x20)
#define MCFGPIO_Px4 (0x10)
#define MCFGPIO_Px3 (0x08)
#define MCFGPIO_Px2 (0x04)
#define MCFGPIO_Px1 (0x02)
#define MCFGPIO_Px0 (0x01)
#define MCFGPIO_Px(x) (0x01<<x)
#define MCFGPIO_PBCDPAR_PBPA (0x80)
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
#define MCFGPIO_PEPAR_PEPA7 (0x4000)
#define MCFGPIO_PEPAR_PEPA6 (0x1000)
#define MCFGPIO_PEPAR_PEPA5 (0x0400)
#define MCFGPIO_PEPAR_PEPA4 (0x0100)
#define MCFGPIO_PEPAR_PEPA3 (0x0040)
#define MCFGPIO_PEPAR_PEPA2 (0x0010)
#define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3))
#define MCFGPIO_PFPAR_PFPA7 (0x80)
#define MCFGPIO_PFPAR_PFPA6 (0x40)
#define MCFGPIO_PFPAR_PFPA5 (0x20)
#define MCFGPIO_PJPAR_PJPA7 (0x80)
#define MCFGPIO_PJPAR_PJPA6 (0x40)
#define MCFGPIO_PJPAR_PJPA5 (0x20)
#define MCFGPIO_PJPAR_PJPA4 (0x10)
#define MCFGPIO_PJPAR_PJPA3 (0x08)
#define MCFGPIO_PJPAR_PJPA2 (0x04)
#define MCFGPIO_PJPAR_PJPA1 (0x02)
#define MCFGPIO_PJPAR_PJPA0 (0x01)
#define MCFGPIO_PJPAR_PJPA(x) (0x01<<x)
#define MCFGPIO_PSDPAR_PSDPA (0x80)
#define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10)
#define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8)
#define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3))
#define MCFGPIO_PEHLPAR_PEHPA (0x80)
#define MCFGPIO_PEHLPAR_PELPA (0x40)
#define MCFGPIO_PQSPAR_PQSPA6 (0x40)
#define MCFGPIO_PQSPAR_PQSPA5 (0x20)
#define MCFGPIO_PQSPAR_PQSPA4 (0x10)
#define MCFGPIO_PQSPAR_PQSPA3 (0x08)
#define MCFGPIO_PQSPAR_PQSPA2 (0x04)
#define MCFGPIO_PQSPAR_PQSPA1 (0x02)
#define MCFGPIO_PQSPAR_PQSPA0 (0x01)
#define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x)
#define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3))
#define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3))
#define MCFGPIO_PUAPAR_PUAPA3 (0x08)
#define MCFGPIO_PUAPAR_PUAPA2 (0x04)
#define MCFGPIO_PUAPAR_PUAPA1 (0x02)
#define MCFGPIO_PUAPAR_PUAPA0 (0x01)
/* System Conrol Module SCM */
#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
#define MCFSCM_CWSR (*(vu_char *) (CFG_MBAR+0x00000013))
#define MCFSCM_MPARK (*(vu_long *) (CFG_MBAR+0x0000001C))
#define MCFSCM_MPR (*(vu_char *) (CFG_MBAR+0x00000020))
#define MCFSCM_PACR0 (*(vu_char *) (CFG_MBAR+0x00000024))
#define MCFSCM_PACR1 (*(vu_char *) (CFG_MBAR+0x00000025))
#define MCFSCM_PACR2 (*(vu_char *) (CFG_MBAR+0x00000026))
#define MCFSCM_PACR3 (*(vu_char *) (CFG_MBAR+0x00000027))
#define MCFSCM_PACR4 (*(vu_char *) (CFG_MBAR+0x00000028))
#define MCFSCM_PACR5 (*(vu_char *) (CFG_MBAR+0x0000002A))
#define MCFSCM_PACR6 (*(vu_char *) (CFG_MBAR+0x0000002B))
#define MCFSCM_PACR7 (*(vu_char *) (CFG_MBAR+0x0000002C))
#define MCFSCM_PACR8 (*(vu_char *) (CFG_MBAR+0x0000002E))
#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCFSCM_RAMBAR_BDE (0x00000200)
/* Reset Controller Module RCM */
#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RCR_LVDF (0x10)
#define MCFRESET_RCR_LVDIE (0x08)
#define MCFRESET_RCR_LVDRE (0x04)
#define MCFRESET_RCR_LVDE (0x01)
#define MCFRESET_RSR_LVD (0x40)
#define MCFRESET_RSR_SOFT (0x20)
#define MCFRESET_RSR_WDR (0x10)
#define MCFRESET_RSR_POR (0x08)
#define MCFRESET_RSR_EXT (0x04)
#define MCFRESET_RSR_LOC (0x02)
#define MCFRESET_RSR_LOL (0x01)
#define MCFRESET_RSR_ALL (0x7F)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
#define MCFCCM_CCR (*(vu_short *)(CFG_MBAR+0x00110004))
#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
#define MCFCCM_CCR_SZEN (0x0040)
#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_BME (0x0008)
#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CIR_PIN_MASK (0xFF00)
#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_MBAR+0x0000004c))
#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_MBAR+0x00000050))
#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_MBAR+0x00000054))
#define MCFSDRAMC_DCR_NAM (0x2000)
#define MCFSDRAMC_DCR_COC (0x1000)
#define MCFSDRAMC_DCR_IS (0x0800)
#define MCFSDRAMC_DCR_RTIM_3 (0x0000)
#define MCFSDRAMC_DCR_RTIM_6 (0x0200)
#define MCFSDRAMC_DCR_RTIM_9 (0x0400)
#define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF)
#define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000)
#define MCFSDRAMC_DACR_RE (0x00008000)
#define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12)
#define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8)
#define MCFSDRAMC_DACR_PS_32 (0x00000000)
#define MCFSDRAMC_DACR_PS_16 (0x00000020)
#define MCFSDRAMC_DACR_PS_8 (0x00000010)
#define MCFSDRAMC_DACR_IP (0x00000008)
#define MCFSDRAMC_DACR_IMRS (0x00000040)
#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
#define MCFSDRAMC_DMR_WP (0x00000100)
#define MCFSDRAMC_DMR_CI (0x00000040)
#define MCFSDRAMC_DMR_AM (0x00000020)
#define MCFSDRAMC_DMR_SC (0x00000010)
#define MCFSDRAMC_DMR_SD (0x00000008)
#define MCFSDRAMC_DMR_UC (0x00000004)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
#define MCFCSM_CSMR0 (*(vu_long *) (CFG_MBAR+0x00000084))
#define MCFCSM_CSCR0 (*(vu_short *)(CFG_MBAR+0x0000008a))
#define MCFCSM_CSAR1 (*(vu_short *)(CFG_MBAR+0x0000008C))
#define MCFCSM_CSMR1 (*(vu_long *) (CFG_MBAR+0x00000090))
#define MCFCSM_CSCR1 (*(vu_short *)(CFG_MBAR+0x00000096))
#define MCFCSM_CSAR2 (*(vu_short *)(CFG_MBAR+0x00000098))
#define MCFCSM_CSMR2 (*(vu_long *) (CFG_MBAR+0x0000009C))
#define MCFCSM_CSCR2 (*(vu_short *)(CFG_MBAR+0x000000A2))
#define MCFCSM_CSAR3 (*(vu_short *)(CFG_MBAR+0x000000A4))
#define MCFCSM_CSMR3 (*(vu_long *) (CFG_MBAR+0x000000A8))
#define MCFCSM_CSCR3 (*(vu_short *)(CFG_MBAR+0x000000AE))
#define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000)
#define MCFCSM_CSMR_WP (1<<8)
#define MCFCSM_CSMR_V (0x01)
#define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10)
#define MCFCSM_CSCR_AA (0x0100)
#define MCFCSM_CSCR_PS_32 (0x0000)
#define MCFCSM_CSCR_PS_8 (0x0040)
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
*
* General Purpose Timer (GPT) Module
*
*********************************************************************/
#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1A0001))
#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1A0002))
#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1A0003))
#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_MBAR+0x1A0004))
#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1A0006))
#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_MBAR+0x1A0008))
#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1A0009))
#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1A000B))
#define MCFGPTA_GPTIE (*(vu_char *)(CFG_MBAR+0x1A000C))
#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1A000D))
#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1A000E))
#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1A000F))
#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_MBAR+0x1A0010))
#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_MBAR+0x1A0012))
#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_MBAR+0x1A0014))
#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_MBAR+0x1A0016))
#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1A0018))
#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1A0019))
#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1A001A))
#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1B0003))
#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_MBAR+0x1B0004))
#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1B0006))
#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_MBAR+0x1B0008))
#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1B0009))
#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1B000B))
#define MCFGPTB_GPTIE (*(vu_char *)(CFG_MBAR+0x1B000C))
#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1B000D))
#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1B000E))
#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1B000F))
#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_MBAR+0x1B0010))
#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_MBAR+0x1B0012))
#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_MBAR+0x1B0014))
#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_MBAR+0x1B0016))
#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1B0018))
#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1B0019))
#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1B001A))
#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_MBAR+0x1B001D))
#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_MBAR+0x1B001E))
/* Bit level definitions and macros */
#define MCFGPT_GPTIOS_IOS3 (0x08)
#define MCFGPT_GPTIOS_IOS2 (0x04)
#define MCFGPT_GPTIOS_IOS1 (0x02)
#define MCFGPT_GPTIOS_IOS0 (0x01)
#define MCFGPT_GPTCFORC_FOC3 (0x08)
#define MCFGPT_GPTCFORC_FOC2 (0x04)
#define MCFGPT_GPTCFORC_FOC1 (0x02)
#define MCFGPT_GPTCFORC_FOC0 (0x01)
#define MCFGPT_GPTOC3M_OC3M3 (0x08)
#define MCFGPT_GPTOC3M_OC3M2 (0x04)
#define MCFGPT_GPTOC3M_OC3M1 (0x02)
#define MCFGPT_GPTOC3M_OC3M0 (0x01)
#define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04))
#define MCFGPT_GPTSCR1_GPTEN (0x80)
#define MCFGPT_GPTSCR1_TFFCA (0x10)
#define MCFGPT_GPTTOV3 (0x08)
#define MCFGPT_GPTTOV2 (0x04)
#define MCFGPT_GPTTOV1 (0x02)
#define MCFGPT_GPTTOV0 (0x01)
#define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6)
#define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4)
#define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2)
#define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03))
#define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6)
#define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4)
#define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2)
#define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03))
#define MCFGPT_GPTIE_C3I (0x08)
#define MCFGPT_GPTIE_C2I (0x04)
#define MCFGPT_GPTIE_C1I (0x02)
#define MCFGPT_GPTIE_C0I (0x01)
#define MCFGPT_GPTSCR2_TOI (0x80)
#define MCFGPT_GPTSCR2_PUPT (0x20)
#define MCFGPT_GPTSCR2_RDPT (0x10)
#define MCFGPT_GPTSCR2_TCRE (0x08)
#define MCFGPT_GPTSCR2_PR(x) (((x)&0x07))
#define MCFGPT_GPTFLG1_C3F (0x08)
#define MCFGPT_GPTFLG1_C2F (0x04)
#define MCFGPT_GPTFLG1_C1F (0x02)
#define MCFGPT_GPTFLG1_C0F (0x01)
#define MCFGPT_GPTFLG2_TOF (0x80)
#define MCFGPT_GPTFLG2_C3F (0x08)
#define MCFGPT_GPTFLG2_C2F (0x04)
#define MCFGPT_GPTFLG2_C1F (0x02)
#define MCFGPT_GPTFLG2_C0F (0x01)
#define MCFGPT_GPTPACTL_PAE (0x40)
#define MCFGPT_GPTPACTL_PAMOD (0x20)
#define MCFGPT_GPTPACTL_PEDGE (0x10)
#define MCFGPT_GPTPACTL_CLK_PACLK (0x04)
#define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08)
#define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C)
#define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2)
#define MCFGPT_GPTPACTL_PAOVI (0x02)
#define MCFGPT_GPTPACTL_PAI (0x01)
#define MCFGPT_GPTPAFLG_PAOVF (0x02)
#define MCFGPT_GPTPAFLG_PAIF (0x01)
#define MCFGPT_GPTPORT_PORTT3 (0x08)
#define MCFGPT_GPTPORT_PORTT2 (0x04)
#define MCFGPT_GPTPORT_PORTT1 (0x02)
#define MCFGPT_GPTPORT_PORTT0 (0x01)
#define MCFGPT_GPTDDR_DDRT3 (0x08)
#define MCFGPT_GPTDDR_DDRT2 (0x04)
#define MCFGPT_GPTDDR_DDRT1 (0x02)
#define MCFGPT_GPTDDR_DDRT0 (0x01)
/* Coldfire Flash Module CFM */
#define MCFCFM_MCR (*(vu_short *)(CFG_MBAR+0x1D0000))
#define MCFCFM_MCR_LOCK (0x0400)
#define MCFCFM_MCR_PVIE (0x0200)
#define MCFCFM_MCR_AEIE (0x0100)
#define MCFCFM_MCR_CBEIE (0x0080)
#define MCFCFM_MCR_CCIE (0x0040)
#define MCFCFM_MCR_KEYACC (0x0020)
#define MCFCFM_CLKD (*(vu_char *)(CFG_MBAR+0x1D0002))
#define MCFCFM_SEC (*(vu_long*) (CFG_MBAR+0x1D0008))
#define MCFCFM_SEC_KEYEN (0x80000000)
#define MCFCFM_SEC_SECSTAT (0x40000000)
#define MCFCFM_PROT (*(vu_long*) (CFG_MBAR+0x1D0010))
#define MCFCFM_SACC (*(vu_long*) (CFG_MBAR+0x1D0014))
#define MCFCFM_DACC (*(vu_long*) (CFG_MBAR+0x1D0018))
#define MCFCFM_USTAT (*(vu_char*) (CFG_MBAR+0x1D0020))
#define MCFCFM_USTAT_CBEIF 0x80
#define MCFCFM_USTAT_CCIF 0x40
#define MCFCFM_USTAT_PVIOL 0x20
#define MCFCFM_USTAT_ACCERR 0x10
#define MCFCFM_USTAT_BLANK 0x04
#define MCFCFM_CMD (*(vu_char*) (CFG_MBAR+0x1D0024))
#define MCFCFM_CMD_ERSVER 0x05
#define MCFCFM_CMD_PGERSVER 0x06
#define MCFCFM_CMD_PGM 0x20
#define MCFCFM_CMD_PGERS 0x40
#define MCFCFM_CMD_MASERS 0x41
/****************************************************************************/
#endif /* m5282_h */

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include/configs/EB+MCF-EV123.h Normal file
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/*
* Configuation settings for the BuS EB+MCF-EV123 boards.
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CONFIG_EB_MCF_EV123_H_
#define _CONFIG_EB_MCF_EV123_H_
#define CONFIG_EB_MCF_EV123
#undef DEBUG
#undef CFG_HALT_BEFOR_RAM_JUMP
#undef ET_DEBUG
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5282 /* define processor type */
#define CONFIG_MISC_INIT_R
#define FEC_ENET
#define CONFIG_ETHADDR 00:CF:52:82:EB:01
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
#define CONFIG_BOOTCOMMAND "printenv"
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_ADDR 0xF003C000 /* End of 256K */
#define CFG_ENV_SECT_SIZE 0x4000
#define CFG_ENV_IS_IN_FLASH 1
/*
#define CFG_ENV_IS_EMBEDDED 1
#define CFG_ENV_ADDR_REDUND 0xF0018000
#define CFG_ENV_SECT_SIZE_REDUND 0x4000
*/
#else
#define CFG_ENV_ADDR 0xFFE04000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
//#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "\nEV123 U-Boot> "
#define CFG_LONGHELP /* undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
#define CFG_MEMTEST_START 0x100000
#define CFG_MEMTEST_END 0x400000
/*#define CFG_DRAM_TEST 1 */
#undef CFG_DRAM_TEST
/* Clock and PLL Configuration */
#define CFG_HZ 10000000
#define CFG_CLK 58982400 /* 9,8304MHz * 6 */
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */
#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_MBAR 0x40000000
#define CFG_DISCOVER_PHY
/* #define CFG_ENET_BD_BASE 0x380000 */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE1 0x00000000
#define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */
/*
#define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
#define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
#define CFG_SDRAM_BASE CFG_SDRAM_BASE1
#define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_INT_FLASH_BASE 0xF0000000
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
#if (TEXT_BASE != CFG_INT_FLASH_BASE)
#define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
#else
#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
#endif
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_SECT 35
#define CFG_MAX_FLASH_BANKS 2
#define CFG_FLASH_ERASE_TOUT 10000000
#define CFG_FLASH_PROTECTION
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CFG_CS0_BASE CFG_FLASH_BASE
#define CFG_CS0_SIZE 2*1024*1024
#define CFG_CS0_WIDTH 16
#define CFG_CS0_RO 0
#define CFG_CS0_WS 6
#define CFG_CS3_BASE 0xE0000000
#define CFG_CS3_SIZE 1*1024*1024
#define CFG_CS3_WIDTH 16
#define CFG_CS3_RO 0
#define CFG_CS3_WS 6
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
#define CFG_PADDR 0x0000000
#define CFG_PADAT 0x0000000
#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
#define CFG_PBDDR 0x0000000
#define CFG_PBDAT 0x0000000
#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
#define CFG_PCDDR 0x0000000
#define CFG_PCDAT 0x0000000
#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
#define CFG_PCDDR 0x0000000
#define CFG_PCDAT 0x0000000
#define CFG_PEHLPAR 0xC0
#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_DDRUA 0x05
#define CFG_PJPAR 0xFF;
/*-----------------------------------------------------------------------
* CCM configuration
*/
#define CFG_CCM_SIZ 0
/*---------------------------------------------------------------------*/
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/