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Convert CONFIG_SYS_FSL_PCIE_COMPAT to Kconfig
This converts the following to Kconfig: CONFIG_SYS_FSL_PCIE_COMPAT To do this, introduce a choice and option for each of the strings used and set CONFIG_SYS_FSL_PCIE_COMPAT based on that. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
1de46d91dd
commit
4143a23794
5
README
5
README
@ -300,11 +300,6 @@ The following options need to be configured:
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system clock. On most PQ3 devices this is 8, on newer QorIQ
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devices it can be 16 or 32. The ratio varies from SoC to Soc.
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CONFIG_SYS_FSL_PCIE_COMPAT
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Defines the string to utilize when trying to match PCIe device
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tree nodes for the given platform.
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CONFIG_SYS_FSL_ERRATUM_A004510
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Enables a workaround for erratum A004510. If set,
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@ -259,6 +259,7 @@ config ARCH_B4420
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS2
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC64
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@ -289,6 +290,7 @@ config ARCH_B4860
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS2
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC64
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@ -326,6 +328,7 @@ config ARCH_BSC9132
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select FSL_PCIE_RESET
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC_E500_USE_DEBUG_TLB
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@ -434,6 +437,7 @@ config ARCH_P1010
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select FSL_PCIE_RESET
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC_E500_USE_DEBUG_TLB
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@ -515,6 +519,7 @@ config ARCH_P1023
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select FSL_PCIE_RESET
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select FSL_ELBC
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@ -602,6 +607,7 @@ config ARCH_P2041
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS1
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select FSL_ELBC
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@ -631,6 +637,7 @@ config ARCH_P3041
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS1
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select FSL_ELBC
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@ -664,6 +671,7 @@ config ARCH_P4080
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select SYS_FSL_ERRATUM_I2C_A004447
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select SYS_FSL_ERRATUM_NMG_CPU_A011
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select SYS_FSL_ERRATUM_SRIO_A004034
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select SYS_FSL_PCIE_COMPAT_P4080_PCIE
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select SYS_P4080_ERRATUM_CPU22
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select SYS_P4080_ERRATUM_PCIE_A003
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select SYS_P4080_ERRATUM_SERDES8
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@ -700,6 +708,7 @@ config ARCH_P5040
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS1
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC64
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@ -730,6 +739,7 @@ config ARCH_T1024
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS2
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_5
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select FSL_IFC
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@ -757,6 +767,7 @@ config ARCH_T1040
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS2
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_5
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select FSL_IFC
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@ -783,6 +794,7 @@ config ARCH_T1042
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select SYS_FSL_HAS_DDR4
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS2
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_5
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select FSL_IFC
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@ -811,6 +823,7 @@ config ARCH_T2080
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS2
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC64
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@ -843,6 +856,7 @@ config ARCH_T4240
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_QORIQ_CHASSIS2
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select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_4
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select SYS_PPC64
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@ -1310,6 +1324,29 @@ config SYS_FSL_CPC
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config SYS_CACHE_STASHING
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bool "Enable cache stashing"
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config SYS_FSL_PCIE_COMPAT_P4080_PCIE
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bool
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config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
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bool
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config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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bool
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config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
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bool
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config SYS_FSL_PCIE_COMPAT
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string
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depends on FSL_CORENET
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default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
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default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
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default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
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default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
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help
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Defines the string to utilize when trying to match PCIe device tree
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nodes for the given platform.
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config SYS_MPC85XX_NO_RESETVEC
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bool "Discard resetvec section and move bootpg section up"
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depends on MPC85xx
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@ -27,7 +27,6 @@
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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@ -50,7 +49,6 @@
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#define CONFIG_SYS_QMAN_NUM_PORTALS 3
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#define CONFIG_SYS_BMAN_NUM_PORTALS 3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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/* P1024 is lower end variant of P1020 */
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#elif defined(CONFIG_ARCH_P1024)
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@ -76,7 +74,6 @@
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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@ -91,7 +88,6 @@
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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@ -108,7 +104,6 @@
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#define CONFIG_SYS_NUM_FM2_10GEC 1
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -124,7 +119,6 @@
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#define CONFIG_SYS_NUM_FM2_10GEC 1
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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@ -139,7 +133,6 @@
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#elif defined(CONFIG_ARCH_T4240)
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#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
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@ -166,7 +159,6 @@
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#define CONFIG_SYS_FM2_CLK 3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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@ -183,7 +175,6 @@
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#ifdef CONFIG_ARCH_B4860
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@ -217,7 +208,6 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
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#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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@ -240,7 +230,6 @@
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#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
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#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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@ -268,7 +257,6 @@
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
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#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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