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Correct SPL uses of SANDBOX_CLK_CCF

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This converts 12 usages of this option to the non-SPL form, since there is
no SPL_SANDBOX_CLK_CCF defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2023-02-05 15:40:43 -07:00 committed by Tom Rini
parent ef746bfd2c
commit 4051c400c5
4 changed files with 12 additions and 12 deletions
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4
drivers/clk/clk-divider.c
View File

@ -81,7 +81,7 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned int val;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
val = divider->io_divider_val;
#else
val = readl(divider->reg);
@ -210,7 +210,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
div->width = width;
div->flags = clk_divider_flags;
div->table = table;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
div->io_divider_val = *(u32 *)reg;
#endif

6
drivers/clk/clk-gate.c
View File

@ -62,7 +62,7 @@ static void clk_gate_endisable(struct clk *clk, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
reg = gate->io_gate_val;
#else
reg = readl(gate->reg);
@ -96,7 +96,7 @@ int clk_gate_is_enabled(struct clk *clk)
struct clk_gate *gate = to_clk_gate(clk);
u32 reg;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
reg = gate->io_gate_val;
#else
reg = readl(gate->reg);
@ -142,7 +142,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
gate->reg = reg;
gate->bit_idx = bit_idx;
gate->flags = clk_gate_flags;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
gate->io_gate_val = *(u32 *)reg;
#endif

8
drivers/clk/clk-mux.c
View File

@ -90,7 +90,7 @@ u8 clk_mux_get_parent(struct clk *clk)
struct clk_mux *mux = to_clk_mux(clk);
u32 val;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
val = mux->io_mux_val;
#else
val = readl(mux->reg);
@ -137,7 +137,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
reg = mux->mask << (mux->shift + 16);
} else {
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
reg = mux->io_mux_val;
#else
reg = readl(mux->reg);
@ -146,7 +146,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
}
val = val << mux->shift;
reg |= val;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
mux->io_mux_val = reg;
#else
writel(reg, mux->reg);
@ -194,7 +194,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
mux->mask = mask;
mux->flags = clk_mux_flags;
mux->table = table;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
mux->io_mux_val = *(u32 *)reg;
#endif

6
include/linux/clk-provider.h
View File

@ -65,7 +65,7 @@ struct clk_mux {
*/
const char * const *parent_names;
u8 num_parents;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
u32 io_mux_val;
#endif
@ -93,7 +93,7 @@ struct clk_gate {
void __iomem *reg;
u8 bit_idx;
u8 flags;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
u32 io_gate_val;
#endif
};
@ -121,7 +121,7 @@ struct clk_divider {
u8 width;
u8 flags;
const struct clk_div_table *table;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
u32 io_divider_val;
#endif
};