mirror of
https://github.com/u-boot/u-boot.git
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ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
SRICHARAN R
Tom Rini
parent
ee9447bfe3
commit
3fcdd4a5f8
@ -443,44 +443,45 @@ static void setup_non_essential_dplls(void)
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}
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#endif
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void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
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u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
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{
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u32 step;
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int ret = 0;
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u32 offset_code;
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/* See if we can first get the GPIO if needed */
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if (gpio >= 0)
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ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
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if (ret < 0) {
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printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
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gpio = -1;
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}
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volt_offset -= pmic->base_offset;
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/* Pull the GPIO low to select SET0 register, while we program SET1 */
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if (gpio >= 0)
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gpio_direction_output(gpio, 0);
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offset_code = (volt_offset + pmic->step - 1) / pmic->step;
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step = volt_mv - TPS62361_BASE_VOLT_MV;
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step /= 10;
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debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
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if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
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puts("Scaling voltage failed for vdd_mpu from TPS\n");
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/* Pull the GPIO high to select SET1 register */
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if (gpio >= 0)
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gpio_direction_output(gpio, 1);
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/*
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* Offset codes 1-6 all give the base voltage in Palmas
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* Offset code 0 switches OFF the SMPS
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*/
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return offset_code + pmic->start_code;
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}
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
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{
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u32 offset_code;
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u32 offset = volt_mv;
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int ret = 0;
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/* See if we can first get the GPIO if needed */
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if (pmic->gpio_en)
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ret = gpio_request(pmic->gpio, "PMIC_GPIO");
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if (ret < 0) {
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printf("%s: gpio %d request failed %d\n", __func__,
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pmic->gpio, ret);
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return;
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}
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/* Pull the GPIO low to select SET0 register, while we program SET1 */
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if (pmic->gpio_en)
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gpio_direction_output(pmic->gpio, 0);
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/* convert to uV for better accuracy in the calculations */
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offset *= 1000;
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offset_code = get_offset_code(offset);
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offset_code = get_offset_code(offset, pmic);
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debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
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offset_code);
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@ -488,6 +489,36 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
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vcore_reg, offset_code))
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printf("Scaling voltage failed for 0x%x\n", vcore_reg);
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if (pmic->gpio_en)
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gpio_direction_output(pmic->gpio, 1);
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}
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/*
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* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
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* We set the maximum voltages allowed here because Smart-Reflex is not
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* enabled in bootloader. Voltage initialization in the kernel will set
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* these to the nominal values after enabling Smart-Reflex
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*/
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void scale_vcores(struct vcores_data const *vcores)
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{
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
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do_scale_vcore(vcores->core.addr, vcores->core.value,
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vcores->core.pmic);
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do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
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vcores->mpu.pmic);
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do_scale_vcore(vcores->mm.addr, vcores->mm.value,
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vcores->mm.pmic);
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if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
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/* Configure LDO SRAM "magic" bits */
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writel(2, (*prcm)->prm_sldo_core_setup);
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writel(2, (*prcm)->prm_sldo_mpu_setup);
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writel(2, (*prcm)->prm_sldo_mm_setup);
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}
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}
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static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
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@ -656,7 +687,7 @@ void prcm_init(void)
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case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
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case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
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enable_basic_clocks();
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scale_vcores();
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scale_vcores(*omap_vcores);
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setup_dplls();
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#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
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setup_non_essential_dplls();
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@ -27,7 +27,6 @@ LIB = $(obj)lib$(SOC).o
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COBJS += sdram_elpida.o
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COBJS += hwinit.o
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COBJS += clocks.o
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COBJS += emif.o
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COBJS += prcm-regs.o
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COBJS += hw_data.o
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@ -1,123 +0,0 @@
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/*
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*
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* Clock initialization for OMAP4
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* Based on previous work by:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/gpio.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#include <asm/omap_gpio.h>
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#ifndef CONFIG_SPL_BUILD
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/*
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* printing to console doesn't work unless
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* this code is executed from SPL
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*/
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#define printf(fmt, args...)
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#define puts(s)
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#endif /* !CONFIG_SPL_BUILD */
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/*
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* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
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* We set the maximum voltages allowed here because Smart-Reflex is not
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* enabled in bootloader. Voltage initialization in the kernel will set
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* these to the nominal values after enabling Smart-Reflex
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*/
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void scale_vcores(void)
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{
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u32 volt, omap_rev;
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
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omap_rev = omap_revision();
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/*
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* Scale Voltage rails:
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* 1. VDD_CORE
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* 3. VDD_MPU
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* 3. VDD_IVA
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*/
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if (omap_rev < OMAP4460_ES1_0) {
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/*
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* OMAP4430:
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* VDD_CORE = TWL6030 VCORE3
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* VDD_MPU = TWL6030 VCORE1
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* VDD_IVA = TWL6030 VCORE2
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*/
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
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/*
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* note on VDD_MPU:
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* Setting a high voltage for Nitro mode as smart reflex is not
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* enabled. We use the maximum possible value in the AVS range
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* because the next higher voltage in the discrete range
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* (code >= 0b111010) is way too high.
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*/
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volt = 1325;
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
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} else {
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/*
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* OMAP4460:
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* VDD_CORE = TWL6030 VCORE1
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* VDD_MPU = TPS62361
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* VDD_IVA = TWL6030 VCORE2
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*/
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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/* TPS62361 */
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volt = 1203;
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do_scale_tps62361(TPS62361_VSEL0_GPIO,
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TPS62361_REG_ADDR_SET1, volt);
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/* VCORE 2 - supplies vdd_iva */
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
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}
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}
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u32 get_offset_code(u32 offset)
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{
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u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
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if (omap_revision() == OMAP4430_ES1_0)
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offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
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else
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offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
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offset_code = (offset + step - 1) / step;
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/* The code starts at 1 not 0 */
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return ++offset_code;
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}
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@ -30,12 +30,15 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_common.h>
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#include <asm/arch/clocks.h>
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#include <asm/omap_gpio.h>
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#include <asm/io.h>
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struct prcm_regs const **prcm =
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(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
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struct dplls const **dplls_data =
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(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
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struct vcores_data const **omap_vcores =
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(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
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/*
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* The M & N values in the following tables are created using the
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@ -194,6 +197,70 @@ struct dplls omap4460_dplls = {
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.usb = usb_dpll_params_1920mhz
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};
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struct pmic_data twl6030_4430es1 = {
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
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.step = 12660, /* 10 mV represented in uV */
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/* The code starts at 1 not 0 */
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.start_code = 1,
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};
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struct pmic_data twl6030 = {
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
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.step = 12660, /* 10 mV represented in uV */
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/* The code starts at 1 not 0 */
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.start_code = 1,
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};
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struct pmic_data tps62361 = {
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.base_offset = TPS62361_BASE_VOLT_MV,
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.step = 10000, /* 10 mV represented in uV */
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.start_code = 0,
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.gpio = TPS62361_VSEL0_GPIO,
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.gpio_en = 1
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};
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struct vcores_data omap4430_volts_es1 = {
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.mpu.value = 1325,
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.mpu.addr = SMPS_REG_ADDR_VCORE1,
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.mpu.pmic = &twl6030_4430es1,
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.core.value = 1200,
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.core.addr = SMPS_REG_ADDR_VCORE3,
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.core.pmic = &twl6030_4430es1,
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.mm.value = 1200,
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.mm.addr = SMPS_REG_ADDR_VCORE2,
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.mm.pmic = &twl6030_4430es1,
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};
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struct vcores_data omap4430_volts = {
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.mpu.value = 1325,
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.mpu.addr = SMPS_REG_ADDR_VCORE1,
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.mpu.pmic = &twl6030,
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.core.value = 1200,
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.core.addr = SMPS_REG_ADDR_VCORE3,
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.core.pmic = &twl6030,
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.mm.value = 1200,
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.mm.addr = SMPS_REG_ADDR_VCORE2,
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.mm.pmic = &twl6030,
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};
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struct vcores_data omap4460_volts = {
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.mpu.value = 1203,
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.mpu.addr = TPS62361_REG_ADDR_SET1,
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.mpu.pmic = &tps62361,
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.core.value = 1200,
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.core.addr = SMPS_REG_ADDR_VCORE1,
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.core.pmic = &tps62361,
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.mm.value = 1200,
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.mm.addr = SMPS_REG_ADDR_VCORE2,
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.mm.pmic = &tps62361,
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};
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/*
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* Enable essential clock domains, modules and
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* do some additional special settings needed
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@ -382,6 +449,7 @@ void hw_data_init(void)
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case OMAP4430_ES1_0:
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*dplls_data = &omap4430_dplls_es1;
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*omap_vcores = &omap4430_volts_es1;
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break;
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case OMAP4430_ES2_0:
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@ -389,11 +457,13 @@ void hw_data_init(void)
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case OMAP4430_ES2_2:
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case OMAP4430_ES2_3:
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*dplls_data = &omap4430_dplls;
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*omap_vcores = &omap4430_volts;
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break;
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case OMAP4460_ES1_0:
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case OMAP4460_ES1_1:
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*dplls_data = &omap4460_dplls;
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*omap_vcores = &omap4460_volts;
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break;
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default:
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@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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COBJS += hwinit.o
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COBJS += clocks.o
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COBJS += emif.o
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COBJS += sdram.o
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COBJS += prcm-regs.o
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@ -1,98 +0,0 @@
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/*
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*
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* Clock initialization for OMAP5
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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* Sricharan R <r.sricharan@ti.com>
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*
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* Based on previous work by:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
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* Rajendra Nayak <rnayak@ti.com>
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*
|
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* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#include <asm/omap_gpio.h>
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#include <asm/emif.h>
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#ifndef CONFIG_SPL_BUILD
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/*
|
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* printing to console doesn't work unless
|
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* this code is executed from SPL
|
||||
*/
|
||||
#define printf(fmt, args...)
|
||||
#define puts(s)
|
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#endif
|
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|
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/*
|
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* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
|
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* We set the maximum voltages allowed here because Smart-Reflex is not
|
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* enabled in bootloader. Voltage initialization in the kernel will set
|
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* these to the nominal values after enabling Smart-Reflex
|
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*/
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void scale_vcores(void)
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{
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u32 volt_core, volt_mpu, volt_mm;
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
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/* Palmas settings */
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if (omap_revision() != OMAP5432_ES1_0) {
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volt_core = VDD_CORE;
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volt_mpu = VDD_MPU;
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volt_mm = VDD_MM;
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} else {
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volt_core = VDD_CORE_5432;
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volt_mpu = VDD_MPU_5432;
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volt_mm = VDD_MM_5432;
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}
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do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
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do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
|
||||
do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
|
||||
|
||||
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
|
||||
/* Configure LDO SRAM "magic" bits */
|
||||
writel(2, (*prcm)->prm_sldo_core_setup);
|
||||
writel(2, (*prcm)->prm_sldo_mpu_setup);
|
||||
writel(2, (*prcm)->prm_sldo_mm_setup);
|
||||
}
|
||||
}
|
||||
|
||||
u32 get_offset_code(u32 volt_offset)
|
||||
{
|
||||
u32 offset_code, step = 10000; /* 10 mV represented in uV */
|
||||
|
||||
volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
|
||||
|
||||
offset_code = (volt_offset + step - 1) / step;
|
||||
|
||||
/*
|
||||
* Offset codes 1-6 all give the base voltage in Palmas
|
||||
* Offset code 0 switches OFF the SMPS
|
||||
*/
|
||||
return offset_code + 6;
|
||||
}
|
||||
@ -30,12 +30,15 @@
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/omap_common.h>
|
||||
#include <asm/arch/clocks.h>
|
||||
#include <asm/omap_gpio.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
struct prcm_regs const **prcm =
|
||||
(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
|
||||
struct dplls const **dplls_data =
|
||||
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
|
||||
struct vcores_data const **omap_vcores =
|
||||
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
|
||||
|
||||
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
|
||||
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
|
||||
@ -179,6 +182,44 @@ struct dplls omap5_dplls_es1 = {
|
||||
.usb = usb_dpll_params_1920mhz
|
||||
};
|
||||
|
||||
struct pmic_data palmas = {
|
||||
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
|
||||
.step = 10000, /* 10 mV represented in uV */
|
||||
/*
|
||||
* Offset codes 1-6 all give the base voltage in Palmas
|
||||
* Offset code 0 switches OFF the SMPS
|
||||
*/
|
||||
.start_code = 6,
|
||||
};
|
||||
|
||||
struct vcores_data omap5430_volts = {
|
||||
.mpu.value = VDD_MPU,
|
||||
.mpu.addr = SMPS_REG_ADDR_12_MPU,
|
||||
.mpu.pmic = &palmas,
|
||||
|
||||
.core.value = VDD_CORE,
|
||||
.core.addr = SMPS_REG_ADDR_8_CORE,
|
||||
.core.pmic = &palmas,
|
||||
|
||||
.mm.value = VDD_MM,
|
||||
.mm.addr = SMPS_REG_ADDR_45_IVA,
|
||||
.mm.pmic = &palmas,
|
||||
};
|
||||
|
||||
struct vcores_data omap5432_volts = {
|
||||
.mpu.value = VDD_MPU_5432,
|
||||
.mpu.addr = SMPS_REG_ADDR_12_MPU,
|
||||
.mpu.pmic = &palmas,
|
||||
|
||||
.core.value = VDD_CORE_5432,
|
||||
.core.addr = SMPS_REG_ADDR_8_CORE,
|
||||
.core.pmic = &palmas,
|
||||
|
||||
.mm.value = VDD_MM_5432,
|
||||
.mm.addr = SMPS_REG_ADDR_45_IVA,
|
||||
.mm.pmic = &palmas,
|
||||
};
|
||||
|
||||
/*
|
||||
* Enable essential clock domains, modules and
|
||||
* do some additional special settings needed
|
||||
@ -380,11 +421,13 @@ void hw_data_init(void)
|
||||
case OMAP5430_ES1_0:
|
||||
*prcm = &omap5_es1_prcm;
|
||||
*dplls_data = &omap5_dplls_es1;
|
||||
*omap_vcores = &omap5430_volts;
|
||||
break;
|
||||
|
||||
case OMAP5432_ES1_0:
|
||||
*prcm = &omap5_es1_prcm;
|
||||
*dplls_data = &omap5_dplls_es1;
|
||||
*omap_vcores = &omap5432_volts;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
@ -242,11 +242,6 @@
|
||||
#define DPLL_NO_LOCK 0
|
||||
#define DPLL_LOCK 1
|
||||
|
||||
void scale_vcores(void);
|
||||
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
|
||||
u32 get_offset_code(u32 offset);
|
||||
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
|
||||
|
||||
struct omap4_scrm_regs {
|
||||
u32 revision; /* 0x0000 */
|
||||
u32 pad00[63];
|
||||
|
||||
@ -180,7 +180,8 @@ struct control_lpddr2io_regs {
|
||||
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
|
||||
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
|
||||
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
|
||||
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
|
||||
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
|
||||
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20)
|
||||
|
||||
/* ROM code defines */
|
||||
/* Boot device */
|
||||
|
||||
@ -234,8 +234,4 @@
|
||||
#define DPLL_NO_LOCK 0
|
||||
#define DPLL_LOCK 1
|
||||
|
||||
void scale_vcores(void);
|
||||
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
|
||||
u32 get_offset_code(u32 offset);
|
||||
void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
|
||||
#endif /* _CLOCKS_OMAP5_H_ */
|
||||
|
||||
@ -273,7 +273,8 @@ struct omap_sys_ctrl_regs {
|
||||
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
|
||||
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
|
||||
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
|
||||
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
|
||||
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
|
||||
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20)
|
||||
|
||||
/* Silicon revisions */
|
||||
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
|
||||
|
||||
@ -364,10 +364,31 @@ struct dplls {
|
||||
const struct dpll_params *usb;
|
||||
};
|
||||
|
||||
struct pmic_data {
|
||||
u32 base_offset;
|
||||
u32 step;
|
||||
u32 start_code;
|
||||
unsigned gpio;
|
||||
int gpio_en;
|
||||
};
|
||||
|
||||
struct volts {
|
||||
u32 value;
|
||||
u32 addr;
|
||||
struct pmic_data *pmic;
|
||||
};
|
||||
|
||||
struct vcores_data {
|
||||
struct volts mpu;
|
||||
struct volts core;
|
||||
struct volts mm;
|
||||
};
|
||||
|
||||
extern struct prcm_regs const **prcm;
|
||||
extern struct prcm_regs const omap5_es1_prcm;
|
||||
extern struct prcm_regs const omap4_prcm;
|
||||
extern struct dplls const **dplls_data;
|
||||
extern struct vcores_data const **omap_vcores;
|
||||
extern const u32 sys_clk_array[8];
|
||||
|
||||
void hw_data_init(void);
|
||||
@ -391,6 +412,9 @@ u32 get_sys_clk_index(void);
|
||||
void enable_basic_clocks(void);
|
||||
void enable_basic_uboot_clocks(void);
|
||||
void enable_non_essential_clocks(void);
|
||||
void scale_vcores(struct vcores_data const *);
|
||||
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
|
||||
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
|
||||
|
||||
/* Max value for DPLL multiplier M */
|
||||
#define OMAP_DPLL_MAX_N 127
|
||||
|
||||
@ -265,5 +265,6 @@
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user