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driver/ddr/altera: Add the sdram calibration portion
This patch adds the DDR calibration portion of the Altera SDRAM driver. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Dinh Nguyen
Marek Vasut
parent
9bbd2132e3
commit
3da428595e
11
drivers/ddr/altera/Makefile
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11
drivers/ddr/altera/Makefile
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@ -0,0 +1,11 @@
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
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# Copyright (C) 2014 Altera Corporation <www.altera.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o
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4051
drivers/ddr/altera/sequencer.c
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4051
drivers/ddr/altera/sequencer.c
Normal file
File diff suppressed because it is too large
Load Diff
322
drivers/ddr/altera/sequencer.h
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322
drivers/ddr/altera/sequencer.h
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@ -0,0 +1,322 @@
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/*
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* Copyright Altera Corporation (C) 2012-2015
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _SEQUENCER_H_
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#define _SEQUENCER_H_
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#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
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/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
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#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
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/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
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#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \
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/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
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#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
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#define RW_MGR_RUN_SINGLE_GROUP (BASE_RW_MGR)
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#define RW_MGR_RUN_ALL_GROUPS (BASE_RW_MGR + 0x0400)
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#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
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#define RW_MGR_MEM_NUMBER_OF_RANKS 1
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#define NUM_SHADOW_REGS 1
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#define RW_MGR_RESET_READ_DATAPATH (BASE_RW_MGR + 0x1000)
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#define RW_MGR_SET_CS_AND_ODT_MASK (BASE_RW_MGR + 0x1400)
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#define RW_MGR_RANK_NONE 0xFF
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#define RW_MGR_RANK_ALL 0x00
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#define RW_MGR_ODT_MODE_OFF 0
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#define RW_MGR_ODT_MODE_READ_WRITE 1
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#define NUM_CALIB_REPEAT 1
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#define NUM_READ_TESTS 7
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#define NUM_READ_PB_TESTS 7
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#define NUM_WRITE_TESTS 15
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#define NUM_WRITE_PB_TESTS 31
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#define PASS_ALL_BITS 1
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#define PASS_ONE_BIT 0
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/* calibration stages */
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#define CAL_STAGE_NIL 0
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#define CAL_STAGE_VFIFO 1
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#define CAL_STAGE_WLEVEL 2
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#define CAL_STAGE_LFIFO 3
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#define CAL_STAGE_WRITES 4
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#define CAL_STAGE_FULLTEST 5
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#define CAL_STAGE_REFRESH 6
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#define CAL_STAGE_CAL_SKIPPED 7
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#define CAL_STAGE_CAL_ABORTED 8
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#define CAL_STAGE_VFIFO_AFTER_WRITES 9
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/* calibration substages */
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#define CAL_SUBSTAGE_NIL 0
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#define CAL_SUBSTAGE_GUARANTEED_READ 1
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#define CAL_SUBSTAGE_DQS_EN_PHASE 2
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#define CAL_SUBSTAGE_VFIFO_CENTER 3
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#define CAL_SUBSTAGE_WORKING_DELAY 1
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#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
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#define CAL_SUBSTAGE_WLEVEL_COPY 3
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#define CAL_SUBSTAGE_WRITES_CENTER 1
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#define CAL_SUBSTAGE_READ_LATENCY 1
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#define CAL_SUBSTAGE_REFRESH 1
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#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
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#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
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RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
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RW_MGR_MEM_IF_READ_DQS_WIDTH)
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#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
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#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
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/* length of VFIFO, from SW_MACROS */
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#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
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/* MarkW: how should these base addresses be done for A-V? */
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#define BASE_PTR_MGR 0x00040000
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#define BASE_SCC_MGR 0x00058000
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#define BASE_REG_FILE 0x00070000
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#define BASE_TIMER 0x00078000
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#define BASE_PHY_MGR 0x00088000
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#define BASE_RW_MGR 0x00090000
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#define BASE_DATA_MGR 0x00098000
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#define BASE_MMR 0x000C0000
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#define BASE_TRK_MGR 0x000D0000
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#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
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#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
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#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
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#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300)
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#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
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#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
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#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
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#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
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/* HHP-HPS-specific versions of some commands */
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#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600)
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#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800)
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#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
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#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
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#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00)
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#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
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#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
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#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
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#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
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#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
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#define PHY_MGR_CAL_RESET (0)
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#define PHY_MGR_CAL_SUCCESS (1)
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#define PHY_MGR_CAL_FAIL (2)
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#define CALIB_SKIP_DELAY_LOOPS (1 << 0)
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#define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
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#define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
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#define CALIB_SKIP_VFIFO (1 << 3)
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#define CALIB_SKIP_LFIFO (1 << 4)
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#define CALIB_SKIP_WLEVEL (1 << 5)
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#define CALIB_SKIP_WRITES (1 << 6)
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#define CALIB_SKIP_FULL_TEST (1 << 7)
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#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
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CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
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CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
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#define CALIB_IN_RTL_SIM (1 << 8)
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/* Scan chain manager command addresses */
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#define READ_SCC_OCT_OUT2_DELAY 0
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#define READ_SCC_DQ_OUT2_DELAY 0
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#define READ_SCC_DQS_IO_OUT2_DELAY 0
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#define READ_SCC_DM_IO_OUT2_DELAY 0
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/* HHP-HPS-specific values */
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#define SCC_MGR_HHP_EXTRAS_OFFSET 0
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#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
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/* PHY Debug mode flag constants */
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#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
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#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
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#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
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#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
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#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
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#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
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/* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
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* otherwise, revert to defaults
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* Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
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* 200.75us @ 266MHz
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*/
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#ifdef TINIT_CNTR0_VAL
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#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
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#else
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#define SEQ_TINIT_CNTR0_VAL 0
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#endif
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#ifdef TINIT_CNTR1_VAL
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#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
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#else
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#define SEQ_TINIT_CNTR1_VAL 202
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#endif
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#ifdef TINIT_CNTR2_VAL
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#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
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#else
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#define SEQ_TINIT_CNTR2_VAL 131
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#endif
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/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
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* 500.86us @ 266MHz
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*/
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#ifdef TRESET_CNTR0_VAL
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#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
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#else
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#define SEQ_TRESET_CNTR0_VAL 2
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#endif
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#ifdef TRESET_CNTR1_VAL
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#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
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#else
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#define SEQ_TRESET_CNTR1_VAL 252
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#endif
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#ifdef TRESET_CNTR2_VAL
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#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
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#else
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#define SEQ_TRESET_CNTR2_VAL 131
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#endif
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#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
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#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
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struct socfpga_sdr_rw_load_manager {
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u32 load_cntr0;
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u32 load_cntr1;
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u32 load_cntr2;
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u32 load_cntr3;
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};
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struct socfpga_sdr_rw_load_jump_manager {
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u32 load_jump_add0;
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u32 load_jump_add1;
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u32 load_jump_add2;
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u32 load_jump_add3;
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};
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struct socfpga_sdr_reg_file {
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u32 signature;
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u32 debug_data_addr;
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u32 cur_stage;
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u32 fom;
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u32 failing_stage;
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u32 debug1;
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u32 debug2;
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u32 dtaps_per_ptap;
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u32 trk_sample_count;
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u32 trk_longidle;
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u32 delays;
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u32 trk_rw_mgr_addr;
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u32 trk_read_dqs_width;
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u32 trk_rfsh;
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};
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/* parameter variable holder */
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struct param_type {
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uint32_t dm_correct_mask;
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uint32_t read_correct_mask;
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uint32_t read_correct_mask_vg;
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uint32_t write_correct_mask;
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uint32_t write_correct_mask_vg;
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/* set a particular entry to 1 if we need to skip a particular rank */
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uint32_t skip_ranks[MAX_RANKS];
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/* set a particular entry to 1 if we need to skip a particular group */
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uint32_t skip_groups;
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/* set a particular entry to 1 if the shadow register
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(which represents a set of ranks) needs to be skipped */
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uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
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};
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/* global variable holder */
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struct gbl_type {
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uint32_t phy_debug_mode_flags;
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/* current read latency */
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uint32_t curr_read_lat;
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/* current write latency */
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uint32_t curr_write_lat;
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/* error code */
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uint32_t error_substage;
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uint32_t error_stage;
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uint32_t error_group;
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/* figure-of-merit in, figure-of-merit out */
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uint32_t fom_in;
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uint32_t fom_out;
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/*USER Number of RW Mgr NOP cycles between
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write command and write data */
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uint32_t rw_wl_nop_cycles;
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};
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struct socfpga_sdr_scc_mgr {
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u32 dqs_ena;
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u32 dqs_io_ena;
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u32 dq_ena;
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u32 dm_ena;
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u32 __padding1[4];
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u32 update;
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u32 __padding2[7];
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u32 active_rank;
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};
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/* PHY manager configuration registers. */
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struct socfpga_phy_mgr_cfg {
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u32 phy_rlat;
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u32 reset_mem_stbl;
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u32 mux_sel;
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u32 cal_status;
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u32 cal_debug_info;
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u32 vfifo_rd_en_ovrd;
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u32 afi_wlat;
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u32 afi_rlat;
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};
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/* PHY manager command addresses. */
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struct socfpga_phy_mgr_cmd {
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u32 inc_vfifo_fr;
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u32 inc_vfifo_hard_phy;
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u32 fifo_reset;
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u32 inc_vfifo_fr_hr;
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u32 inc_vfifo_qr;
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};
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struct socfpga_data_mgr {
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u32 __padding1;
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u32 t_wl_add;
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u32 mem_t_add;
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u32 t_rl_add;
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};
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#endif /* _SEQUENCER_H_ */
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128
drivers/ddr/altera/sequencer_auto.h
Normal file
128
drivers/ddr/altera/sequencer_auto.h
Normal file
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/*
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* Copyright Altera Corporation (C) 2012-2015
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define RW_MGR_READ_B2B_WAIT2 0x6A
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#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
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#define RW_MGR_REFRESH_ALL 0x14
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#define RW_MGR_ZQCL 0x06
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#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
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#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
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#define RW_MGR_ACTIVATE_0_AND_1 0x0D
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#define RW_MGR_MRS2_MIRR 0x0A
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#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
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#define RW_MGR_ACTIVATE_1 0x0F
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#define RW_MGR_MRS2 0x04
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
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#define RW_MGR_MRS1 0x03
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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#define RW_MGR_IDLE_LOOP1 0x7A
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#else
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#define RW_MGR_IDLE_LOOP1 0x7C
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
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#define RW_MGR_MRS3 0x05
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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#define RW_MGR_IDLE_LOOP2 0x79
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#else
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#define RW_MGR_IDLE_LOOP2 0x7B
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
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#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
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#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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#define RW_MGR_RDIMM_CMD 0x78
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#else
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#define RW_MGR_RDIMM_CMD 0x7A
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
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#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
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#define RW_MGR_GUARANTEED_READ_CONT 0x53
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#define RW_MGR_MRS3_MIRR 0x0B
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#define RW_MGR_IDLE 0x00
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#define RW_MGR_READ_B2B 0x58
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#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
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#define RW_MGR_GUARANTEED_WRITE 0x17
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#define RW_MGR_PRECHARGE_ALL 0x12
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#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
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#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define RW_MGR_SGLE_READ 0x7C
|
||||
#else
|
||||
#define RW_MGR_SGLE_READ 0x7E
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
#define RW_MGR_MRS0_USER_MIRR 0x0C
|
||||
#define RW_MGR_RETURN 0x01
|
||||
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
|
||||
#define RW_MGR_MRS0_USER 0x07
|
||||
#define RW_MGR_GUARANTEED_READ 0x4B
|
||||
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
|
||||
#define RW_MGR_INIT_RESET_1_CKE_0 0x73
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
|
||||
#define RW_MGR_MRS0_DLL_RESET 0x02
|
||||
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
|
||||
#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
|
||||
#define RW_MGR_CLEAR_DQS_ENABLE 0x48
|
||||
#define RW_MGR_MRS1_MIRR 0x09
|
||||
#define RW_MGR_READ_B2B_WAIT1 0x60
|
||||
#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
|
||||
#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
|
||||
#define RW_MGR_CONTENT_ZQCL 0x008380
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
|
||||
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
|
||||
#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
|
||||
#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
|
||||
#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
|
||||
#define RW_MGR_CONTENT_MRS2 0x008280
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
|
||||
#define RW_MGR_CONTENT_MRS1 0x008200
|
||||
#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
|
||||
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
|
||||
#define RW_MGR_CONTENT_MRS3 0x008300
|
||||
#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
|
||||
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
|
||||
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
|
||||
#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
|
||||
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
|
||||
#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
|
||||
#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
|
||||
#define RW_MGR_CONTENT_IDLE 0x080000
|
||||
#define RW_MGR_CONTENT_READ_B2B 0x040E88
|
||||
#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
|
||||
#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
|
||||
#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
|
||||
#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
|
||||
#define RW_MGR_CONTENT_SGLE_READ 0x040F08
|
||||
#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
|
||||
#define RW_MGR_CONTENT_RETURN 0x080680
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
|
||||
#define RW_MGR_CONTENT_MRS0_USER 0x008100
|
||||
#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
|
||||
#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
|
||||
#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
|
||||
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
|
||||
#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
|
||||
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
|
||||
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
|
||||
#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
|
||||
#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
|
||||
#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
|
||||
|
||||
84
drivers/ddr/altera/sequencer_auto_ac_init.h
Normal file
84
drivers/ddr/altera/sequencer_auto_ac_init.h
Normal file
@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2015
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
const uint32_t ac_rom_init[] = {
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080831,
|
||||
0x10080930,
|
||||
0x10090004,
|
||||
0x100a0008,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080849,
|
||||
0x100808c8,
|
||||
0x100a0004,
|
||||
0x10090010,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
#else
|
||||
0x20700000,
|
||||
0x20780000,
|
||||
0x10080431,
|
||||
0x10080530,
|
||||
0x10090004,
|
||||
0x100a0008,
|
||||
0x100b0000,
|
||||
0x10380400,
|
||||
0x10080449,
|
||||
0x100804c8,
|
||||
0x100a0004,
|
||||
0x10090010,
|
||||
0x100b0000,
|
||||
0x30780000,
|
||||
0x38780000,
|
||||
0x30780000,
|
||||
0x10680000,
|
||||
0x106b0000,
|
||||
0x10280400,
|
||||
0x10480000,
|
||||
0x1c980000,
|
||||
0x1c9b0000,
|
||||
0x1c980008,
|
||||
0x1c9b0008,
|
||||
0x38f80000,
|
||||
0x3cf80000,
|
||||
0x38780000,
|
||||
0x18180000,
|
||||
0x18980000,
|
||||
0x13580000,
|
||||
0x135b0000,
|
||||
0x13580008,
|
||||
0x135b0008,
|
||||
0x33780000,
|
||||
0x10580008,
|
||||
0x10780000
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
};
|
||||
268
drivers/ddr/altera/sequencer_auto_inst_init.h
Normal file
268
drivers/ddr/altera/sequencer_auto_inst_init.h
Normal file
@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2015
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x8000,
|
||||
0xa000,
|
||||
0xc000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x8080,
|
||||
0xa080,
|
||||
0xc080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
#else
|
||||
const u32 inst_rom_init[] = {
|
||||
0x80000,
|
||||
0x80680,
|
||||
0x8180,
|
||||
0x8200,
|
||||
0x8280,
|
||||
0x8300,
|
||||
0x8380,
|
||||
0x8100,
|
||||
0x8480,
|
||||
0x8500,
|
||||
0x8580,
|
||||
0x8600,
|
||||
0x8400,
|
||||
0x800,
|
||||
0x8680,
|
||||
0x880,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x900,
|
||||
0x80680,
|
||||
0x980,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xb68,
|
||||
0xcce8,
|
||||
0xae8,
|
||||
0x8ce8,
|
||||
0xb88,
|
||||
0xec88,
|
||||
0xa08,
|
||||
0xac88,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0x20ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x60e80,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0x61080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0xce00,
|
||||
0xcd80,
|
||||
0xe700,
|
||||
0xc00,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0x30ce0,
|
||||
0xd00,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x680,
|
||||
0x70e80,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0x71080,
|
||||
0xa680,
|
||||
0x8680,
|
||||
0x80680,
|
||||
0x1158,
|
||||
0x6d8,
|
||||
0x80680,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0x87e8,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x1168,
|
||||
0x7e8,
|
||||
0x7e8,
|
||||
0xa7e8,
|
||||
0x80680,
|
||||
0x40e88,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x40f68,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0xa680,
|
||||
0x40fe8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x410e8,
|
||||
0x41008,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x41088,
|
||||
0x1100,
|
||||
0xc680,
|
||||
0x8680,
|
||||
0xe680,
|
||||
0x80680,
|
||||
0x0,
|
||||
0x0,
|
||||
0xa000,
|
||||
0x8000,
|
||||
0x80000,
|
||||
0x80,
|
||||
0x80,
|
||||
0x80,
|
||||
0x80,
|
||||
0xa080,
|
||||
0x8080,
|
||||
0x80080,
|
||||
0x9180,
|
||||
0x8680,
|
||||
0xa680,
|
||||
0x80680,
|
||||
0x40f08,
|
||||
0x80680
|
||||
};
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
121
drivers/ddr/altera/sequencer_defines.h
Normal file
121
drivers/ddr/altera/sequencer_defines.h
Normal file
@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright Altera Corporation (C) 2012-2015
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _SEQUENCER_DEFINES_H_
|
||||
#define _SEQUENCER_DEFINES_H_
|
||||
|
||||
#define AC_ROM_MR1_MIRR 0000000000100
|
||||
#define AC_ROM_MR1_OCD_ENABLE
|
||||
#define AC_ROM_MR2_MIRR 0000000010000
|
||||
#define AC_ROM_MR3_MIRR 0000000000000
|
||||
#define AC_ROM_MR0_CALIB
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
|
||||
#define AC_ROM_MR0_DLL_RESET 0100100110000
|
||||
#define AC_ROM_MR0_MIRR 0100001001001
|
||||
#define AC_ROM_MR0 0100000110001
|
||||
#else
|
||||
#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
|
||||
#define AC_ROM_MR0_DLL_RESET 0010100110000
|
||||
#define AC_ROM_MR0_MIRR 0010001001001
|
||||
#define AC_ROM_MR0 0010000110001
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
#define AC_ROM_MR1 0000000000100
|
||||
#define AC_ROM_MR2 0000000001000
|
||||
#define AC_ROM_MR3 0000000000000
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define AFI_CLK_FREQ 534
|
||||
#else
|
||||
#define AFI_CLK_FREQ 401
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
#define AFI_RATE_RATIO 1
|
||||
#define AVL_CLK_FREQ 67
|
||||
#define BFM_MODE 0
|
||||
#define BURST2 0
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define CALIB_LFIFO_OFFSET 8
|
||||
#define CALIB_VFIFO_OFFSET 6
|
||||
#else
|
||||
#define CALIB_LFIFO_OFFSET 7
|
||||
#define CALIB_VFIFO_OFFSET 5
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
|
||||
#define ENABLE_SUPER_QUICK_CALIBRATION 0
|
||||
#define GUARANTEED_READ_BRINGUP_TEST 0
|
||||
#define HARD_PHY 1
|
||||
#define HARD_VFIFO 1
|
||||
#define HPS_HW 1
|
||||
#define HR_DDIO_OUT_HAS_THREE_REGS 0
|
||||
#define IO_DELAY_PER_DCHAIN_TAP 25
|
||||
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define IO_DELAY_PER_OPA_TAP 234
|
||||
#else
|
||||
#define IO_DELAY_PER_OPA_TAP 312
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
#define IO_DLL_CHAIN_LENGTH 8
|
||||
#define IO_DM_OUT_RESERVE 0
|
||||
#define IO_DQDQS_OUT_PHASE_MAX 0
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define IO_DQS_EN_DELAY_MAX 15
|
||||
#define IO_DQS_EN_DELAY_OFFSET 16
|
||||
#else
|
||||
#define IO_DQS_EN_DELAY_MAX 31
|
||||
#define IO_DQS_EN_DELAY_OFFSET 0
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
#define IO_DQS_EN_PHASE_MAX 7
|
||||
#define IO_DQS_IN_DELAY_MAX 31
|
||||
#define IO_DQS_IN_RESERVE 4
|
||||
#define IO_DQS_OUT_RESERVE 6
|
||||
#define IO_DQ_OUT_RESERVE 0
|
||||
#define IO_IO_IN_DELAY_MAX 31
|
||||
#define IO_IO_OUT1_DELAY_MAX 31
|
||||
#define IO_IO_OUT2_DELAY_MAX 0
|
||||
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
|
||||
#define MARGIN_VARIATION_TEST 0
|
||||
#define MAX_LATENCY_COUNT_WIDTH 5
|
||||
#define MEM_ADDR_WIDTH 13
|
||||
#define READ_VALID_FIFO_SIZE 16
|
||||
#ifdef CONFIG_SOCFPGA_ARRIA5
|
||||
/* The if..else... is not required if generated by tools */
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
|
||||
#else
|
||||
#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
|
||||
#endif /* CONFIG_SOCFPGA_ARRIA5 */
|
||||
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
|
||||
#define RW_MGR_MEM_ADDRESS_WIDTH 15
|
||||
#define RW_MGR_MEM_BANK_WIDTH 3
|
||||
#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
|
||||
#define RW_MGR_MEM_CLK_EN_WIDTH 1
|
||||
#define RW_MGR_MEM_CONTROL_WIDTH 1
|
||||
#define RW_MGR_MEM_DATA_MASK_WIDTH 5
|
||||
#define RW_MGR_MEM_DATA_WIDTH 40
|
||||
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
|
||||
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
|
||||
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
|
||||
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
|
||||
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
|
||||
#define RW_MGR_MEM_ODT_WIDTH 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
|
||||
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
|
||||
#define RW_MGR_MR0_BL 1
|
||||
#define RW_MGR_MR0_CAS_LATENCY 3
|
||||
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
|
||||
#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
|
||||
#define SKEW_CALIBRATION 0
|
||||
#define TINIT_CNTR1_VAL 32
|
||||
#define TINIT_CNTR2_VAL 32
|
||||
#define TINIT_CNTR0_VAL 132
|
||||
#define TRESET_CNTR1_VAL 99
|
||||
#define TRESET_CNTR2_VAL 10
|
||||
#define TRESET_CNTR0_VAL 132
|
||||
|
||||
#endif /* _SEQUENCER_DEFINES_H_ */
|
||||
Loading…
Reference in New Issue
Block a user