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dm: core: Sort the uclasses
Sort uclasses into alphabetical order and tidy up the comments. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -22,31 +22,31 @@ enum uclass_id {
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UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
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UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
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UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
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UCLASS_SIMPLE_BUS,
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UCLASS_SIMPLE_BUS, /* bus with child devices */
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/* U-Boot uclasses start here */
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/* U-Boot uclasses start here - in alphabetical order */
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UCLASS_CPU, /* CPU, typically part of an SoC */
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UCLASS_CROS_EC, /* Chrome OS EC */
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UCLASS_ETH, /* Ethernet device */
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UCLASS_GPIO, /* Bank of general-purpose I/O pins */
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UCLASS_I2C, /* I2C bus */
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UCLASS_I2C_EEPROM, /* I2C EEPROM device */
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UCLASS_I2C_GENERIC, /* Generic I2C device */
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UCLASS_LPC, /* x86 'low pin count' interface */
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UCLASS_MASS_STORAGE, /* Mass storage device */
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UCLASS_MOD_EXP, /* RSA Mod Exp device */
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_RTC, /* Real time clock device */
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UCLASS_SERIAL, /* Serial UART */
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UCLASS_SPI, /* SPI bus */
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UCLASS_SPI_GENERIC, /* Generic SPI flash target */
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UCLASS_SPI_FLASH, /* SPI flash */
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UCLASS_CROS_EC, /* Chrome OS EC */
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UCLASS_THERMAL, /* Thermal sensor */
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UCLASS_I2C, /* I2C bus */
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UCLASS_I2C_GENERIC, /* Generic I2C device */
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UCLASS_I2C_EEPROM, /* I2C EEPROM device */
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UCLASS_MOD_EXP, /* RSA Mod Exp device */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_ETH, /* Ethernet device */
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UCLASS_LPC, /* x86 'low pin count' interface */
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UCLASS_USB, /* USB bus */
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UCLASS_USB_HUB, /* USB hub */
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UCLASS_USB_DEV_GENERIC, /* USB generic device */
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UCLASS_MASS_STORAGE, /* Mass storage device */
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UCLASS_CPU, /* CPU, typically part of an SoC */
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UCLASS_RTC, /* Real time clock device */
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UCLASS_USB_HUB, /* USB hub */
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UCLASS_COUNT,
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UCLASS_INVALID = -1,
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