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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

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This commit is contained in:
Tom Rini 2017-10-31 08:14:53 -04:00
commit 3c1af17c5e
34 changed files with 185 additions and 93 deletions
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3
arch/arm/include/asm/arch-mx6/imx-regs.h
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@ -346,6 +346,9 @@
#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) #define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#endif #endif
#define NOC_DDR_BASE_ADDR (GPV0_BASE_ADDR + 0xB0000)
/* Only for i.MX6SX */ /* Only for i.MX6SX */
#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)

10
board/dhelectronics/dh_imx6/dh_imx6.c
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@ -252,17 +252,11 @@ static void setup_usb(void)
} }
int board_usb_phy_mode(int port) int board_usb_phy_mode(int port)
{
return USB_INIT_HOST;
}
/* Use only Port 1 == DHCOM USB Host 1 */
int board_ehci_hcd_init(int port)
{ {
if (port == 1) if (port == 1)
return 0; return USB_INIT_HOST;
else else
return -ENODEV; return USB_INIT_DEVICE;
} }
int board_ehci_power(int port, int on) int board_ehci_power(int port, int on)

52
board/freescale/mx6slevk/mx6slevk.c
View File

@ -27,8 +27,6 @@
#include <power/pmic.h> #include <power/pmic.h>
#include <power/pfuze100_pmic.h> #include <power/pfuze100_pmic.h>
#include "../common/pfuze.h" #include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -223,49 +221,6 @@ static int setup_fec(void)
} }
#endif #endif
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
/* OTG1 */
MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
/* OTG2 */
MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};
static void setup_usb(void)
{
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));
}
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return usb_phy_mode(port);
}
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
/* Set Power polarity */
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
#endif
int board_early_init_f(void) int board_early_init_f(void)
{ {
setup_iomux_uart(); setup_iomux_uart();
@ -287,10 +242,6 @@ int board_init(void)
setup_fec(); setup_fec();
#endif #endif
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
return 0; return 0;
} }
@ -322,12 +273,15 @@ int board_mmc_getcd(struct mmc *mmc)
switch (cfg->esdhc_base) { switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR: case USDHC1_BASE_ADDR:
gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
ret = !gpio_get_value(USDHC1_CD_GPIO); ret = !gpio_get_value(USDHC1_CD_GPIO);
break; break;
case USDHC2_BASE_ADDR: case USDHC2_BASE_ADDR:
gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
ret = !gpio_get_value(USDHC2_CD_GPIO); ret = !gpio_get_value(USDHC2_CD_GPIO);
break; break;
case USDHC3_BASE_ADDR: case USDHC3_BASE_ADDR:
gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
ret = !gpio_get_value(USDHC3_CD_GPIO); ret = !gpio_get_value(USDHC3_CD_GPIO);
break; break;
} }

1
board/udoo/udoo.c
View File

@ -245,7 +245,6 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SATA #ifdef CONFIG_SATA
if (is_cpu_type(MXC_CPU_MX6Q))
setup_sata(); setup_sata();
#endif #endif
return 0; return 0;

125
board/wandboard/spl.c
View File

@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX6DQ_DRIVE_STRENGTH 0x30 #define IMX6DQ_DRIVE_STRENGTH 0x30
#define IMX6SDL_DRIVE_STRENGTH 0x28 #define IMX6SDL_DRIVE_STRENGTH 0x28
#define IMX6QP_DRIVE_STRENGTH 0x28
/* configure MX6Q/DUAL mmdc DDR io registers */ /* configure MX6Q/DUAL mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
@ -63,6 +64,36 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
}; };
/* configure MX6QP mmdc DDR io registers */
static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
.dram_cas = IMX6QP_DRIVE_STRENGTH,
.dram_ras = IMX6QP_DRIVE_STRENGTH,
.dram_reset = IMX6QP_DRIVE_STRENGTH,
.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
};
/* configure MX6Q/DUAL mmdc GRP io registers */ /* configure MX6Q/DUAL mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
.grp_ddr_type = 0x000c0000, .grp_ddr_type = 0x000c0000,
@ -81,6 +112,24 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
.grp_b7ds = IMX6DQ_DRIVE_STRENGTH, .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
}; };
/* configure MX6QP mmdc GRP io registers */
static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
.grp_ddr_type = 0x000c0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = IMX6QP_DRIVE_STRENGTH,
.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
.grp_ddrmode = 0x00020000,
.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
};
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
@ -260,15 +309,87 @@ static void ccgr_init(void)
writel(0x00C03F3F, &ccm->CCGR0); writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1); writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2); writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3); writel(0x3FF03000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4); writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5); writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6); writel(0x000003FF, &ccm->CCGR6);
} }
static void spl_dram_init_imx6qp_lpddr3(void)
{
/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
/* Calibrations - ZQ */
writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
/* write leveling */
writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
/*
* DQS gating, read delay, write delay calibration values
* based on calibration compare of 0x00ffff00
*/
writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
/* add NOC DDR configuration */
writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
}
static void spl_dram_init(void) static void spl_dram_init(void)
{ {
if (is_cpu_type(MXC_CPU_MX6SOLO)) { if (is_mx6dqp()) {
mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
spl_dram_init_imx6qp_lpddr3();
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
} else if (is_cpu_type(MXC_CPU_MX6DL)) { } else if (is_cpu_type(MXC_CPU_MX6DL)) {

8
board/wandboard/wandboard.c
View File

@ -435,8 +435,6 @@ int board_early_init_f(void)
{ {
setup_iomux_uart(); setup_iomux_uart();
#ifdef CONFIG_SATA #ifdef CONFIG_SATA
/* Only mx6q wandboard has SATA */
if (is_cpu_type(MXC_CPU_MX6Q))
setup_sata(); setup_sata();
#endif #endif
@ -512,7 +510,9 @@ int board_late_init(void)
#endif #endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (is_mx6dq()) if (is_mx6dqp())
env_set("board_rev", "MX6QP");
else if (is_mx6dq())
env_set("board_rev", "MX6Q"); env_set("board_rev", "MX6Q");
else else
env_set("board_rev", "MX6DL"); env_set("board_rev", "MX6DL");
@ -534,7 +534,7 @@ int board_init(void)
#if defined(CONFIG_VIDEO_IPUV3) #if defined(CONFIG_VIDEO_IPUV3)
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
if (is_mx6dq()) { if (is_mx6dq() || is_mx6dqp()) {
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
} else { } else {

8
configs/dh_imx6_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y CONFIG_CMD_MEMTEST=y
CONFIG_CMD_UNZIP=y CONFIG_CMD_UNZIP=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set # CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y CONFIG_CMD_I2C=y
@ -27,6 +28,7 @@ CONFIG_CMD_PART=y
CONFIG_CMD_SATA=y CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y CONFIG_CMD_SF=y
CONFIG_CMD_USB=y CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y CONFIG_CMD_MII=y
CONFIG_CMD_PING=y CONFIG_CMD_PING=y
@ -47,4 +49,10 @@ CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y CONFIG_FEC_MXC=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="dh"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_OF_LIBFDT=y CONFIG_OF_LIBFDT=y

1
configs/imx6q_logic_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_NAND=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_MXC=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_MXS=y CONFIG_NAND_MXS=y

1
configs/imx6qdl_icore_nand_defconfig
View File

@ -31,7 +31,6 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y CONFIG_CMD_UBI=y
CONFIG_OF_LIST="imx6q-icore imx6dl-icore" CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_NAND=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_MXC=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_MXS=y CONFIG_NAND_MXS=y

1
configs/imx6ul_geam_mmc_defconfig
View File

@ -32,7 +32,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_MXC=y
CONFIG_PHYLIB=y CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y CONFIG_PHY_SMSC=y

1
configs/imx6ul_geam_nand_defconfig
View File

@ -31,7 +31,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_NAND=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_MXC=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_MXS=y CONFIG_NAND_MXS=y

1
configs/imx6ul_isiot_emmc_defconfig
View File

@ -31,7 +31,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLK is not set
CONFIG_PHYLIB=y CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y CONFIG_FEC_MXC=y

1
configs/imx6ul_isiot_mmc_defconfig
View File

@ -32,7 +32,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_MXC=y
CONFIG_PHYLIB=y CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y CONFIG_PHY_SMSC=y

1
configs/imx6ul_isiot_nand_defconfig
View File

@ -31,7 +31,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_NAND=y
# CONFIG_BLK is not set
CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_MXC=y
CONFIG_NAND=y CONFIG_NAND=y
CONFIG_NAND_MXS=y CONFIG_NAND_MXS=y

2
configs/mx6slevk_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
@ -45,6 +44,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y CONFIG_DM_THERMAL=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX=y

2
configs/mx6slevk_spinor_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y
@ -45,6 +44,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y CONFIG_DM_THERMAL=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX=y

16
configs/mx6slevk_spl_defconfig
View File

@ -9,7 +9,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y
# CONFIG_CMD_BMODE is not set # CONFIG_CMD_BMODE is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL,SYS_I2C" CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6SL"
CONFIG_BOOTDELAY=3 CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y CONFIG_SPL=y
@ -32,13 +33,26 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y CONFIG_PHYLIB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_THERMAL=y CONFIG_DM_THERMAL=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX=y

1
configs/mx6sllevk_defconfig
View File

@ -24,7 +24,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y

1
configs/mx6sllevk_plugin_defconfig
View File

@ -25,7 +25,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_DM_MMC=y CONFIG_DM_MMC=y

2
configs/mx6sxsabreauto_defconfig
View File

@ -28,7 +28,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
@ -47,6 +46,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_GPIO=y
CONFIG_FSL_QSPI=y CONFIG_FSL_QSPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX=y

1
configs/mx6ull_14x14_evk_defconfig
View File

@ -21,7 +21,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y CONFIG_DM_74X164=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/mx6ull_14x14_evk_plugin_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y CONFIG_DM_74X164=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/mx7dsabresd_defconfig
View File

@ -36,7 +36,6 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y

1
configs/mx7dsabresd_secure_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y

1
configs/mx7ulp_evk_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_IMX_RGPIO2P=y CONFIG_IMX_RGPIO2P=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/mx7ulp_evk_plugin_defconfig
View File

@ -11,7 +11,6 @@ CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
CONFIG_IMX_RGPIO2P=y CONFIG_IMX_RGPIO2P=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y

1
configs/opos6uldev_defconfig
View File

@ -56,7 +56,6 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y CONFIG_REGMAP=y
CONFIG_SYSCON=y CONFIG_SYSCON=y
# CONFIG_BLK is not set
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y CONFIG_SYS_I2C_MXC=y
CONFIG_PWRSEQ=y CONFIG_PWRSEQ=y

2
drivers/net/fec_mxc.c
View File

@ -882,7 +882,7 @@ static int fec_recv(struct eth_device *dev)
len = frame_length; len = frame_length;
} else { } else {
if (bd_status & FEC_RBD_ERR) if (bd_status & FEC_RBD_ERR)
printf("error frame: 0x%08x 0x%08x\n", debug("error frame: 0x%08x 0x%08x\n",
addr, bd_status); addr, bd_status);
} }

4
include/configs/colibri_vf.h
View File

@ -75,8 +75,8 @@
#define CONFIG_FDTADDR 0x84000000 #define CONFIG_FDTADDR 0x84000000
/* We boot from the gfxRAM area of the OCRAM. */ /* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_SYS_TEXT_BASE 0x3f408000 #define CONFIG_SYS_TEXT_BASE 0x3f401000
#define CONFIG_BOARD_SIZE_LIMIT 524288 #define CONFIG_BOARD_SIZE_LIMIT 520192
#define SD_BOOTCMD \ #define SD_BOOTCMD \
"sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \

12
include/configs/dh_imx6.h
View File

@ -115,6 +115,18 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
/* USB Gadget (DFU, UMS) */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
#endif
#endif #endif
/* Watchdog */ /* Watchdog */

1
include/configs/opos6uldev.h
View File

@ -17,6 +17,7 @@
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_GPIO #undef CONFIG_DM_GPIO
#undef CONFIG_DM_MMC #undef CONFIG_DM_MMC
#undef CONFIG_BLK
#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_MXC_UART_BASE UART1_BASE
#endif #endif

4
include/configs/pcm052.h
View File

@ -89,8 +89,8 @@
#define CONFIG_LOADADDR 0x82000000 #define CONFIG_LOADADDR 0x82000000
/* We boot from the gfxRAM area of the OCRAM. */ /* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_SYS_TEXT_BASE 0x3f408000 #define CONFIG_SYS_TEXT_BASE 0x3f401000
#define CONFIG_BOARD_SIZE_LIMIT 524288 #define CONFIG_BOARD_SIZE_LIMIT 520192
/* if no target-specific extra environment settings were defined by the /* if no target-specific extra environment settings were defined by the
target, define an empty one */ target, define an empty one */

4
include/configs/vf610twr.h
View File

@ -79,8 +79,8 @@
#define CONFIG_SYS_LOAD_ADDR 0x82000000 #define CONFIG_SYS_LOAD_ADDR 0x82000000
/* We boot from the gfxRAM area of the OCRAM. */ /* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_SYS_TEXT_BASE 0x3f408000 #define CONFIG_SYS_TEXT_BASE 0x3f401000
#define CONFIG_BOARD_SIZE_LIMIT 524288 #define CONFIG_BOARD_SIZE_LIMIT 520192
/* /*
* We do have 128MB of memory on the Vybrid Tower board. Leave the last * We do have 128MB of memory on the Vybrid Tower board. Leave the last

2
include/configs/wandboard.h
View File

@ -109,6 +109,8 @@
"fi; " \ "fi; " \
"fi\0" \ "fi\0" \
"findfdt="\ "findfdt="\
"if test $board_name = D1 && test $board_rev = MX6QP ; then " \
"setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \
"if test $board_name = D1 && test $board_rev = MX6Q ; then " \ "if test $board_name = D1 && test $board_rev = MX6Q ; then " \
"setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \ "setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \
"if test $board_name = D1 && test $board_rev = MX6DL ; then " \ "if test $board_name = D1 && test $board_rev = MX6DL ; then " \