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nios2: use bitops from linux-2.6 asm-generic
These are needed to use ubi/ubifs. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This commit is contained in:
Thomas Chou
Scott McNutt
parent
d8b73dffa9
commit
3bef253f08
@ -24,15 +24,9 @@
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#ifndef __ASM_NIOS2_BITOPS_H_
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#define __ASM_NIOS2_BITOPS_H_
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extern void set_bit(int nr, volatile void * a);
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extern void clear_bit(int nr, volatile void * a);
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extern int test_and_clear_bit(int nr, volatile void * a);
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extern void change_bit(unsigned long nr, volatile void *addr);
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extern int test_and_set_bit(int nr, volatile void * a);
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extern int test_and_change_bit(int nr, volatile void * addr);
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extern int test_bit(int nr, volatile void * a);
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extern int ffs(int i);
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#define PLATFORM_FFS
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/* copied from linux-2.6/include/asm-generic/bitops */
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#include <asm/bitops/atomic.h>
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#include <asm/bitops/non-atomic.h>
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#include <asm/bitops/ffs.h>
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#endif /* __ASM_NIOS2_BITOPS_H */
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189
include/asm-nios2/bitops/atomic.h
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189
include/asm-nios2/bitops/atomic.h
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@ -0,0 +1,189 @@
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#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_
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#define _ASM_GENERIC_BITOPS_ATOMIC_H_
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#include <asm/types.h>
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#include <asm/system.h>
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#ifdef CONFIG_SMP
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#include <asm/spinlock.h>
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#include <asm/cache.h> /* we use L1_CACHE_BYTES */
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/* Use an array of spinlocks for our atomic_ts.
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* Hash function to index into a different SPINLOCK.
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* Since "a" is usually an address, use one spinlock per cacheline.
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*/
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# define ATOMIC_HASH_SIZE 4
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# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
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extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
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/* Can't use raw_spin_lock_irq because of #include problems, so
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* this is the substitute */
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#define _atomic_spin_lock_irqsave(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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local_irq_save(f); \
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__raw_spin_lock(s); \
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} while(0)
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#define _atomic_spin_unlock_irqrestore(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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__raw_spin_unlock(s); \
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local_irq_restore(f); \
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} while(0)
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#else
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# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
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# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
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#endif
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/*
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* NMI events can occur at any time, including when interrupts have been
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* disabled by *_irqsave(). So you can get NMI events occurring while a
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* *_bit function is holding a spin lock. If the NMI handler also wants
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* to do bit manipulation (and they do) then you can get a deadlock
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* between the original caller of *_bit() and the NMI handler.
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*
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* by Keith Owens
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*/
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writing portable code,
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* make sure not to rely on its reordering guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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*p |= mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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*p &= ~mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered. It may be
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* reordered on other architectures than x86.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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*p ^= mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It may be reordered on other architectures than x86.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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old = *p;
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*p = old | mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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return (old & mask) != 0;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It can be reorderdered on other architectures other than x86.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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old = *p;
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*p = old & ~mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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return (old & mask) != 0;
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old;
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unsigned long flags;
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_atomic_spin_lock_irqsave(p, flags);
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old = *p;
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*p = old ^ mask;
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_atomic_spin_unlock_irqrestore(p, flags);
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return (old & mask) != 0;
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}
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#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */
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41
include/asm-nios2/bitops/ffs.h
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41
include/asm-nios2/bitops/ffs.h
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@ -0,0 +1,41 @@
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#ifndef _ASM_GENERIC_BITOPS_FFS_H_
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#define _ASM_GENERIC_BITOPS_FFS_H_
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/**
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* ffs - find first bit set
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* @x: the word to search
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*
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* This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static inline int ffs(int x)
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{
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int r = 1;
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if (!x)
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return 0;
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if (!(x & 0xffff)) {
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x >>= 16;
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r += 16;
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}
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if (!(x & 0xff)) {
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x >>= 8;
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r += 8;
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}
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if (!(x & 0xf)) {
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x >>= 4;
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r += 4;
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}
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if (!(x & 3)) {
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x >>= 2;
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r += 2;
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}
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if (!(x & 1)) {
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x >>= 1;
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r += 1;
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}
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return r;
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}
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#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */
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108
include/asm-nios2/bitops/non-atomic.h
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108
include/asm-nios2/bitops/non-atomic.h
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@ -0,0 +1,108 @@
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#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
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#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
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#include <asm/types.h>
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p |= mask;
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}
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static inline void __clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p &= ~mask;
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}
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p ^= mask;
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old | mask;
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return (old & mask) != 0;
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old & ~mask;
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return (old & mask) != 0;
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}
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/* WARNING: non atomic and it can be reordered! */
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static inline int __test_and_change_bit(int nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old ^ mask;
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return (old & mask) != 0;
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}
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/**
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* test_bit - Determine whether a bit is set
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* @nr: bit number to test
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* @addr: Address to start counting from
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*/
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static inline int test_bit(int nr, const volatile unsigned long *addr)
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{
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return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
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}
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#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */
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