mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-29 07:33:29 +08:00
Code Issues Packages Projects Releases Wiki Activity

mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()

Browse Source 
As noticed while working on the USB xHCI support, Octeon needs to flush
all pending writes so that the values are present in the memory. Add
this "syncw" instruction (twice) to flush_dcache_range().

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2020-08-24 13:04:41 +02:00 committed by Daniel Schwierzeck
parent b28d35234c
commit 399b867fac
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/mips/mach-octeon/cache.c
View File

@ -5,14 +5,13 @@
#include <cpu_func.h>
/*
* The Octeon platform is cache coherent and cache flushes and invalidates
* are not needed. Define some platform specific empty flush_foo()
* functions here to overwrite the _weak common function as a no-op.
* This effectively disables all cache operations.
*/
/* Octeon memory write barrier */
#define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : : "memory")
void flush_dcache_range(ulong start_addr, ulong stop)
{
/* Flush all pending writes */
CVMX_SYNCW;
}
void flush_cache(ulong start_addr, ulong size)
@ -21,4 +20,5 @@ void flush_cache(ulong start_addr, ulong size)
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
/* Don't need to do anything for OCTEON */
}