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board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
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parent
21be309bb7
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39441b35c6
@ -28,8 +28,10 @@ endif
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \
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../common/usb_uhci.o ../common/common_util.o
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COBJS = $(BOARD).o cmd_mip405.o \
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../common/pci.o \
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../common/usb_uhci.o \
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../common/common_util.o
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SOBJS = init.o
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@ -498,6 +498,27 @@ int board_early_init_f (void)
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return 0;
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}
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int board_early_init_r(void)
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{
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int mode;
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/*
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* since we are relocated, we can finally enable i-cache
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* and set up the flash CS correctly
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*/
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icache_enable();
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setup_cs_reloc();
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/* get and display boot mode */
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mode = get_boot_mode();
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if (mode & BOOT_PCI)
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printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
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"MPS" : "Flash");
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else
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printf("%s Boot\n", (mode & BOOT_MPS) ?
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"MPS" : "Flash");
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return 0;
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}
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/*
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* Get some PLD Registers
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@ -671,7 +692,6 @@ static int test_dram (unsigned long ramsize)
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/* used to check if the time in RTC is valid */
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static unsigned long start;
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static struct rtc_time tm;
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extern flash_info_t flash_info[]; /* info for FLASH chips */
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int misc_init_r (void)
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{
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@ -239,11 +239,17 @@
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_UPDATE_FLASH_SIZE
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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/*
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* JFFS2 partitions
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@ -291,6 +297,7 @@
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#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_BOARD_EARLY_INIT_R
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/* Peripheral Bus Mapping */
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#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
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