mirror of
https://github.com/u-boot/u-boot.git
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Seagate FreeAgent DockStar support
start with sheevaplug configuration
add modifications by Alexander Holler <holler@ahsoftware.de>
change RAM definitions to one bank (128 MB)
change ident string and prompt
define MTD partitions and default environment variables
add support for LEDs
Signed-off-by: Eric Cooper <ecc@cmu.edu>
This commit is contained in:
Eric Cooper
Wolfgang Denk
parent
e81bb57f2d
commit
38041db740
@ -591,6 +591,10 @@ Po-Yu Chuang <ratbert@faraday-tech.com>
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a320evb FA526 (ARM920T-like) (a320 SoC)
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Eric Cooper <ecc@cmu.edu>
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dockstar ARM926EJS (Kirkwood SoC)
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George G. Davis <gdavis@mvista.com>
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assabet SA1100
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54
board/Seagate/dockstar/Makefile
Normal file
54
board/Seagate/dockstar/Makefile
Normal file
@ -0,0 +1,54 @@
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#
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# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
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#
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# Based on sheevaplug/Makefile originally written by
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# Prafulla Wadaskar <prafulla@marvell.com>
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := dockstar.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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181
board/Seagate/dockstar/dockstar.c
Normal file
181
board/Seagate/dockstar/dockstar.c
Normal file
@ -0,0 +1,181 @@
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/*
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* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
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*
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* Based on sheevaplug.c originally written by
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* Prafulla Wadaskar <prafulla@marvell.com>
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "dockstar.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(DOCKSTAR_OE_VAL_LOW,
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DOCKSTAR_OE_VAL_HIGH,
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DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_UART0_RTS,
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MPP9_UART0_CTS,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_TSMP9,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config);
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return 0;
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}
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int board_init(void)
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{
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/*
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* arch number of board
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*/
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gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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u16 reg;
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u16 devadr;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__FUNCTION__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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#define GREEN_LED (1 << 14)
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#define ORANGE_LED (1 << 15)
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#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
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#define NEITHER_LED 0
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static void set_leds(u32 leds, u32 blinking)
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{
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struct kwgpio_registers *r = (struct kwgpio_registers *)KW_GPIO1_BASE;
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u32 oe = readl(&r->oe) | BOTH_LEDS;
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writel(oe & ~leds, &r->oe); /* active low */
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u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
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writel(bl | blinking, &r->blink_en);
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}
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void show_boot_progress(int val)
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{
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switch (val) {
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case 15: /* booting Linux */
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set_leds(BOTH_LEDS, NEITHER_LED);
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break;
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case 64: /* Ethernet initialization */
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set_leds(GREEN_LED, GREEN_LED);
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break;
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default:
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if (val < 0) /* error */
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set_leds(ORANGE_LED, ORANGE_LED);
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break;
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}
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}
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44
board/Seagate/dockstar/dockstar.h
Normal file
44
board/Seagate/dockstar/dockstar.h
Normal file
@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
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*
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* Based on sheevaplug.h originally written by
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* Prafulla Wadaskar <prafulla@marvell.com>
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __DOCKSTAR_H
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#define __DOCKSTAR_H
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#define DOCKSTAR_OE_LOW (~(0))
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#define DOCKSTAR_OE_HIGH (~(0))
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#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
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#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
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/* PHY related */
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __DOCKSTAR_H */
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165
board/Seagate/dockstar/kwbimage.cfg
Normal file
165
board/Seagate/dockstar/kwbimage.cfg
Normal file
@ -0,0 +1,165 @@
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#
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# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
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#
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# Based on sheevaplug/kwbimage.cfg originally written by
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# Prafulla Wadaskar <prafulla@marvell.com>
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
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# MA 02110-1301 USA
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#
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# Refer docs/README.kwimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM nand
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NAND_ECC_MODE default
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NAND_PAGE_SIZE 0x0800
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xFFD100e0 0x1b1b1b9b
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
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# bit23-14: zero
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# bit24: 1= enable exit self refresh mode on DDR access
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# bit25: 1 required
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# bit29-26: zero
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# bit31-30: 01
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DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
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# bit 4: 0=addr/cmd in smame cycle
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# bit 5: 0=clk is driven during self refresh, we don't care for APX
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# bit 6: 0=use recommended falling edge of clk for addr/cmd
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# bit14: 0=input buffer always powered up
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# bit18: 1=cpu lock transaction enabled
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 3 required
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# bit31: 0=no additional STARTBURST delay
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DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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# bit3-0: TRAS lsbs
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# bit7-4: TRCD
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# bit11- 8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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||||
# bit31-13: zero required
|
||||
|
||||
DATA 0xFFD01410 0x0000000d # DDR Address Control
|
||||
# bit1-0: 00, Cs0width=x8
|
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# bit3-2: 11, Cs0size=1Gb
|
||||
# bit5-4: 00, Cs1width=nonexistent
|
||||
# bit7-6: 00, Cs1size =nonexistent
|
||||
# bit9-8: 00, Cs2width=nonexistent
|
||||
# bit11-10: 00, Cs2size =nonexistent
|
||||
# bit13-12: 00, Cs3width=nonexistent
|
||||
# bit15-14: 00, Cs3size =nonexistent
|
||||
# bit16: 0, Cs0AddrSel
|
||||
# bit17: 0, Cs1AddrSel
|
||||
# bit18: 0, Cs2AddrSel
|
||||
# bit19: 0, Cs3AddrSel
|
||||
# bit31-20: 0 required
|
||||
|
||||
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
|
||||
# bit0: 0, OpenPage enabled
|
||||
# bit31-1: 0 required
|
||||
|
||||
DATA 0xFFD01418 0x00000000 # DDR Operation
|
||||
# bit3-0: 0x0, DDR cmd
|
||||
# bit31-4: 0 required
|
||||
|
||||
DATA 0xFFD0141C 0x00000C52 # DDR Mode
|
||||
# bit2-0: 2, BurstLen=2 required
|
||||
# bit3: 0, BurstType=0 required
|
||||
# bit6-4: 4, CL=5
|
||||
# bit7: 0, TestMode=0 normal
|
||||
# bit8: 0, DLL reset=0 normal
|
||||
# bit11-9: 6, auto-precharge write recovery ????????????
|
||||
# bit12: 0, PD must be zero
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01420 0x00000040 # DDR Extended Mode
|
||||
# bit0: 0, DDR DLL enabled
|
||||
# bit1: 0, DDR drive strenght normal
|
||||
# bit2: 0, DDR ODT control lsd (disabled)
|
||||
# bit5-3: 000, required
|
||||
# bit6: 1, DDR ODT control msb, (disabled)
|
||||
# bit9-7: 000, required
|
||||
# bit10: 0, differential DQS enabled
|
||||
# bit11: 0, required
|
||||
# bit12: 0, DDR output buffer enabled
|
||||
# bit31-13: 0 required
|
||||
|
||||
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
|
||||
# bit2-0: 111, required
|
||||
# bit3 : 1 , MBUS Burst Chop disabled
|
||||
# bit6-4: 111, required
|
||||
# bit7 : 0
|
||||
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
||||
# bit9 : 0 , no half clock cycle addition to dataout
|
||||
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
|
||||
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
||||
# bit15-12: 1111 required
|
||||
# bit31-16: 0 required
|
||||
|
||||
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
|
||||
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
|
||||
|
||||
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
|
||||
DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
|
||||
# bit0: 1, Window enabled
|
||||
# bit1: 0, Write Protect disabled
|
||||
# bit3-2: 00, CS0 hit selected
|
||||
# bit23-4: ones, required
|
||||
# bit31-24: 0x07, Size (i.e. 128MB)
|
||||
|
||||
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
|
||||
DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
|
||||
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
|
||||
|
||||
DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
|
||||
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
|
||||
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
|
||||
# bit3-2: 01, ODT1 active NEVER!
|
||||
# bit31-4: zero, required
|
||||
|
||||
DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
|
||||
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
|
||||
#bit0=1, enable DDR init upon this register write
|
||||
|
||||
# End of Header extension
|
||||
DATA 0x0 0x0
|
||||
@ -53,6 +53,7 @@ pm9261 arm arm926ejs - ronetix at91
|
||||
pm9263 arm arm926ejs - ronetix at91
|
||||
suen3 arm arm926ejs km_arm keymile kirkwood
|
||||
rd6281a arm arm926ejs - Marvell kirkwood
|
||||
dockstar arm arm926ejs - Seagate kirkwood
|
||||
jadecpu arm arm926ejs jadecpu syteco mb86r0x
|
||||
mx51evk arm armv7 mx51evk freescale mx5
|
||||
vision2 arm armv7 vision2 ttcontrol mx5
|
||||
|
||||
125
include/configs/dockstar.h
Normal file
125
include/configs/dockstar.h
Normal file
@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
|
||||
*
|
||||
* Based on sheevaplug.h originally written by
|
||||
* Prafulla Wadaskar <prafulla@marvell.com>
|
||||
* (C) Copyright 2009
|
||||
* Marvell Semiconductor <www.marvell.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_DOCKSTAR_H
|
||||
#define _CONFIG_DOCKSTAR_H
|
||||
|
||||
/*
|
||||
* Version number information
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING "\nSeagate FreeAgent DockStar"
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
|
||||
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
|
||||
#define CONFIG_KW88F6281 1 /* SOC Name */
|
||||
#define CONFIG_MACH_DOCKSTAR /* Machine type */
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
|
||||
#define CONFIG_SYS_PROMPT "DockStar> " /* Command Prompt */
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
|
||||
#endif
|
||||
/*
|
||||
* max 4k env size is enough, but in case of nand
|
||||
* it has to be rounded to sector size
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
|
||||
#define CONFIG_ENV_ADDR 0x60000
|
||||
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
|
||||
"ubi part root; " \
|
||||
"ubifsmount root; " \
|
||||
"ubifsload 0x800000 ${kernel}; " \
|
||||
"ubifsload 0x1100000 ${initrd}; " \
|
||||
"bootm 0x800000 0x1100000"
|
||||
|
||||
#define CONFIG_MTDPARTS "mtdparts=orion_nand:1m(uboot),-(root)\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console=console=ttyS0,115200\0" \
|
||||
"mtdids=nand0=orion_nand\0" \
|
||||
"mtdparts="CONFIG_MTDPARTS \
|
||||
"kernel=/boot/uImage\0" \
|
||||
"initrd=/boot/uInitrd\0" \
|
||||
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
||||
#define CONFIG_PHY_BASE_ADR 0
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* File system
|
||||
*/
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_LZO
|
||||
|
||||
#endif /* _CONFIG_DOCKSTAR_H */
|
||||
Loading…
Reference in New Issue
Block a user