From 6ad8c743001c1114c5921f78c17e6fb43d4b6ca0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 23 Jun 2015 19:57:23 +0800 Subject: [PATCH 1/5] sunxi: hardware-feature-specific function index defines for PORT F UART0 Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/cpu/armv7/sunxi/board.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 03443629bcd..1c268656ff1 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -45,11 +45,11 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); #endif #if defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); #else - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); #endif sunxi_gpio_set_pull(SUNXI_GPF(4), 1); #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) From dec7c84227339cda4bf6c7d9a411ea189473112d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 23 Jun 2015 19:57:24 +0800 Subject: [PATCH 2/5] sunxi: rsb: Enable R_PIO clock before configuring external pins The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai Cc: Maxime Ripard Tested-by: Maxime Ripard Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/cpu/armv7/sunxi/rsb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c index f115a9cac41..6fd11f15298 100644 --- a/arch/arm/cpu/armv7/sunxi/rsb.c +++ b/arch/arm/cpu/armv7/sunxi/rsb.c @@ -60,11 +60,12 @@ int rsb_init(void) struct sunxi_rsb_reg * const rsb = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - rsb_cfg_io(); - /* Enable RSB and PIO clk, and de-assert their resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + /* Setup external pins */ + rsb_cfg_io(); + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); rsb_set_clk(); From e506889c9690b672a601ac84a31bb8dbc40d7e35 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 23 Jun 2015 19:57:25 +0800 Subject: [PATCH 3/5] sunxi: Add support for UART0 in PB pin group on A33 The A33 adds a pinmux function for UART0 in the PB pin group. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/cpu/armv7/sunxi/board.c | 4 ++++ arch/arm/include/asm/arch-sunxi/gpio.h | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 1c268656ff1..5f39aa07cfb 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -64,6 +64,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 496295d3573..8e67b3bcb87 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -156,6 +156,7 @@ enum sunxi_gpio_number { #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 +#define SUN8I_A33_GPB_UART0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 From d8656b6297cb8c08f80adbbe717bd06e150fb759 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 23 Jun 2015 19:57:26 +0800 Subject: [PATCH 4/5] sunxi: Sync sun8i dts files with the linux kernel Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2. This adds a dts file for Sinlinx SinA33 dev board, and the required changes in the .dtsi files. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/dts/sun8i-a23-a33.dtsi | 10 ++ arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 129 ++++++++++++++++++++++ arch/arm/dts/sun8i-a33.dtsi | 8 ++ 3 files changed, 147 insertions(+) create mode 100644 arch/arm/dts/sun8i-a33-sinlinx-sina33.dts diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index faea94e45ee..7abd0ae3143 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -366,6 +366,16 @@ allwinner,pull = ; }; + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = ; + allwinner,pull = ; + }; + i2c0_pins_a: i2c0@0 { allwinner,pins = "PH2", "PH3"; allwinner,function = "i2c0"; diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts new file mode 100644 index 00000000000..5788c29cb56 --- /dev/null +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts @@ -0,0 +1,129 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Sinlinx SinA33"; + compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <191011>; + }; + + button@400 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <391304>; + }; + + button@600 { + label = "Home"; + linux,code = ; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* eMMC is missing pull-ups */ + allwinner,pull = ; +}; + +&pio { + mmc0_cd_pin_sina33: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 9b43bc6e792..85ee08098b7 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -86,4 +86,12 @@ compatible = "allwinner,sun8i-a33-pinctrl"; interrupts = , ; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; From 4e87398fcc946c076339e8ed9bf1cc576fd42cf7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 23 Jun 2015 19:57:27 +0800 Subject: [PATCH 5/5] sunxi: Add Sinlinx SinA33 defconfig Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO and GPIO headers. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/dts/Makefile | 3 ++- board/sunxi/MAINTAINERS | 6 ++++++ configs/Sinlinx_SinA33_defconfig | 16 ++++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 configs/Sinlinx_SinA33_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c735c672ab..bbca94f1a08 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -128,7 +128,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb + sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb \ + sun8i-a33-sinlinx-sina33.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 7a420555593..1f12a646e48 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -162,6 +162,12 @@ M: Siarhei Siamashka S: Maintained F: configs/MSI_Primo81_defconfig +SINLINX SINA33 BOARD +M: Chen-Yu Tsai +S: Maintained +F: configs/Sinlinx_SinA33_defconfig +W: http://linux-sunxi.org/Sinlinx_SinA33 + TZX-Q8-713B7 BOARD M: Paul Kocialkowski S: Maintained diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig new file mode 100644 index 00000000000..e9e62da101d --- /dev/null +++ b/configs/Sinlinx_SinA33_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=552 +CONFIG_DRAM_ZQ=15291 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_DM_ETH=y +CONFIG_DM_SERIAL=y +CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB=y +CONFIG_DM_USB=y