diff --git a/CREDITS b/CREDITS index 802158879f2..0099bd46c26 100644 --- a/CREDITS +++ b/CREDITS @@ -160,6 +160,10 @@ N: Thomas Frieden E: ThomasF@hyperion-entertainment.com D: Support for AmigaOne +N: Paul Gortmaker +E: paul.gortmaker@windriver.com +D: Support for WRS SBC8347/8349 boards + N: Frank Gottschling E: fgottschling@eltec.de D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM diff --git a/MAINTAINERS b/MAINTAINERS index 1d0a8dfdb31..183fb10d963 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -350,6 +350,7 @@ John Zhan Timur Tabi MPC8349E-mITX MPC8349 + MPC8349E-mITX-GP MPC8349 Kim Phillips diff --git a/MAKEALL b/MAKEALL index 8431b3ea533..816210e44ae 100755 --- a/MAKEALL +++ b/MAKEALL @@ -132,7 +132,8 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ - TQM834x MPC8349EMDS MPC8349ITX MPC8360EMDS \ + MPC832XEMDS MPC8349EMDS MPC8349ITX MPC8349ITXGP \ + MPC8360EMDS sbc8349 TQM834x \ " diff --git a/Makefile b/Makefile index e139d760c52..29180f3ea15 100644 --- a/Makefile +++ b/Makefile @@ -1619,12 +1619,47 @@ r5200_config : unconfig ## MPC83xx Systems ######################################################################### -TQM834x_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x +MPC832XEMDS_config \ +MPC832XEMDS_HOST_33_config \ +MPC832XEMDS_HOST_66_config \ +MPC832XEMDS_SLAVE_config: unconfig + @echo "" >include/config.h ; \ + if [ "$(findstring _HOST_,$@)" ] ; then \ + echo -n "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _SLAVE_,$@)" ] ; then \ + echo "...PCI SLAVE 66M" ; \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "...33M ..." ; \ + echo "#define PCI_33M" >>include/config.h ; \ + fi ; \ + if [ "$(findstring _66_,$@)" ] ; then \ + echo -n "...66M..." ; \ + echo "#define PCI_66M" >>include/config.h ; \ + fi ; + @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds MPC8349EMDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds +MPC8349ITX_config \ +MPC8349ITX_LOWBOOT_config \ +MPC8349ITXGP_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/mpc8349itx + @echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h + @if [ "$(findstring GP,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @if [ "$(findstring LOWBOOT,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx + MPC8360EMDS_config \ MPC8360EMDS_HOST_33_config \ MPC8360EMDS_HOST_66_config \ @@ -1649,8 +1684,12 @@ MPC8360EMDS_SLAVE_config: unconfig fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds -MPC8349ITX_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx +sbc8349_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 + +TQM834x_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x + ######################################################################### ## MPC85xx Systems diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile new file mode 100644 index 00000000000..5ec7a871d4d --- /dev/null +++ b/board/mpc832xemds/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mpc832xemds/config.mk b/board/mpc832xemds/config.mk new file mode 100644 index 00000000000..6c3eca75341 --- /dev/null +++ b/board/mpc832xemds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC832XEMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c new file mode 100644 index 00000000000..772da678f00 --- /dev/null +++ b/board/mpc832xemds/mpc832xemds.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) +#include +#endif +#if defined(CONFIG_SPD_EEPROM) +#include +#else +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* ETH3 */ + {1, 0, 1, 0, 1}, /* TxD0 */ + {1, 1, 1, 0, 1}, /* TxD1 */ + {1, 2, 1, 0, 1}, /* TxD2 */ + {1, 3, 1, 0, 1}, /* TxD3 */ + {1, 9, 1, 0, 1}, /* TxER */ + {1, 12, 1, 0, 1}, /* TxEN */ + {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1}, /* RxD0 */ + {1, 5, 2, 0, 1}, /* RxD1 */ + {1, 6, 2, 0, 1}, /* RxD2 */ + {1, 7, 2, 0, 1}, /* RxD3 */ + {1, 8, 2, 0, 1}, /* RxER */ + {1, 10, 2, 0, 1}, /* RxDV */ + {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1}, /* COL */ + {1, 13, 2, 0, 1}, /* CRS */ + + /* ETH4 */ + {1, 18, 1, 0, 1}, /* TxD0 */ + {1, 19, 1, 0, 1}, /* TxD1 */ + {1, 20, 1, 0, 1}, /* TxD2 */ + {1, 21, 1, 0, 1}, /* TxD3 */ + {1, 27, 1, 0, 1}, /* TxER */ + {1, 30, 1, 0, 1}, /* TxEN */ + {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ + + {1, 22, 2, 0, 1}, /* RxD0 */ + {1, 23, 2, 0, 1}, /* RxD1 */ + {1, 24, 2, 0, 1}, /* RxD2 */ + {1, 25, 2, 0, 1}, /* RxD3 */ + {1, 26, 1, 0, 1}, /* RxER */ + {1, 28, 2, 0, 1}, /* Rx_DV */ + {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ + {1, 29, 2, 0, 1}, /* COL */ + {1, 31, 2, 0, 1}, /* CRS */ + + {3, 4, 3, 0, 2}, /* MDIO */ + {3, 5, 1, 0, 2}, /* MDC */ + + {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ +}; + +int board_early_init_f(void) +{ + volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; + + /* Enable flash write */ + bcsr[9] &= ~0x08; + + return 0; +} + +int fixed_sdram(void); + +long int initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + + msize = fixed_sdram(); + + puts("\n DDR RAM: "); + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CFG_DDR_SIZE != 128) +#warning Currenly any ddr size other than 128 is not supported +#endif + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + __asm__ __volatile__ ("sync"); + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + __asm__ __volatile__ ("sync"); + return msize; +} + +int checkboard(void) +{ + puts("Board: Freescale MPC832XEMDS\n"); + return 0; +} + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c new file mode 100644 index 00000000000..d0a407ae8aa --- /dev/null +++ b/board/mpc832xemds/pci.c @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/* + * PCI Configuration space access support for MPC83xx PCI Bridge + */ +#include +#include +#include +#include +#include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PCI) +#define PCI_FUNCTION_CONFIG 0x44 +#define PCI_FUNCTION_CFG_LOCK 0x20 + +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxemds_config_table[] = { + { + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + pci_cfgfunc_config_device, + {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} + }, + {} +} +#endif +static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxemds_config_table, +#endif + }, +}; + +/********************************************************************** + * pci_init_board() + *********************************************************************/ +void pci_init_board(void) +#ifdef CONFIG_PCISLAVE +{ + u16 reg16; + volatile immap_t *immr; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + immr = (immap_t *) CFG_IMMR; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar0 = 0x0; + pci_ctrl[0].pibar0 = 0x0; + pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_4K; + + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 &= ~PIWAR_EN; + + pci_ctrl[0].pitar2 = 0x0; + pci_ctrl[0].pibar2 = 0x0; + pci_ctrl[0].piebar2 = 0x0; + pci_ctrl[0].piwar2 &= ~PIWAR_EN; + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + reg16 = 0xff; + + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), + PCI_LATENCY_TIMER, 0x80); + + /* + * Unlock configuration lock in PCI function configuration register. + */ + pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, ®16); + reg16 &= ~(PCI_FUNCTION_CFG_LOCK); + pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), + PCI_FUNCTION_CONFIG, reg16); + + printf("Enabled PCI 32bit Agent Mode\n"); +} +#else +{ + volatile immap_t *immr; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + volatile pot83xx_t *pci_pot; + volatile pcictrl83xx_t *pci_ctrl; + volatile pciconf83xx_t *pci_conf; + + u8 val8, orig_i2c_bus; + u16 reg16; + u32 val32; + u32 dev; + + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) & immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + val32 = clk->occr; + udelay(2000); +#if defined(PCI_66M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#elif defined(PCI_33M) + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | + OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; + printf("PCI clock is 33MHz\n"); +#else + clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; + printf("PCI clock is 66MHz\n"); +#endif + udelay(2000); + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = + POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI mmio - non-prefetch mem space */ + pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI IO space */ + pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; + pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = + PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | + PIWAR_IWS_2G; + + /* + * Assign PIB PMC slot to desired PCI bus + */ + + /* Switch temporarily to I2C bus #2 */ + orig_i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); + + val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + asm("eieio"); + + /* Reset to original I2C bus */ + i2c_set_bus_num(orig_i2c_bus); + + /* + * Release PCI RST Output signal + */ + udelay(2000); + pci_ctrl[0].gcr = 1; + udelay(2000); + + hose[0].first_busno = 0; + hose[0].last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose[0].regions + 0, + CFG_PCI_MEM_BASE, + CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose[0].regions + 1, + CFG_PCI_MMIO_BASE, + CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose[0].regions + 2, + CFG_PCI_IO_BASE, + CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose[0].regions + 3, + CFG_PCI_SLV_MEM_LOCAL, + CFG_PCI_SLV_MEM_BUS, + CFG_PCI_SLV_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose[0].region_count = 4; + + pci_setup_indirect(&hose[0], + (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + + pci_register_hose(hose); + + /* + * Write command register + */ + reg16 = 0xff; + dev = PCI_BDF(0, 0, 0); + pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); + + printf("PCI 32bit bus on PMC2 & PMC3\n"); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCISLAVE */ + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = hose[0].first_busno; + p[1] = hose[0].last_busno; + } +} +#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/mpc832xemds/u-boot.lds b/board/mpc832xemds/u-boot.lds new file mode 100644 index 00000000000..937c87a27cd --- /dev/null +++ b/board/mpc832xemds/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 873bdd01cd6..071591ed835 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -119,6 +119,20 @@ int fixed_sdram(void) #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; + im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else im->ddr.csbnds[2].csbnds = 0x0000000f; im->ddr.cs_config[2] = CFG_DDR_CONFIG; @@ -143,6 +157,7 @@ int fixed_sdram(void) im->ddr.sdram_mode = CFG_DDR_MODE; im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif udelay(200); /* enable DDR controller */ @@ -239,7 +254,7 @@ void sdram_init(void) #else void sdram_init(void) { - put("SDRAM on Local Bus is NOT available!\n"); + puts(" SDRAM on Local Bus is NOT available!\n"); } #endif diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk index 2e113118bd7..1901fdc2cef 100644 --- a/board/mpc8349itx/config.mk +++ b/board/mpc8349itx/config.mk @@ -21,10 +21,14 @@ # # -# MPC8349ITX +# MPC8349E-mITX and MPC8349E-mITX-GP # +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE TEXT_BASE = 0xFEF00000 +endif ifneq ($(OBJTREE),$(SRCTREE)) # We are building u-boot in a separate directory, use generated diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 4838e707f09..2b3ded17629 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -134,88 +134,6 @@ volatile static struct pci_controller hose[] = { }; #endif /* CONFIG_PCI */ -/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbc = &immap->lbus; - -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) \ - && !defined(CONFIG_COMPACT_FLASH) - - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; - - puts("\n SDRAM on Local Bus: "); - print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ - - lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ - asm("sync"); - *sdram_addr = 0xff; /*1 time*/ - udelay(100); - *sdram_addr = 0xff; /*2 times*/ - udelay(100); - *sdram_addr = 0xff; /*3 times*/ - udelay(100); - *sdram_addr = 0xff; /*4 times*/ - udelay(100); - *sdram_addr = 0xff; /*5 times*/ - udelay(100); - *sdram_addr = 0xff; /*6 times*/ - udelay(100); - *sdram_addr = 0xff; /*7 times*/ - udelay(100); - *sdram_addr = 0xff; /*8 times*/ - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - -#else - puts("SDRAM on Local Bus is NOT available!\n"); - -#ifdef CFG_BR2_PRELIM - lbc->bank[2].br = CFG_BR2_PRELIM; - lbc->bank[2].or = CFG_OR2_PRELIM; -#endif - -#ifdef CFG_BR3_PRELIM - lbc->bank[3].br = CFG_BR3_PRELIM; - lbc->bank[3].or = CFG_OR3_PRELIM; -#endif -#endif -} - long int initdram(int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; @@ -243,18 +161,18 @@ long int initdram(int board_type) ddr_enable_ecc(msize * 1048576); #endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); puts(" DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ + /* return total bus RAM size(bytes) */ return msize * 1024 * 1024; } int checkboard(void) { +#ifdef CONFIG_MPC8349ITX puts("Board: Freescale MPC8349E-mITX\n"); +#else + puts("Board: Freescale MPC8349E-mITX-GP\n"); +#endif return 0; } @@ -267,6 +185,7 @@ int checkboard(void) */ int misc_init_f(void) { +#ifdef CONFIG_VSC7385 volatile u32 *vsc7385_cpuctrl; /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up @@ -286,6 +205,7 @@ int misc_init_f(void) vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); *vsc7385_cpuctrl |= 0x0c; +#endif #ifdef CONFIG_COMPACT_FLASH /* UPM Table Configuration Code */ @@ -345,7 +265,7 @@ int misc_init_r(void) #ifdef CONFIG_HARD_I2C - unsigned int orig_bus = i2c_get_bus_num();; + unsigned int orig_bus = i2c_get_bus_num(); u8 i2c_data; #ifdef CFG_I2C_RTC_ADDR @@ -355,9 +275,19 @@ int misc_init_r(void) #ifdef CFG_I2C_EEPROM_ADDR static u8 eeprom_data[] = /* HRCW data */ { - 0xaa, 0x55, 0xaa, - 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, - 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, + 0xAA, 0x55, 0xAA, /* Preamble */ + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ + (CFG_HRCW_LOW >> 24) & 0xFF, + (CFG_HRCW_LOW >> 16) & 0xFF, + (CFG_HRCW_LOW >> 8) & 0xFF, + CFG_HRCW_LOW & 0xFF, + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ + (CFG_HRCW_HIGH >> 24) & 0xFF, + (CFG_HRCW_HIGH >> 16) & 0xFF, + (CFG_HRCW_HIGH >> 8) & 0xFF, + CFG_HRCW_HIGH & 0xFF }; u8 data[sizeof(eeprom_data)]; diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c index ddc1047c618..535884cb509 100644 --- a/board/mpc8360emds/mpc8360emds.c +++ b/board/mpc8360emds/mpc8360emds.c @@ -90,11 +90,18 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { int board_early_init_f(void) { - volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; + + u8 *bcsr = (u8 *)CFG_BCSR; + const immap_t *immr = (immap_t *)CFG_IMMR; /* Enable flash write */ bcsr[0xa] &= ~0x04; + /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */ + if (immr->sysconf.spridr == SPR_8360_REV20 || + immr->sysconf.spridr == SPR_8360E_REV20) + bcsr[0xe] = 0x30; + return 0; } @@ -158,6 +165,20 @@ int fixed_sdram(void) #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else im->ddr.csbnds[0].csbnds = 0x00000007; im->ddr.csbnds[1].csbnds = 0x0008000f; @@ -170,6 +191,7 @@ int fixed_sdram(void) im->ddr.sdram_mode = CFG_DDR_MODE; im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c index 15a48dcf407..67cd70981ca 100644 --- a/board/mpc8360emds/pci.c +++ b/board/mpc8360emds/pci.c @@ -18,6 +18,9 @@ #include #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif #include diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile new file mode 100644 index 00000000000..02cf569b5b8 --- /dev/null +++ b/board/sbc8349/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (c) 2006 Wind River Systems, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sbc8349/config.mk b/board/sbc8349/config.mk new file mode 100644 index 00000000000..05fa5a07d57 --- /dev/null +++ b/board/sbc8349/config.mk @@ -0,0 +1,27 @@ +# +# Copyright (c) 2006 Wind River Systems, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# SBC8349E +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c new file mode 100644 index 00000000000..eadf230983d --- /dev/null +++ b/board/sbc8349/pci.c @@ -0,0 +1,348 @@ +/* + * pci.c -- WindRiver SBC8349 PCI board support. + * Copyright (c) 2006 Wind River Systems, Inc. + * + * Based on MPC8349 PCI support but w/o PIB related code. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_PCI + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8349emds_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } + }, + {} +}; +#endif + +static struct pci_controller pci_hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + } +}; + +/************************************************************************** + * pci_init_board() + * + * NOTICE: PCI2 is not supported. There is only one + * physical PCI slot on the board. + * + */ +void +pci_init_board(void) +{ + volatile immap_t * immr; + volatile clk83xx_t * clk; + volatile law83xx_t * pci_law; + volatile pot83xx_t * pci_pot; + volatile pcictrl83xx_t * pci_ctrl; + volatile pciconf83xx_t * pci_conf; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller * hose; + + immr = (immap_t *)CFG_IMMR; + clk = (clk83xx_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci_hose[0]; + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + + reg32 = clk->occr; + udelay(2000); + clk->occr = 0xff000000; + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + +#ifdef CONFIG_MPC83XX_PCI2 + pci_ctrl[1].gcr = 0; + udelay(2000); + pci_ctrl[1].gcr = 1; +#endif + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; ++i) + udelay (1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI1 mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MMIO_BASE, + CFG_PCI1_MMIO_PHYS, + CFG_PCI1_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMR+0x8300), + (CFG_IMMR+0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC83XX_PCI2 + hose = &pci_hose[1]; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI2 mem space - prefetch */ + pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI2 IO space */ + pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI2 mmio - non-prefetch mem space */ + pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[1].pitar1 = 0x0; + pci_ctrl[1].pibar1 = 0x0; + pci_ctrl[1].piebar1 = 0x0; + pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MMIO_BASE, + CFG_PCI2_MMIO_PHYS, + CFG_PCI2_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMR+0x8380), + (CFG_IMMR+0x8384)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +#endif + +} + +#ifdef CONFIG_OF_FLAT_TREE +void +ft_pci_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[0].first_busno; + p[1] = pci_hose[0].last_busno; + } + +#ifdef CONFIG_MPC83XX_PCI2 + p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); + if (p != NULL) { + p[0] = pci_hose[1].first_busno; + p[1] = pci_hose[1].last_busno; + } +#endif +} +#endif /* CONFIG_OF_FLAT_TREE */ +#endif /* CONFIG_PCI */ diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c new file mode 100644 index 00000000000..4cd447e097f --- /dev/null +++ b/board/sbc8349/sbc8349.c @@ -0,0 +1,585 @@ +/* + * sbc8349.c -- WindRiver SBC8349 board support. + * Copyright (c) 2006-2007 Wind River Systems, Inc. + * + * Paul Gortmaker + * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_SPD_EEPROM) +#include +#endif +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + +int fixed_sdram(void); +void sdram_init(void); + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) +void ddr_enable_ecc(unsigned int dram_size); +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f (void) +{ + return 0; +} +#endif + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + puts("Initializing\n"); + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size>>1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + +#if (CFG_DDR_SIZE != 256) +#warning Currently any ddr size other than 256 is not supported +#endif + im->ddr.csbnds[2].csbnds = 0x0000000f; + im->ddr.cs_config[2] = CFG_DDR_CONFIG; + + /* currently we use only one CS, so disable the other banks */ + im->ddr.cs_config[0] = 0; + im->ddr.cs_config[1] = 0; + im->ddr.cs_config[3] = 0; + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + + im->ddr.sdram_cfg = + SDRAM_CFG_SREN +#if defined(CONFIG_DDR_2T_TIMING) + | SDRAM_CFG_2T_EN +#endif + | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; +#if defined (CONFIG_DDR_32BIT) + /* for 32-bit mode burst length is 8 */ + im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); +#endif + im->ddr.sdram_mode = CFG_DDR_MODE; + + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + return msize; +} +#endif/*!CFG_SPD_EEPROM*/ + + +int checkboard (void) +{ + puts("Board: Wind River SBC834x\n"); + return 0; +} + +/* + * if board is fitted with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile lbus83xx_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /* setup mtrpt, lsrt and lbcr for LB bus */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + asm("sync"); + /*1 times*/ + *sdram_addr = 0xff; + udelay(100); + /*2 times*/ + *sdram_addr = 0xff; + udelay(100); + /*3 times*/ + *sdram_addr = 0xff; + udelay(100); + /*4 times*/ + *sdram_addr = 0xff; + udelay(100); + /*5 times*/ + *sdram_addr = 0xff; + udelay(100); + /*6 times*/ + *sdram_addr = 0xff; + udelay(100); + /*7 times*/ + *sdram_addr = 0xff; + udelay(100); + /*8 times*/ + *sdram_addr = 0xff; + udelay(100); + + /* 0x58636733; mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void sdram_init(void) +{ + puts(" SDRAM on Local Bus: Disabled in config\n"); +} +#endif + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) +/* + * ECC user commands + */ +void ecc_print_status(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ddr83xx_t *ddr = &immap->ddr; + + printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); + + /* Interrupts */ + printf("Memory Error Interrupt Enable:\n"); + printf(" Multiple-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); + printf(" Single-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); + printf(" Memory Select Error Interrupt Enable: %d\n\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); + + /* Error disable */ + printf("Memory Error Disable:\n"); + printf(" Multiple-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); + printf(" Sinle-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); + printf(" Memory Select Error Disable: %d\n\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); + + /* Error injection */ + printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", + ddr->data_err_inject_hi, ddr->data_err_inject_lo); + + printf("Memory Data Path Error Injection Mask ECC:\n"); + printf(" ECC Mirror Byte: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); + printf(" ECC Injection Enable: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); + printf(" ECC Error Injection Mask: 0x%02x\n\n", + ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); + + /* SBE counter/threshold */ + printf("Memory Single-Bit Error Management (0..255):\n"); + printf(" Single-Bit Error Threshold: %d\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); + printf(" Single-Bit Error Counter: %d\n\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); + + /* Error detect */ + printf("Memory Error Detect:\n"); + printf(" Multiple Memory Errors: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); + printf(" Multiple-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); + printf(" Single-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); + printf(" Memory Select Error: %d\n\n", + (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); + + /* Capture data */ + printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); + printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", + ddr->capture_data_hi, ddr->capture_data_lo); + printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", + ddr->capture_ecc & CAPTURE_ECC_ECE); + + printf("Memory Error Attributes Capture:\n"); + printf(" Data Beat Number: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); + printf(" Transaction Size: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); + printf(" Transaction Source: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); + printf(" Transaction Type: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); + printf(" Error Information Valid: %d\n\n", + ddr->capture_attributes & ECC_CAPT_ATTR_VLD); +} + +int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ddr83xx_t *ddr = &immap->ddr; + volatile u32 val; + u64 *addr, count, val64; + register u64 *i; + + if (argc > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (argc == 2) { + if (strcmp(argv[1], "status") == 0) { + ecc_print_status(); + return 0; + } else if (strcmp(argv[1], "captureclear") == 0) { + ddr->capture_address = 0; + ddr->capture_data_hi = 0; + ddr->capture_data_lo = 0; + ddr->capture_ecc = 0; + ddr->capture_attributes = 0; + return 0; + } + } + + if (argc == 3) { + if (strcmp(argv[1], "sbecnt") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBEC_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "sbethr") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBET_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "errdisable") == 0) { + val = ddr->err_disable; + + if (strcmp(argv[2], "+sbe") == 0) { + val |= ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "+mbe") == 0) { + val |= ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "+mse") == 0) { + val |= ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "+all") == 0) { + val |= (ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else if (strcmp(argv[2], "-sbe") == 0) { + val &= ~ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "-mbe") == 0) { + val &= ~ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "-mse") == 0) { + val &= ~ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "-all") == 0) { + val &= ~(ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else { + printf("Incorrect err_disable field\n"); + return 1; + } + + ddr->err_disable = val; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + return 0; + } else if (strcmp(argv[1], "errdetectclr") == 0) { + val = ddr->err_detect; + + if (strcmp(argv[2], "mme") == 0) { + val |= ECC_ERROR_DETECT_MME; + } else if (strcmp(argv[2], "sbe") == 0) { + val |= ECC_ERROR_DETECT_SBE; + } else if (strcmp(argv[2], "mbe") == 0) { + val |= ECC_ERROR_DETECT_MBE; + } else if (strcmp(argv[2], "mse") == 0) { + val |= ECC_ERROR_DETECT_MSE; + } else if (strcmp(argv[2], "all") == 0) { + val |= (ECC_ERROR_DETECT_MME | + ECC_ERROR_DETECT_MBE | + ECC_ERROR_DETECT_SBE | + ECC_ERROR_DETECT_MSE); + } else { + printf("Incorrect err_detect field\n"); + return 1; + } + + ddr->err_detect = val; + return 0; + } else if (strcmp(argv[1], "injectdatahi") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_hi = val; + return 0; + } else if (strcmp(argv[1], "injectdatalo") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_lo = val; + return 0; + } else if (strcmp(argv[1], "injectecc") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + if (val > 0xff) { + printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); + return 1; + } + val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); + + ddr->ecc_err_inject = val; + return 0; + } else if (strcmp(argv[1], "inject") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EIEN; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EIEN; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + return 0; + } else if (strcmp(argv[1], "mirror") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EMB; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EMB; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + return 0; + } + } + + if (argc == 4) { + if (strcmp(argv[1], "test") == 0) { + addr = (u64 *)simple_strtoul(argv[2], NULL, 16); + count = simple_strtoul(argv[3], NULL, 16); + + if ((u32)addr % 8) { + printf("Address not alligned on double word boundary\n"); + return 1; + } + + disable_interrupts(); + icache_disable(); + + for (i = addr; i < addr + count; i++) { + /* enable injects */ + ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* write memory location injecting errors */ + *i = 0x1122334455667788ULL; + __asm__ __volatile__ ("sync"); + + /* disable injects */ + ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* read data, this generates ECC error */ + val64 = *i; + __asm__ __volatile__ ("sync"); + + /* disable errors for ECC */ + ddr->err_disable |= ~ECC_ERROR_ENABLE; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* re-initialize memory, write the location again + * NOT injecting errors this time */ + *i = 0xcafecafecafecafeULL; + __asm__ __volatile__ ("sync"); + + /* enable errors for ECC */ + ddr->err_disable &= ECC_ERROR_ENABLE; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + } + + icache_enable(); + enable_interrupts(); + + return 0; + } + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + ecc, 4, 0, do_ecc, + "ecc - support for DDR ECC features\n", + "status - print out status info\n" + "ecc captureclear - clear capture regs data\n" + "ecc sbecnt - set Single-Bit Error counter\n" + "ecc sbethr - set Single-Bit Threshold\n" + "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" + " [-|+]sbe - Single-Bit Error\n" + " [-|+]mbe - Multiple-Bit Error\n" + " [-|+]mse - Memory Select Error\n" + " [-|+]all - all errors\n" + "ecc errdetectclr - clear Memory Error Detect, flag:\n" + " mme - Multiple Memory Errors\n" + " sbe - Single-Bit Error\n" + " mbe - Multiple-Bit Error\n" + " mse - Memory Select Error\n" + " all - all errors\n" + "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" + "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" + "ecc injectecc - set ECC Error Injection Mask\n" + "ecc inject - enable/disable error injection\n" + "ecc mirror - enable/disable mirror byte\n" + "ecc test - test mem region:\n" + " - enables injects\n" + " - writes pattern injecting errors\n" + " - disables injects\n" + " - reads pattern back, generates error\n" + " - re-inits memory" +); +#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + + p = ft_get_prop(blob, "/memory/reg", &len); + if (p != NULL) { + *p++ = cpu_to_be32(bd->bi_memstart); + *p = cpu_to_be32(bd->bi_memsize); + } +} +#endif diff --git a/board/sbc8349/u-boot.lds b/board/sbc8349/u-boot.lds new file mode 100644 index 00000000000..e32c0754cf6 --- /dev/null +++ b/board/sbc8349/u-boot.lds @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2006 Wind River Systems, Inc. + * u-boot.lds for WindRiver SBC8349. + * + * Based on the MPC8349 u-boot.lds + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c index 36d901f0942..9c35e22c8e1 100644 --- a/board/tqm834x/tqm834x.c +++ b/board/tqm834x/tqm834x.c @@ -148,14 +148,14 @@ int checkboard (void) u32 w, f; immr = (immap_t *)CFG_IMMR; - if (!(immr->reset.rcwh & RCWH_PCIHOST)) { + if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { printf("PCI: NOT in host mode..?!\n"); return 0; } /* get bus width */ w = 32; - if (immr->reset.rcwh & RCWH_PCI64) + if (immr->reset.rcwh & HRCWH_64_BIT_PCI) w = 64; /* get clock */ diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 1b5107881ed..e4bc4052db5 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -56,49 +56,78 @@ int checkcpu(void) switch(spridr) { case SPR_8349E_REV10: case SPR_8349E_REV11: + case SPR_8349E_REV31: puts("MPC8349E, "); break; case SPR_8349_REV10: case SPR_8349_REV11: + case SPR_8349_REV31: puts("MPC8349, "); break; case SPR_8347E_REV10_TBGA: case SPR_8347E_REV11_TBGA: + case SPR_8347E_REV31_TBGA: case SPR_8347E_REV10_PBGA: case SPR_8347E_REV11_PBGA: + case SPR_8347E_REV31_PBGA: puts("MPC8347E, "); break; case SPR_8347_REV10_TBGA: case SPR_8347_REV11_TBGA: + case SPR_8347_REV31_TBGA: case SPR_8347_REV10_PBGA: case SPR_8347_REV11_PBGA: + case SPR_8347_REV31_PBGA: puts("MPC8347, "); break; case SPR_8343E_REV10: case SPR_8343E_REV11: + case SPR_8343E_REV31: puts("MPC8343E, "); break; case SPR_8343_REV10: case SPR_8343_REV11: + case SPR_8343_REV31: puts("MPC8343, "); break; case SPR_8360E_REV10: case SPR_8360E_REV11: case SPR_8360E_REV12: + case SPR_8360E_REV20: puts("MPC8360E, "); break; case SPR_8360_REV10: case SPR_8360_REV11: case SPR_8360_REV12: + case SPR_8360_REV20: puts("MPC8360, "); break; + case SPR_8323E_REV10: + case SPR_8323E_REV11: + puts("MPC8323E, "); + break; + case SPR_8323_REV10: + case SPR_8323_REV11: + puts("MPC8323, "); + break; + case SPR_8321E_REV10: + case SPR_8321E_REV11: + puts("MPC8321E, "); + break; + case SPR_8321_REV10: + case SPR_8321_REV11: + puts("MPC8321, "); + break; default: - puts("Rev: Unknown\n"); - return -1; /* Not sure what this is */ + puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n"); + return 0; } -#if defined(CONFIG_MPC8349) - printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock)); +#if defined(CONFIG_MPC834X) + /* Multiple revisons of 834x processors may have the same SPRIDR value. + * So use PVR to identify the revision number. + */ + printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock)); #else printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock)); #endif @@ -250,7 +279,6 @@ unsigned long get_tbclk(void) #if defined(CONFIG_WATCHDOG) void watchdog_reset (void) { -#ifdef CONFIG_MPC834X int re_enable = disable_interrupts(); /* Reset the 83xx watchdog */ @@ -260,9 +288,6 @@ void watchdog_reset (void) if (re_enable) enable_interrupts (); -#else - hang(); -#endif } #endif @@ -292,13 +317,63 @@ ft_cpu_setup(void *blob, bd_t *bd) *p = cpu_to_be32(clock); #ifdef CONFIG_MPC83XX_TSEC1 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); + if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); #endif #ifdef CONFIG_MPC83XX_TSEC2 - p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); + if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet1addr, 6); +#endif + +#ifdef CONFIG_UEC_ETH1 +#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */ + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); +#elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */ + p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); +#endif +#endif + +#ifdef CONFIG_UEC_ETH2 +#if CFG_UEC2_UCC_NUM == 1 /* UCC2 */ + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet1addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet1addr, 6); +#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */ + p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet1addr, 6); + + p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enet1addr, 6); +#endif #endif } #endif diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index e5725fb91d9..3ac91619c4b 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -69,31 +69,53 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_ACR_PIPE_DEP /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | + (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); #endif #ifdef CFG_SPCR_TSEC1EP /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT); + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); #endif #ifdef CFG_SPCR_TSEC2EP /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT); + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); #endif +#ifdef CONFIG_MPC834X #ifdef CFG_SCCR_TSEC1CM /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT); + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); #endif #ifdef CFG_SCCR_TSEC2CM /* TSEC2 & I2C1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT); + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); +#endif +#ifdef CFG_SCCR_USBMPHCM + /* USB MPH clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); +#endif +#endif /* CONFIG_MPC834X */ + +#ifdef CFG_SCCR_PCICM + /* PCI & DMA clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT); +#endif + +#ifdef CFG_SCCR_USBDRCM + /* USB DR clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); +#endif + +#ifdef CFG_SCCR_ENCCM + /* Encryption clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT); #endif #ifdef CFG_ACR_RPTCNT /* Arbiter repeat count */ - im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT)); + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); #endif /* RSR - Reset Status Register - clear all status (4.6.1.3) */ @@ -119,6 +141,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CFG_SICRL im->sysconf.sicrl = CFG_SICRL; #endif + /* DDR control driver register */ +#ifdef CFG_DDRCDR + im->sysconf.ddrcdr = CFG_DDRCDR; +#endif + #ifdef CONFIG_QE /* Config QE ioports */ config_qe_ioports(); @@ -202,12 +229,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; #endif #ifdef CFG_GPIO1_PRELIM - im->pgio[0].dir = CFG_GPIO1_DIR; - im->pgio[0].dat = CFG_GPIO1_DAT; + im->gpio[0].dir = CFG_GPIO1_DIR; + im->gpio[0].dat = CFG_GPIO1_DAT; #endif #ifdef CFG_GPIO2_PRELIM - im->pgio[1].dir = CFG_GPIO2_DIR; - im->pgio[1].dat = CFG_GPIO2_DAT; + im->gpio[1].dir = CFG_GPIO2_DIR; + im->gpio[1].dat = CFG_GPIO2_DAT; #endif } diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index ebe34871120..8b3937aa9b9 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -35,7 +35,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_1bit_mask; u32 tmp_val; volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 0d93f2e1ea4..d9b8753ca09 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -106,16 +106,29 @@ long int spd_sdram() volatile ddr83xx_t *ddr = &immap->ddr; volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; spd_eeprom_t spd; + unsigned int n_ranks; + unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned char twr_clk, twtr_clk; + unsigned char sdram_type; unsigned int memsize; unsigned int law_size; unsigned char caslat, caslat_ctrl; + unsigned int trfc, trfc_clk, trfc_low, trfc_high; + unsigned int trcd_clk, trtp_clk; + unsigned char cke_min_clk; + unsigned char add_lat, wr_lat; + unsigned char wr_data_delay; + unsigned char four_act; + unsigned char cpo; unsigned char burstlen; + unsigned char odt_cfg, mode_odt_enable; unsigned int max_bus_clk; unsigned int max_data_rate, effective_data_rate; unsigned int ddrc_clk; unsigned int refresh_clk; - unsigned sdram_cfg; + unsigned int sdram_cfg; unsigned int ddrc_ecc_enable; + unsigned int pvr = get_pvr(); /* Read SPD parameters with I2C */ CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); @@ -123,19 +136,25 @@ long int spd_sdram() spd_debug(&spd); #endif /* Check the memory type */ - if (spd.mem_type != SPD_MEMTYPE_DDR) { + if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { printf("DDR: Module mem type is %02X\n", spd.mem_type); return 0; } /* Check the number of physical bank */ - if (spd.nrows > 2) { - printf("DDR: The number of physical bank is %02X\n", spd.nrows); + if (spd.mem_type == SPD_MEMTYPE_DDR) { + n_ranks = spd.nrows; + } else { + n_ranks = (spd.nrows & 0x7) + 1; + } + + if (n_ranks > 2) { + printf("DDR: The number of physical bank is %02X\n", n_ranks); return 0; } /* Check if the number of row of the module is in the range of DDRC */ - if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { + if (spd.nrow_addr < 12 || spd.nrow_addr > 15) { printf("DDR: Row number is out of range of DDRC, row=%02X\n", spd.nrow_addr); return 0; @@ -147,20 +166,43 @@ long int spd_sdram() spd.ncol_addr); return 0; } + +#ifdef CFG_DDRCDR_VALUE + /* + * Adjust DDR II IO voltage biasing. It just makes it work. + */ + if(spd.mem_type == SPD_MEMTYPE_DDR2) { + immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + } +#endif + + /* + * ODT configuration recommendation from DDR Controller Chapter. + */ + odt_rd_cfg = 0; /* Never assert ODT */ + odt_wr_cfg = 0; /* Never assert ODT */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + odt_wr_cfg = 1; /* Assert ODT on writes to CSn */ + } + /* Setup DDR chip select register */ #ifdef CFG_83XX_DDR_USES_CS0 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[0] = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); - if (spd.nrows == 2) { + if (n_ranks == 2) { ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) | ((banksize(spd.row_dens) >> 23) - 1) ); ddr->cs_config[1] = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr-12) << 8 | (spd.ncol_addr-8) ); debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); @@ -170,16 +212,20 @@ long int spd_sdram() #else ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[2] = ( 1 << 31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); - if (spd.nrows == 2) { + if (n_ranks == 2) { ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) | ((banksize(spd.row_dens) >> 23) - 1) ); ddr->cs_config[3] = ( 1<<31 + | (odt_rd_cfg << 20) + | (odt_wr_cfg << 16) | (spd.nrow_addr-12) << 8 | (spd.ncol_addr-8) ); debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); @@ -187,15 +233,10 @@ long int spd_sdram() } #endif - if (spd.mem_type != 0x07) { - puts("No DDR module found!\n"); - return 0; - } - /* * Figure out memory size in Megabytes. */ - memsize = spd.nrows * banksize(spd.row_dens) / 0x100000; + memsize = n_ranks * banksize(spd.row_dens) / 0x100000; /* * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. @@ -215,24 +256,32 @@ long int spd_sdram() * in the spd.cas_lat field. Translate it to a DDR * controller field value: * - * CAS Lat DDR I Ctrl - * Clocks SPD Bit Value - * -------+--------+--------- - * 1.0 0 001 - * 1.5 1 010 - * 2.0 2 011 - * 2.5 3 100 - * 3.0 4 101 - * 3.5 5 110 - * 4.0 6 111 + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 6 4 0111 + * 4.5 1000 + * 5.0 5 1001 */ caslat = __ilog2(spd.cas_lat); - - if (caslat > 6 ) { - printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", - spd.cas_lat); + if ((spd.mem_type == SPD_MEMTYPE_DDR) + && (caslat > 6)) { + printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); + return 0; + } else if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (caslat < 2 || caslat > 5)) { + printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", + spd.cas_lat); return 0; } + debug("DDR: caslat SPD bit is %d\n", caslat); + max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f)); max_data_rate = max_bus_clk * 2; @@ -240,10 +289,11 @@ long int spd_sdram() debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); ddrc_clk = gd->ddr_clk / 1000000; + effective_data_rate = 0; - if (max_data_rate >= 390) { /* it is DDR 400 */ - if (ddrc_clk <= 410 && ddrc_clk > 350) { - /* DDR controller clk at 350~410 */ + if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ + if (ddrc_clk <= 460 && ddrc_clk > 350) { + /* DDR controller clk at 350~460 */ effective_data_rate = 400; /* 5ns */ caslat = caslat; } else if (ddrc_clk <= 350 && ddrc_clk > 280) { @@ -258,16 +308,16 @@ long int spd_sdram() effective_data_rate = 266; /* 7.5ns */ if (spd.clk_cycle3 == 0x75) caslat = caslat - 2; - else if (spd.clk_cycle2 == 0x60) + else if (spd.clk_cycle2 == 0x75) caslat = caslat - 1; else caslat = caslat; } else if (ddrc_clk <= 230 && ddrc_clk > 90) { /* DDR controller clk at 90~230 */ effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle3 == 0x75) + if (spd.clk_cycle3 == 0xa0) caslat = caslat - 2; - else if (spd.clk_cycle2 == 0x60) + else if (spd.clk_cycle2 == 0xa0) caslat = caslat - 1; else caslat = caslat; @@ -289,7 +339,7 @@ long int spd_sdram() effective_data_rate = 200; /* 10ns */ if (spd.clk_cycle3 == 0xa0) caslat = caslat - 2; - else if (spd.clk_cycle2 == 0x75) + else if (spd.clk_cycle2 == 0xa0) caslat = caslat - 1; else caslat = caslat; @@ -330,41 +380,197 @@ long int spd_sdram() * Errata DDR6 work around: input enable 2 cycles earlier. * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. */ - if (caslat == 2) - ddr->debug_reg = 0x201c0000; /* CL=2 */ - else if (caslat == 3) - ddr->debug_reg = 0x202c0000; /* CL=2.5 */ - else if (caslat == 4) - ddr->debug_reg = 0x202c0000; /* CL=3.0 */ + if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){ + if (caslat == 2) + ddr->debug_reg = 0x201c0000; /* CL=2 */ + else if (caslat == 3) + ddr->debug_reg = 0x202c0000; /* CL=2.5 */ + else if (caslat == 4) + ddr->debug_reg = 0x202c0000; /* CL=3.0 */ - __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("sync"); - debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); + debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); + } /* - * note: caslat must also be programmed into ddr->sdram_mode - * register. - * - * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, - * use conservative value here. + * Convert caslat clocks to DDR controller value. + * Force caslat_ctrl to be DDR Controller field-sized. */ - caslat_ctrl = (caslat + 1) & 0x07; /* see as above */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + caslat_ctrl = (caslat + 1) & 0x07; + } else { + caslat_ctrl = (2 * caslat - 1) & 0x0f; + } + + debug("DDR: effective data rate is %d MHz\n", effective_data_rate); + debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", + caslat, caslat_ctrl); + + /* + * Timing Config 0. + * Avoid writing for DDR I. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + unsigned char taxpd_clk = 8; /* By the book. */ + unsigned char tmrd_clk = 2; /* By the book. */ + unsigned char act_pd_exit = 2; /* Empirical? */ + unsigned char pre_pd_exit = 6; /* Empirical? */ + + ddr->timing_cfg_0 = (0 + | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ + | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ + ); + debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); + } + + /* + * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value. + * For DDR II, they are bytes 36 and 37, in quarter nanos. + */ + + if (spd.mem_type == SPD_MEMTYPE_DDR) { + twr_clk = 3; /* Clocks */ + twtr_clk = 1; /* Clocks */ + } else { + twr_clk = picos_to_clk(spd.twr * 250); + twtr_clk = picos_to_clk(spd.twtr * 250); + } + + /* + * Calculate Trfc, in picos. + * DDR I: Byte 42 straight up in ns. + * DDR II: Byte 40 and 42 swizzled some, in ns. + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + trfc = spd.trfc * 1000; /* up to ps */ + } else { + unsigned int byte40_table_ps[8] = { + 0, + 250, + 330, + 500, + 660, + 750, + 0, + 0 + }; + + trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 + + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; + } + trfc_clk = picos_to_clk(trfc); + + /* + * Trcd, Byte 29, from quarter nanos to ps and clocks. + */ + trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; + + /* + * Convert trfc_clk to DDR controller fields. DDR I should + * fit in the REFREC field (16-19) of TIMING_CFG_1, but the + * 83xx controller has an extended REFREC field of three bits. + * The controller automatically adds 8 clocks to this value, + * so preadjust it down 8 first before splitting it up. + */ + trfc_low = (trfc_clk - 8) & 0xf; + trfc_high = ((trfc_clk - 8) >> 4) & 0x3; ddr->timing_cfg_1 = - (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | - ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | - ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | - ((caslat_ctrl & 0x07) << 16 ) | - (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) | - ( 0x300 ) | - ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); + (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */ + ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */ + (trcd_clk << 20 ) | /* ACTTORW */ + (caslat_ctrl << 16 ) | /* CASLAT */ + (trfc_low << 12 ) | /* REFEC */ + ((twr_clk & 0x07) << 8) | /* WRRREC */ + ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */ + ((twtr_clk & 0x07) << 0) /* WRTORD */ + ); - ddr->timing_cfg_2 = 0x00000800; + /* + * Additive Latency + * For DDR I, 0. + * For DDR II, with ODT enabled, use "a value" less than ACTTORW, + * which comes from Trcd, and also note that: + * add_lat + caslat must be >= 4 + */ + add_lat = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2 + && (odt_wr_cfg || odt_rd_cfg) + && (caslat < 4)) { + add_lat = trcd_clk - 1; + if ((add_lat + caslat) < 4) { + add_lat = 0; + } + } + + /* + * Write Data Delay + * Historically 0x2 == 4/8 clock delay. + * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. + */ + wr_data_delay = 2; + + /* + * Write Latency + * Read to Precharge + * Minimum CKE Pulse Width. + * Four Activate Window + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; + + trtp_clk = 2; /* By the book. */ + cke_min_clk = 1; /* By the book. */ + four_act = 1; /* By the book. */ + + } else { + wr_lat = caslat - 1; + + /* Convert SPD value from quarter nanos to picos. */ + trtp_clk = picos_to_clk(spd.trtp * 250); + + cke_min_clk = 3; /* By the book. */ + four_act = picos_to_clk(37500); /* By the book. 1k pages? */ + } + + /* + * Empirically set ~MCAS-to-preamble override for DDR 2. + * Your milage will vary. + */ + cpo = 0; + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (effective_data_rate == 266 || effective_data_rate == 333) { + cpo = 0x7; /* READ_LAT + 5/4 */ + } else if (effective_data_rate == 400) { + cpo = 0x9; /* READ_LAT + 7/4 */ + } else { + /* Automatic calibration */ + cpo = 0x1f; + } + } + + ddr->timing_cfg_2 = (0 + | ((add_lat & 0x7) << 28) /* ADD_LAT */ + | ((cpo & 0x1f) << 23) /* CPO */ + | ((wr_lat & 0x7) << 19) /* WR_LAT */ + | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ + | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ + | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ + | ((four_act & 0x1f) << 0) /* FOUR_ACT */ + ); debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); - /* Setup init value, but not enable */ - ddr->sdram_cfg = 0x42000000; /* Check DIMM data bus width */ if (spd.dataw_lsb == 0x20) { @@ -384,7 +590,8 @@ long int spd_sdram() /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, Burst type is sequential */ - switch (caslat) { + if (spd.mem_type == SPD_MEMTYPE_DDR) { + switch (caslat) { case 1: ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ break; @@ -400,9 +607,36 @@ long int spd_sdram() default: printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n"); return 0; + } + } else { + mode_odt_enable = 0x0; /* Default disabled */ + if (odt_wr_cfg || odt_rd_cfg) { + /* + * Bits 6 and 2 in Extended MRS(1) + * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. + * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. + */ + mode_odt_enable = 0x40; /* 150 Ohm */ + } + + ddr->sdram_mode = + (0 + | (1 << (16 + 10)) /* DQS Differential disable */ + | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ + | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ + | ((twr_clk >> 1) << 9) /* Write Recovery Autopre */ + | (caslat << 4) /* caslat */ + | (burstlen << 0) /* Burst length */ + ); } debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); + /* + * Clear EMRS2 and EMRS3. + */ + ddr->sdram_mode2 = 0; + debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2); + switch (spd.refresh) { case 0x00: case 0x80: @@ -440,10 +674,31 @@ long int spd_sdram() ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); + /* + * SDRAM Cfg 2 + */ + odt_cfg = 0; + if (odt_rd_cfg | odt_wr_cfg) { + odt_cfg = 0x2; /* ODT to IOs during reads */ + } + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + ddr->sdram_cfg2 = (0 + | (0 << 26) /* True DQS */ + | (odt_cfg << 21) /* ODT only read */ + | (1 << 12) /* 1 refresh at a time */ + ); + + debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); + } + +#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ + ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; +#else /* SS_EN = 0, source synchronous disable * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd */ ddr->sdram_clk_cntl = 0x00000000; +#endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); asm("sync;isync"); @@ -458,11 +713,22 @@ long int spd_sdram() * * sdram_cfg[0] = 1 (ddr sdram logic enable) * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) + * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) + * 010 DDR 1 SDRAM + * 011 DDR 2 SDRAM * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode) * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) */ - sdram_cfg = 0xC2000000; + if (spd.mem_type == SPD_MEMTYPE_DDR) + sdram_type = 2; + else + sdram_type = 3; + + sdram_cfg = (0 + | (1 << 31) /* DDR enable */ + | (1 << 30) /* Self refresh */ + | (sdram_type << 24) /* SDRAM type */ + ); /* sdram_cfg[3] = RD_EN - registered DIMM enable */ if (spd.mod_attr & 0x02) diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 7e53b1e6061..c75993059e0 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -99,7 +99,7 @@ int get_clocks(void) u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; @@ -107,15 +107,19 @@ int get_clocks(void) #endif u32 core_clk; u32 i2c1_clk; +#if !defined(CONFIG_MPC832X) u32 i2c2_clk; +#endif u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; u32 ddr_clk; -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) + u32 ddr_sec_clk; +#endif +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) u32 qepmf; u32 qepdf; - u32 ddr_sec_clk; u32 qe_clk; u32 brg_clk; #endif @@ -139,12 +143,12 @@ int get_clocks(void) #endif } - spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); + spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); csb_clk = pci_sync_in * (1 + clkin_div) * spmf; sccr = im->clk.sccr; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -227,10 +231,12 @@ int get_clocks(void) return -9; } #endif -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) i2c1_clk = csb_clk; #endif +#if !defined(CONFIG_MPC832X) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ +#endif switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { case 0: @@ -249,12 +255,9 @@ int get_clocks(void) /* unkown SCCR_ENCCM value */ return -6; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) + lbiu_clk = csb_clk * - (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); -#else -#error Unknown MPC83xx chip -#endif + (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; switch (lcrr) { case 2: @@ -266,16 +269,13 @@ int get_clocks(void) /* unknown lcrr */ return -10; } -#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) + ddr_clk = csb_clk * - (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); - corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; -#if defined (CONFIG_MPC8360) + (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); + corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; +#if defined(CONFIG_MPC8360) ddr_sec_clk = csb_clk * (1 + - ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); -#endif -#else -#error Unknown MPC83xx chip + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); #endif corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); @@ -306,15 +306,15 @@ int get_clocks(void) return -12; } -#if defined (CONFIG_MPC8360) - qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT; - qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT; +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; + qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); brg_clk = qe_clk / 2; #endif gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC8349) +#if defined(CONFIG_MPC834X) gd->tsec1_clk = tsec1_clk; gd->tsec2_clk = tsec2_clk; gd->usbmph_clk = usbmph_clk; @@ -322,13 +322,17 @@ int get_clocks(void) #endif gd->core_clk = core_clk; gd->i2c1_clk = i2c1_clk; +#if !defined(CONFIG_MPC832X) gd->i2c2_clk = i2c2_clk; +#endif gd->enc_clk = enc_clk; gd->lbiu_clk = lbiu_clk; gd->lclk_clk = lclk_clk; gd->ddr_clk = ddr_clk; -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) gd->ddr_sec_clk = ddr_sec_clk; +#endif +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif @@ -352,19 +356,22 @@ int print_clock_conf(void) printf("Clock configuration:\n"); printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); printf(" Core: %4d MHz\n", gd->core_clk / 1000000); -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) printf(" QE: %4d MHz\n", gd->qe_clk / 1000000); + printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000); #endif printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000); printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000); printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000); -#if defined (CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000); #endif printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); +#if !defined(CONFIG_MPC832X) printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); -#if defined(CONFIG_MPC8349) +#endif +#if defined(CONFIG_MPC834X) printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 0f27bb61f8c..6ee9ec96c97 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -77,19 +77,11 @@ END_GOT /* - * Version string - must be in data segment because MPC83xx uses the - * first 256 bytes for the Hard Reset Configuration Word table (see - * below). Similarly, can't have the U-Boot Magic Number as the first - * thing in the image - don't know how this will affect the image tools, - * but I guess I'll find out soon. + * The Hard Reset Configuration Word (HRCW) table is in the first 64 + * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 + * times so the processor can fetch it out of flash whether the flash + * is 8, 16, 32, or 64 bits wide (hardware trickery). */ - .data - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" - .text #define _HRCW_TABLE_ENTRY(w) \ .fill 8,1,(((w)>>24)&0xff); \ @@ -100,6 +92,18 @@ version_string: _HRCW_TABLE_ENTRY(CFG_HRCW_LOW) _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) +/* + * Magic number and version string - put it after the HRCW since it + * cannot be first in flash like it is in many other processors. + */ + .long 0x27051956 /* U-Boot Magic Number */ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, "\0" + #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined diff --git a/doc/README.mpc832xemds b/doc/README.mpc832xemds new file mode 100644 index 00000000000..4cfc0fb752a --- /dev/null +++ b/doc/README.mpc832xemds @@ -0,0 +1,129 @@ +Freescale MPC832XEMDS Board +----------------------------------------- +1. Board Switches and Jumpers +1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board + For some reason, the HW designers describe the switch settings + in terms of 0 and 1, and then map that to physical switches where + the label "On" refers to logic 0 and "Off" is logic 1. + + Switch bits are numbered 1 through, like, 4 6 8 or 10, but the + bits may contribute to signals that are numbered based at 0, + and some of those signals may be high-bit-number-0 too. Heed + well the names and labels and do not get confused. + + "Off" == 1 + "On" == 0 + + SW3 is switch 18 as silk-screened onto the board. + SW4[8] is the bit labled 8 on Switch 4. + SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. + SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. + SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" + and bits labeled 8 is set as "Off". + +1.1 For the MPC832XEMDS PROTO Board + + First, make sure the board default setting is consistent with the document + shipped with your board. Then apply the following setting: + SW3[1-8]= 0000_1000 (core PLL setting, core enable) + SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) + SW5[1-8]= 0010_0110 (Boot from high end) + SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) + SW7[1-8]= 1000_0011 (QE PLL setting) + + ENET3/4 MII mode settings: + J1 1-2 (ETH3_TXER) + J2 2-3 (MII mode) + J3 2-3 (MII mode) + J4 2-3 (ADSL clockOscillator) + J5 1-2 (ETH4_TXER) + J6 2-3 (ClockOscillator) + JP1 removed (don't force PORESET) + JP2 mounted (ETH4/2 MII) + JP3 mounted (ETH3 MII) + JP4 mounted (HRCW from BCSR) + + ENET3/4 RMII mode settings: + J1 1-2 (ETH3_TXER) + J2 1-2 (RMII mode) + J3 1-2 (RMII mode) + J4 2-3 (ADSL clockOscillator) + J5 1-2 (ETH4_TXER) + J6 2-3 (ClockOscillator) + JP1 removed (don't force PORESET) + JP2 removed (ETH4/2 RMII) + JP3 removed (ETH3 RMII) + JP4 removed (HRCW from FLASH) + + on board Oscillator: 66M + + +2. Memory Map + +2.1 The memory map should look pretty much like this: + + 0x0000_0000 0x7fff_ffff DDR 2G + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M + 0xc000_0000 0xdfff_ffff Empty 512M + 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M + 0xe020_0000 0xe02f_ffff Empty 1M + 0xe030_0000 0xe03f_ffff PCI IO 1M + 0xe040_0000 0xefff_ffff Empty 252M + 0xf400_0000 0xf7ff_ffff Empty 64M + 0xf800_0000 0xf800_7fff BCSR on CS1 32K + 0xf800_8000 0xf800_ffff PIB CS2 32K + 0xf801_0000 0xf801_7fff PIB CS3 32K + 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC832XEPB.h + + CONFIG_MPC83XX MPC83XX family for MPC8349, MPC8360 and MPC832X + CONFIG_MPC832X MPC832X specific + CONFIG_MPC832XEMDS MPC832XEMDS board specific + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC832XEMDS_config + make + + MPC832X support PCI 33MHz and PCI 66MHz, to make u-boot support PCI: + + 1)Make sure the DIP SW support PCI mode as described in Section 1.1. + + 2)To Make U-Boot image support PCI 33MHz, use + Make MPC832XEMDS_HOST_33_config + + 3)To Make U-Boot image support PCI 66MHz, use + Make MPC832XEMDS_HOST_66M_config + +5. Downloading and Flashing Images + +5.0 Download over network: + + tftp 10000 u-boot.bin + +5.1 Reflash U-boot Image using U-boot + + tftp 20000 u-boot.bin + protect off fe000000 fe0fffff + erase fe000000 fe0fffff + cp.b 20000 fe000000 xxxx + +You have to supply the correct byte count with 'xxxx' from the TFTP result log. +Maybe 3ffff will work too, that corresponds to the erased sectors. + + +6. Notes + 1) The console baudrate for MPC832XEMDS is 115200bps. + diff --git a/doc/README.mpc8349itx b/doc/README.mpc8349itx new file mode 100644 index 00000000000..4ae03ae0559 --- /dev/null +++ b/doc/README.mpc8349itx @@ -0,0 +1,187 @@ +Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards +--------------------------------------------------- + +1. Board Description + + The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring + the Freescale MPC8349E processor in a Mini-ITX form factor. + + The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: + + A) One 8MB on-board flash EEPROM chip, instead of two. + B) No SATA controller + C) No Compact Flash slot + D) No Mini-PCI slot + E) No Vitesse 7385 5-port Ethernet switch + F) No 4-port USB Type-A interface + +2. Board Switches and Jumpers + +2.0 Descriptions for all of the board jumpers can be found in the User + Guide. Of particular interest to U-Boot developers is jumper J22: + + Pos. Name Default Description + ----------------------------------------------------------------------- + A LGPL0 ON (0) HRCW source, bit 0 + B LGPL1 ON (0) HRCW source, bit 1 + C LGPL3 ON (0) HRCW source, bit 2 + D LGPL5 OFF (1) PCI_SYNC_OUT frequency + E BOOT1 ON (0) Flash EEPROM boot device + F PCI_M66EN ON (0) PCI 66MHz enable + G I2C-WP ON (0) I2C EEPROM write protection + H F_WP OFF (1) Flash EEPROM write protection + + Jumper J22.E is only for the ITX, and it decides the configuration + of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip + U4 is located at address FE000000 and flash chip U7 is at FE800000. + If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. + + For U-Boot development, J22.E can be used to switch back-and-forth + between two U-Boot images. + +3. Memory Map + +3.1. The memory map should look pretty much like this: + + 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) + 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) + 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) + 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) + 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) + 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) + 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) + 0xF001_0000 - 0xF001_FFFF Local bus expansion slot + 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) + 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) + +3.2 Flash EEPROM layout. + + On the ITX, jumper J22.E is used to determine which flash chips are + at which address. When J22.E is switched, addresses from FE000000 + to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. + + On the ITX, at the normal boot address (aka HIGHBOOT): + + FE00_0000 HRCW + FE70_0000 Alternative U-Boot image + FE80_0000 Alternative HRCW + FEF0_0000 U-Boot image + FEFF_FFFF End of flash + + On the ITX, at the low boot address (LOWBOOT) + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + FE80_0000 Alternative HRCW and U-Boot image + FEFF_FFFF End of flash + + On the ITX-GP, the only option is LOWBOOT and there is only one chip + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + F7FF_FFFF End of flash + +4. Definitions + +4.1 Explanation of NEW definitions in: + + include/configs/MPC8349ITX.h + + CONFIG_MPC83XX MPC83xx family + CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC8349ITX MPC8349E-mITX + CONFIG_MPC8349ITXGP MPC8349E-mITX-GP + +5. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + + make MPC8349ITX_config + or: + make MPC8349ITXGP_config + or: + make MPC8349ITX_LOWBOOT_config + + make + +6. Downloading and Flashing Images + +6.1 Download via tftp: + + tftp $loadaddr + + where "" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.1 Reflash U-Boot Image using U-Boot + + setenv uboot + run tftpflash + + where "" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.2 Using the HRCW to switch between two different U-Boot images on the ITX + + Because the ITX has 16MB of flash, it is possible to keep two U-Boot + images in flash, and use the HRCW to specify which one is to be used + when the board boots. This trick is especially effective with a + hardware debugger that can override the HRCW, such as the BDI-2000. + + When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image + at address FE000000. When the BMS bit is 1, the ITX will boot the + image at address FEF00000. + + Therefore, just put a U-Boot image at both FE000000 and FEF00000 and + change the BMS bit whenever you want to boot the other image. + + Step-by-step instructions: + + 1) Build an ITX image to be loaded at FEF00000 + + make distclean + make MPC8349ITX_config + make + + 2) Take the u-boot.bin image and flash it at FEF00000. + + tftp $loadaddr u-boot.bin + protect off all + erase FEF00000 +$filesize + cp.b $loadaddr FEF00000 $filesize + + 3) Build an ITX image to be loaded at FE000000 + + make distclean + make MPC8349ITX_LOWBOOT_config + make + + 4) Take the u-boot.bin image and flash it at FE000000. + + tftp $loadaddr u-boot.bin + protect off FE000000 +$filesize + erase FE000000 +$filesize + cp.b $loadaddr FE000000 $filesize + + The HRCW in flash is currently set to boot the image at FE000000. + + If you have a hardware debugger, configure it to set the HRCW to + B460A000 04040000 if you want to boot the image at FEF00000, or set + it to B060A000 04040000 if you want to boot the image at FE000000. + + To change the HRCW in flash to boot the image at FEF00000, use these + U-Boot commands: + + cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 + mw.b 1020 b4 8 ; modify BMS bit + protect off FE000000 +10000 + erase FE000000 +10000 + cp.b 1000 FE000000 10000 + +7. Notes + 1) The console baudrate for MPC8349EITX is 115200bps. diff --git a/doc/README.sbc8349 b/doc/README.sbc8349 new file mode 100644 index 00000000000..a0ac6388d60 --- /dev/null +++ b/doc/README.sbc8349 @@ -0,0 +1,99 @@ + + + U-Boot for Wind River SBC834x Boards + ==================================== + + +The Wind River SBC834x board is a 6U form factor (not CPCI) reference +design that uses the MPC8347E or MPC8349E processor. U-Boot support +for this board is heavily based on the existing U-Boot support for +Freescale MPC8349 reference boards. + +Support has been primarily tested on the SBC8349 version of the board, +although earlier versions were also tested on the SBC8347. The primary +difference in the two is the level of PCI functionality. + + http://www.windriver.com/products/OCD/SBC8347E_49E/ + + +Flash Details: +============== + +The flash type is intel 28F640Jx (4096x16) [one device]. Base address +is 0xFF80_0000 which is also where the Hardware Reset Configuration +Word (HRCW) is stored. Caution should be used to not overwrite the +HRCW, or "CF RCW" with a Wind River ICE will be required to restore +the HRCW and allow the board to enter background mode for further +steps in the flash process. + + +Restoring a corrupted or missing flash image: +============================================= + +Details for storing U-boot to flash using a Wind River ICE can be found +on page 19 of the board manual (request ERG-00328-001). The following +is a summary of that information: + + - Connect ICE and establish connection to it from WorkBench/OCD. + - Ensure you have background mode (BKM) in the OCD terminal window. + - Select the appropriate flash type (listed above) + - Prepare a u-boot image by using the Wind River Convert utility; + by using "Convert and Add file" on the ELF file from your build. + Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are + trying to preserve your old environment settings). + - Set the start address of the erase/flash process to FFF0_0000 + - Set the target RAM required to 64kB. + - Select sectors for erasing (see note on enviroment below) + - Select Erase and Reprogram. + +Note that some versions of the register files used with Workbench +would zero some TSEC registers, which inhibits ethernet operation +by u-boot when this register file is played to the target. Using +"INN" in the OCD terminal window instead of "IN" before the "GO" +will not play the register file, and allow u-boot to use the TSEC +interface while executed from the ICE "GO" command. + +Alternatively, you can locate the register file which will be named +WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines +beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to +use all the remaining register file content. + +If you wish to preserve your prior U-Boot environment settings, +then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF. +The size for converting (and erasing) must be at least as large +as u-boot.bin. + + +Updating U-Boot with U-Boot: +============================ + +This procedure is very similar to other boards that have u-boot installed. +Assuming that the network has been configured, and that the new u-boot.bin +has been copied to the TFTP server, the commands are: + + tftp 200000 u-boot.bin + protect off all + erase fff00000 fff3ffff + cp.b 200000 fff00000 3ffff + protect on all + + +PCI: +==== + +This board and U-Boot have been tested with PCI built in, on a SBC8349 +and confirmed that the "pci" command showed the intel e1000 that was +present in the PCI slot. Note that if a 33MHz 32bit card is inserted +in the slot, then the whole board will clock down to a 33MHz base +clock instead of the default 66MHz. This will change the baud clocks +and mess up your serial console output. If you want to use a 33MHz PCI +card, then you should build a U-Boot with #undef PCI_66M in the +include/configs/sbc8349.h and store this to flash prior to powering down +the board and inserting the 33MHz PCI card. + +By default PCI support is disabled to better support very early +revision MPC834x chips with possible PCI issues. Also PCI support is +untested on the sbc8347 variants at this point in time. + + + Paul Gortmaker, 01/2007 diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c index c92909608a3..ebae5af154e 100644 --- a/drivers/fsl_i2c.c +++ b/drivers/fsl_i2c.c @@ -58,6 +58,7 @@ i2c_init(int speed, int slaveadd) dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ + udelay(5); /* let it shutdown in peace */ writeb(0x3F, &dev->fdr); /* set bus speed */ writeb(0x3F, &dev->dfsrr); /* set default filter */ writeb(slaveadd << 1, &dev->adr); /* write slave address */ @@ -191,15 +192,17 @@ __i2c_read(u8 *data, int length) int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) { - int i = 0; + int i = -1; /* signal error */ u8 *a = (u8*)&addr; if (i2c_wait4bus() >= 0 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 - && __i2c_write(&a[4 - alen], alen) == alen - && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) { + && __i2c_write(&a[4 - alen], alen) == alen) + i = 0; /* No error so far */ + + if (length + && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) i = __i2c_read(data, length); - } writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); @@ -212,7 +215,7 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) { - int i = 0; + int i = -1; /* signal error */ u8 *a = (u8*)&addr; if (i2c_wait4bus() >= 0 @@ -232,16 +235,14 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) int i2c_probe(uchar chip) { - int tmp; - - /* - * Try to read the first location of the chip. The underlying - * driver doesn't appear to support sending just the chip address - * and looking for an back. + /* For unknow reason the controller will ACK when + * probing for a slave with the same address, so skip + * it. */ - udelay(10000); + if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) + return -1; - return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + return i2c_read(chip, 0, 0, NULL, 0); } uchar diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h index f7f8ed0a724..0bcd0a9573e 100644 --- a/drivers/qe/qe.h +++ b/drivers/qe/qe.h @@ -30,7 +30,7 @@ #define UCC_MAX_NUM 8 #define QE_DATAONLY_BASE (uint)(128) -#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE) +#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) /* QE threads SNUM */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index f640c819161..c416a67c832 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -432,7 +432,12 @@ static int init_phy(struct eth_device *dev) } memset(mii_info, 0, sizeof(*mii_info)); - mii_info->speed = SPEED_1000; + if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { + mii_info->speed = SPEED_1000; + } else { + mii_info->speed = SPEED_100; + } + mii_info->duplex = DUPLEX_FULL; mii_info->pause = 0; mii_info->link = 1; @@ -508,7 +513,8 @@ static void adjust_link(struct eth_device *dev) } if (mii_info->speed != uec->oldspeed) { - switch (mii_info->speed) { + if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { + switch (mii_info->speed) { case 1000: break; case 100: @@ -531,6 +537,7 @@ static void adjust_link(struct eth_device *dev) printf("%s: Ack,Speed(%d)is illegal\n", dev->name, mii_info->speed); break; + } } printf("%s: Speed %dBT\n", dev->name, mii_info->speed); @@ -1122,7 +1129,7 @@ static int uec_send(struct eth_device* dev, volatile void *buf, int len) uec_private_t *uec; ucc_fast_private_t *uccf; volatile qe_bd_t *bd; - volatile u16 status; + u16 status; int i; int result = 0; @@ -1131,7 +1138,7 @@ static int uec_send(struct eth_device* dev, volatile void *buf, int len) bd = uec->txBd; /* Find an empty TxBD */ - for (i = 0; BD_STATUS(bd) & TxBD_READY; i++) { + for (i = 0; bd->status & TxBD_READY; i++) { if (i > 0x100000) { printf("%s: tx buffer not ready\n", dev->name); return result; @@ -1141,7 +1148,7 @@ static int uec_send(struct eth_device* dev, volatile void *buf, int len) /* Init TxBD */ BD_DATA_SET(bd, buf); BD_LENGTH_SET(bd, len); - status = BD_STATUS(bd); + status = bd->status; status &= BD_WRAP; status |= (TxBD_READY | TxBD_LAST); BD_STATUS_SET(bd, status); @@ -1150,13 +1157,11 @@ static int uec_send(struct eth_device* dev, volatile void *buf, int len) ucc_fast_transmit_on_demand(uccf); /* Wait for buffer to be transmitted */ - status = BD_STATUS(bd); - for (i = 0; status & TxBD_READY; i++) { + for (i = 0; bd->status & TxBD_READY; i++) { if (i > 0x100000) { printf("%s: tx error\n", dev->name); return result; } - status = BD_STATUS(bd); } /* Ok, the buffer be transimitted */ @@ -1171,12 +1176,12 @@ static int uec_recv(struct eth_device* dev) { uec_private_t *uec = dev->priv; volatile qe_bd_t *bd; - volatile u16 status; + u16 status; u16 len; u8 *data; bd = uec->rxBd; - status = BD_STATUS(bd); + status = bd->status; while (!(status & RxBD_EMPTY)) { if (!(status & RxBD_ERROR)) { @@ -1190,7 +1195,7 @@ static int uec_recv(struct eth_device* dev) BD_LENGTH_SET(bd, 0); BD_STATUS_SET(bd, status | RxBD_EMPTY); BD_ADVANCE(bd, status, uec->p_rx_bd_ring); - status = BD_STATUS(bd); + status = bd->status; } uec->rxBd = bd; diff --git a/drivers/tsec.c b/drivers/tsec.c index 2524e4f6d2b..3f11eb03b41 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -381,6 +381,61 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) return 0; } +/* + * Parse the BCM54xx status register for speed and duplex information. + * The linux sungem_phy has this information, but in a table format. + */ +uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) +{ + + switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ + + case 1: + printf("Enet starting in 10BT/HD\n"); + priv->duplexity = 0; + priv->speed = 10; + break; + + case 2: + printf("Enet starting in 10BT/FD\n"); + priv->duplexity = 1; + priv->speed = 10; + break; + + case 3: + printf("Enet starting in 100BT/HD\n"); + priv->duplexity = 0; + priv->speed = 100; + break; + + case 5: + printf("Enet starting in 100BT/FD\n"); + priv->duplexity = 1; + priv->speed = 100; + break; + + case 6: + printf("Enet starting in 1000BT/HD\n"); + priv->duplexity = 0; + priv->speed = 1000; + break; + + case 7: + printf("Enet starting in 1000BT/FD\n"); + priv->duplexity = 1; + priv->speed = 1000; + break; + + default: + printf("Auto-neg error, defaulting to 10BT/HD\n"); + priv->duplexity = 0; + priv->speed = 10; + break; + } + + return 0; + +} /* Parse the 88E1011's status register for speed and duplex * information */ @@ -770,6 +825,34 @@ static void tsec_halt(struct eth_device *dev) phy_run_commands(priv, priv->phyinfo->shutdown); } +/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ +struct phy_info phy_info_BCM5461S = { + 0x02060c1, /* 5461 ID */ + "Broadcom BCM5461S", + 0, /* not clear to me what minor revisions we can shift away */ + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", @@ -1112,6 +1195,7 @@ struct phy_info phy_info_dp83865 = { struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_cis8201, + &phy_info_BCM5461S, &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1145, diff --git a/drivers/tsec.h b/drivers/tsec.h index cee30037db0..422bc669229 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -109,6 +109,11 @@ #define MIIM_GBIT_CONTROL 0x9 #define MIIM_GBIT_CONTROL_INIT 0xe00 +/* Broadcom BCM54xx -- taken from linux sungem_phy */ +#define MIIM_BCM54xx_AUXSTATUS 0x19 +#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 +#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 + /* Cicada Auxiliary Control/Status Register */ #define MIIM_CIS8201_AUX_CONSTAT 0x1c #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 79dcae416f9..ff9512f203c 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -15,6 +15,11 @@ #define PVR_8360_REV10 (PVR_83xx | 0x0020) #define PVR_8360_REV11 (PVR_83xx | 0x0020) +#if defined(CONFIG_MPC832X) +#undef PVR_83xx +#define PVR_83xx 0x80840000 +#endif + /* * Hardware Implementation-Dependent Register 0 (HID0) */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 8bc61b63a85..c113b7ee0e4 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -52,12 +52,12 @@ typedef struct global_data { #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined (CONFIG_MPC8349) +#if defined (CONFIG_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbmph_clk; u32 usbdr_clk; -#endif /* CONFIG_MPC8349 */ +#endif /* CONFIG_MPC834X */ u32 core_clk; u32 i2c1_clk; u32 i2c2_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 43cde5e28ef..5e088d67d24 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -3,20 +3,11 @@ * * MPC83xx Internal Memory Map * - * History : - * 20060601: Daveliu (daveliu@freescale.com) - * TanyaJiang (tanya.jiang@freescale.com) - * Unified variable names for mpc83xx - * 2005 : Mandy Lavi (mandy.lavi@freescale.com) - * support for mpc8360e - * 2004 : Eran Liberty (liberty@freescale.com) - * Initialized for mpc8349 - * based on: - * MPC8260 Internal Memory Map - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - * MPC85xx Internal Memory Map - * Copyright(c) 2002,2003 Motorola Inc. - * Xianghua Xiao (x.xiao@motorola.com) + * Contributors: + * Dave Liu + * Tanya Jiang + * Mandy Lavi + * Eran Liberty * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -37,36 +28,24 @@ #ifndef __IMMAP_83xx__ #define __IMMAP_83xx__ -#include #include #include /* - * Local Access Window. + * Local Access Window */ typedef struct law83xx { u32 bar; /* LBIU local access window base address register */ -/* Identifies the 20 most-significant address bits of the base of local - * access window n. The specified base address should be aligned to the - * window size, as defined by LBLAWARn[SIZE]. - */ -#define LAWBAR_BAR 0xFFFFF000 -#define LAWBAR_RES ~(LAWBAR_BAR) u32 ar; /* LBIU local access window attribute register */ } law83xx_t; /* - * System configuration registers. + * System configuration registers */ typedef struct sysconf83xx { u32 immrbar; /* Internal memory map base address register */ u8 res0[0x04]; u32 altcbar; /* Alternate configuration base address register */ -/* Identifies the12 most significant address bits of an alternate base - * address used for boot sequencer configuration accesses. - */ -#define ALTCBAR_BASE_ADDR 0xFFF00000 -#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ u8 res1[0x14]; law83xx_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; @@ -77,116 +56,14 @@ typedef struct sysconf83xx { u32 sgprl; /* System General Purpose Register Low */ u32 sgprh; /* System General Purpose Register High */ u32 spridr; /* System Part and Revision ID Register */ -#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ -#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ u8 res5[0x04]; u32 spcr; /* System Priority Configuration Register */ -#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ -#define SPCR_PCIHPE_SHIFT (31-3) -#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ -#define SPCR_PCIPR_SHIFT (31-7) -#define SPCR_OPT 0x00800000 /* Optimize */ -#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ -#define SPCR_TBEN_SHIFT (31-9) -#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ -#define SPCR_COREPR_SHIFT (31-11) -#if defined (CONFIG_MPC8349) -#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ -#define SPCR_TSEC1DP_SHIFT (31-19) -#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ -#define SPCR_TSEC1BDP_SHIFT (31-21) -#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ -#define SPCR_TSEC1EP_SHIFT (31-23) -#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ -#define SPCR_TSEC2DP_SHIFT (31-27) -#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ -#define SPCR_TSEC2BDP_SHIFT (31-29) -#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ -#define SPCR_TSEC2EP_SHIFT (31-31) -#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ - | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ - | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) -#elif defined (CONFIG_MPC8360) -#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR) -#endif - u32 sicrl; /* System General Purpose Register Low */ -#if defined (CONFIG_MPC8349) -#define SICRL_LDP_A 0x80000000 -#define SICRL_USB1 0x40000000 -#define SICRL_USB0 0x20000000 -#define SICRL_UART 0x0C000000 -#define SICRL_GPIO1_A 0x02000000 -#define SICRL_GPIO1_B 0x01000000 -#define SICRL_GPIO1_C 0x00800000 -#define SICRL_GPIO1_D 0x00400000 -#define SICRL_GPIO1_E 0x00200000 -#define SICRL_GPIO1_F 0x00180000 -#define SICRL_GPIO1_G 0x00040000 -#define SICRL_GPIO1_H 0x00020000 -#define SICRL_GPIO1_I 0x00010000 -#define SICRL_GPIO1_J 0x00008000 -#define SICRL_GPIO1_K 0x00004000 -#define SICRL_GPIO1_L 0x00003000 -#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \ - | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \ - | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \ - | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \ - | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L ) -#elif defined (CONFIG_MPC8360) -#define SICRL_LDP_A 0xC0000000 -#define SICRL_LCLK_1 0x10000000 -#define SICRL_LCLK_2 0x08000000 -#define SICRL_SRCID_A 0x03000000 -#define SICRL_IRQ_CKSTP_A 0x00C00000 -#define SICRL_RES ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \ - SICRL_SRCID_A | SICRL_IRQ_CKSTP_A) -#endif - u32 sicrh; /* System General Purpose Register High */ -#define SICRH_DDR 0x80000000 -#if defined (CONFIG_MPC8349) -#define SICRH_TSEC1_A 0x10000000 -#define SICRH_TSEC1_B 0x08000000 -#define SICRH_TSEC1_C 0x04000000 -#define SICRH_TSEC1_D 0x02000000 -#define SICRH_TSEC1_E 0x01000000 -#define SICRH_TSEC1_F 0x00800000 -#define SICRH_TSEC2_A 0x00400000 -#define SICRH_TSEC2_B 0x00200000 -#define SICRH_TSEC2_C 0x00100000 -#define SICRH_TSEC2_D 0x00080000 -#define SICRH_TSEC2_E 0x00040000 -#define SICRH_TSEC2_F 0x00020000 -#define SICRH_TSEC2_G 0x00010000 -#define SICRH_TSEC2_H 0x00008000 -#define SICRH_GPIO2_A 0x00004000 -#define SICRH_GPIO2_B 0x00002000 -#define SICRH_GPIO2_C 0x00001000 -#define SICRH_GPIO2_D 0x00000800 -#define SICRH_GPIO2_E 0x00000400 -#define SICRH_GPIO2_F 0x00000200 -#define SICRH_GPIO2_G 0x00000180 -#define SICRH_GPIO2_H 0x00000060 -#define SICRH_TSOBI1 0x00000002 -#define SICRH_TSOBI2 0x00000001 -#define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ - | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \ - | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \ - | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \ - | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \ - | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \ - | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \ - | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \ - | SICRH_TSOBI2) -#elif defined (CONFIG_MPC8360) -#define SICRH_SECONDARY_DDR 0x40000000 -#define SICRH_SDDROE 0x02000000 /* SDDRIOE bit from reset configuration word high. */ -#define SICRH_UC1EOBI 0x00000004 /* UCC1 Ethernet Output Buffer Impedance. */ -#define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */ -#define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */ -#define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \ - SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI) -#endif - u8 res6[0xE4]; + u32 sicrl; /* System I/O Configuration Register Low */ + u32 sicrh; /* System I/O Configuration Register High */ + u8 res6[0x0C]; + u32 ddrcdr; /* DDR Control Driver Register */ + u32 ddrdsr; /* DDR Debug Status Register */ + u8 res7[0xD0]; } sysconf83xx_t; /* @@ -196,11 +73,8 @@ typedef struct wdt83xx { u8 res0[4]; u32 swcrr; /* System watchdog control register */ u32 swcnr; /* System watchdog count register */ -#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. -#define SWCNR_RES ~(SWCNR_SWCN) u8 res1[2]; u16 swsrr; /* System watchdog service register */ -#define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field. */ u8 res2[0xF0]; } wdt83xx_t; @@ -209,91 +83,46 @@ typedef struct wdt83xx { */ typedef struct rtclk83xx { u32 cnr; /* control register */ -#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ -#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ -#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ -#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ -#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) u32 ldr; /* load register */ -#define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be - * loaded in a 32-bit RTC counter.*/ u32 psr; /* prescale register */ -#define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits. */ - u32 ctr; /* Counter value field register */ -#define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field. */ + u32 ctr; /* counter value field register */ u32 evr; /* event register */ -#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ -#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ -#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF) -#define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit. */ -#define PTEVR_RES ~(PTEVR_PIF) u32 alr; /* alarm register */ u8 res0[0xE8]; } rtclk83xx_t; /* - * Global timper module + * Global timer module */ - typedef struct gtm83xx { - u8 cfr1; /* Timer1/2 Configuration */ -#define CFR1_PCAS 0x80 /* Pair Cascade mode */ -#define CFR1_BCM 0x40 /* Backward compatible mode */ -#define CFR1_STP2 0x20 /* Stop timer */ -#define CFR1_RST2 0x10 /* Reset timer */ -#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ -#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ -#define CFR1_STP1 0x02 /* Stop timer */ -#define CFR1_RST1 0x01 /* Reset timer */ -#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\ - CFR1_GM1 | CFR1_STP1 | CFR1_RST1) + u8 cfr1; /* Timer1/2 Configuration */ u8 res0[3]; - u8 cfr2; /* Timer3/4 Configuration */ -#define CFR2_PCAS 0x80 /* Pair Cascade mode */ -#define CFR2_SCAS 0x40 /* Super Cascade mode */ -#define CFR2_STP4 0x20 /* Stop timer */ -#define CFR2_RST4 0x10 /* Reset timer */ -#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ -#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ -#define CFR2_STP3 0x02 /* Stop timer */ -#define CFR2_RST3 0x01 /* Reset timer */ + u8 cfr2; /* Timer3/4 Configuration */ u8 res1[10]; - u16 mdr1; /* Timer1 Mode Register */ -#define MDR_SPS 0xff00 /* Secondary Prescaler value */ -#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ -#define MDR_OM 0x0020 /* Output mode */ -#define MDR_ORI 0x0010 /* Output reference interrupt enable */ -#define MDR_FRR 0x0008 /* Free run/restart */ -#define MDR_ICLK 0x0006 /* Input clock source for the timer */ -#define MDR_GE 0x0001 /* Gate enable */ - u16 mdr2; /* Timer2 Mode Register */ - u16 rfr1; /* Timer1 Reference Register */ - u16 rfr2; /* Timer2 Reference Register */ - u16 cpr1; /* Timer1 Capture Register */ - u16 cpr2; /* Timer2 Capture Register */ - u16 cnr1; /* Timer1 Counter Register */ - u16 cnr2; /* Timer2 Counter Register */ - u16 mdr3; /* Timer3 Mode Register */ - u16 mdr4; /* Timer4 Mode Register */ - u16 rfr3; /* Timer3 Reference Register */ - u16 rfr4; /* Timer4 Reference Register */ - u16 cpr3; /* Timer3 Capture Register */ - u16 cpr4; /* Timer4 Capture Register */ - u16 cnr3; /* Timer3 Counter Register */ - u16 cnr4; /* Timer4 Counter Register */ - u16 evr1; /* Timer1 Event Register */ - u16 evr2; /* Timer2 Event Register */ - u16 evr3; /* Timer3 Event Register */ - u16 evr4; /* Timer4 Event Register */ -#define GTEVR_REF 0x0002 /* Output reference event */ -#define GTEVR_CAP 0x0001 /* Counter Capture event */ -#define GTEVR_RES ~(EVR_CAP|EVR_REF) - u16 psr1; /* Timer1 Prescaler Register */ - u16 psr2; /* Timer2 Prescaler Register */ - u16 psr3; /* Timer3 Prescaler Register */ - u16 psr4; /* Timer4 Prescaler Register */ -#define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */ -#define GTPSR_RES ~(GTPSR_PPS) + u16 mdr1; /* Timer1 Mode Register */ + u16 mdr2; /* Timer2 Mode Register */ + u16 rfr1; /* Timer1 Reference Register */ + u16 rfr2; /* Timer2 Reference Register */ + u16 cpr1; /* Timer1 Capture Register */ + u16 cpr2; /* Timer2 Capture Register */ + u16 cnr1; /* Timer1 Counter Register */ + u16 cnr2; /* Timer2 Counter Register */ + u16 mdr3; /* Timer3 Mode Register */ + u16 mdr4; /* Timer4 Mode Register */ + u16 rfr3; /* Timer3 Reference Register */ + u16 rfr4; /* Timer4 Reference Register */ + u16 cpr3; /* Timer3 Capture Register */ + u16 cpr4; /* Timer4 Capture Register */ + u16 cnr3; /* Timer3 Counter Register */ + u16 cnr4; /* Timer4 Counter Register */ + u16 evr1; /* Timer1 Event Register */ + u16 evr2; /* Timer2 Event Register */ + u16 evr3; /* Timer3 Event Register */ + u16 evr4; /* Timer4 Event Register */ + u16 psr1; /* Timer1 Prescaler Register */ + u16 psr2; /* Timer2 Prescaler Register */ + u16 psr3; /* Timer3 Prescaler Register */ + u16 psr4; /* Timer4 Prescaler Register */ u8 res[0xC0]; } gtm83xx_t; @@ -301,188 +130,31 @@ typedef struct gtm83xx { * Integrated Programmable Interrupt Controller */ typedef struct ipic83xx { - u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ -#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ -#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ -#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ -#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ -#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ -#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ -#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) - u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ -#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ -#define SICVR_IVEC 0x0000007f /* Interrupt vector */ -#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) - u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ -#if defined (CONFIG_MPC8349) -#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ -#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ -#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ -#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ -#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ -#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ -#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ -#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ -#endif -#if defined (CONFIG_MPC8360) -#define SIIH_H_QE_H 0x80000000 /* QE high interrupt */ -#define SIIH_H_QE_L 0x40000000 /* QE low interrupt */ -#endif -#define SIIH_UART1 0x00000080 /* UART1 interrupt */ -#define SIIH_UART2 0x00000040 /* UART2 interrupt */ -#define SIIH_SEC 0x00000020 /* SEC interrupt */ -#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ -#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIH_SPI 0x00000001 /* SPI interrupt */ -#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ - | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ - | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ - | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \ - | SIIH_I2C2 | SIIH_SPI) -#endif -#if defined (CONFIG_MPC8360) -#define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \ - SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2) -#endif - u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ -#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ -#define SIIL_PIT 0x40000000 /* PIT interrupt */ -#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ -#endif -#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ -#define SIIL_MU 0x04000000 /* Message Unit interrupt */ -#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ -#define SIIL_DMA 0x01000000 /* DMA interrupt */ -#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ -#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ -#if defined (CONFIG_MPC8349) -#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ -#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ -#endif -#if defined (CONFIG_MPC8360) -#define SIIL_QEP 0x00200000 /* QE ports interrupt */ -#define SIIL_SDDR 0x00100000 /* SDDR interrupt */ -#endif -#define SIIL_DDR 0x00080000 /* DDR interrupt */ -#define SIIL_LBC 0x00040000 /* LBC interrupt */ -#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ -#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ -#define SIIL_PMC 0x00008000 /* PMC interrupt */ -#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ -#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ -#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ -#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ -#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ -#if defined (CONFIG_MPC8349) -#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ - | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ - | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ - | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \ - | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \ - | SIIL_GTM5 |SIIL_DPTC ) -#endif -#if defined (CONFIG_MPC8360) -#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \ - |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ - |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ - |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ - |SIIL_GTM5 ) -#endif - u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ + u32 sicfr; /* System Global Interrupt Configuration Register */ + u32 sivcr; /* System Global Interrupt Vector Register */ + u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ + u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ + u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ u8 res0[8]; - u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ - u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ - u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ + u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ + u32 simsr_h; /* System Internal Interrupt Mask Register - High */ + u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ u8 res1[4]; - u32 sepnr; /* System External Interrupt Pending Register (SEI) */ - u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ - u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ -#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ -#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ -#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ -#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ -#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ -#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ -#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ -#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ -#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) - u32 semsr; /* System External Interrupt Mask Register (SEI) */ -#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ -#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ -#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ -#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ -#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ -#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ -#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ -#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ -#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ -#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \ - | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ - | SEI_SIRQ0) - u32 secnr; /* System External Interrupt Control Register (SECNR) */ -#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ -#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ -#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ -#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ -#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ -#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ -#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ -#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ -#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ -#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ -#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ -#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ -#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \ - | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ - | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ - | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) - u32 sersr; /* System Error Status Register (SERR) */ - u32 sermr; /* System Error Mask Register (SERR) */ -#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ -#define SERR_WDT 0x40000000 /* WDT MCP request */ -#define SERR_SBA 0x20000000 /* SBA MCP request */ -#if defined (CONFIG_MPC8349) -#define SERR_DDR 0x10000000 /* DDR MCP request */ -#define SERR_LBC 0x08000000 /* LBC MCP request */ -#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ -#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ -#endif -#if defined (CONFIG_MPC8360) -#define SERR_CIEE 0x10000000 /* CIEE MCP request */ -#define SERR_CMEE 0x08000000 /* CMEEMCP request */ -#define SERR_PCI 0x04000000 /* PCI MCP request */ -#endif -#define SERR_MU 0x01000000 /* MU MCP request */ -#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ -#if defined (CONFIG_MPC8349) -#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ - |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ - |SERR_RNC ) -#elif defined (CONFIG_MPC8360) -#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\ - |SERR_CMEE|SERR_PCI|SERR_MU) -#endif - u32 sercr; /* System Error Control Register (SERCR) */ -#define SERCR_MCPR 0x00000001 /* MCP Route */ -#define SERCR_RES ~(SERCR_MCPR) + u32 sepnr; /* System External Interrupt Pending Register */ + u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ + u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ + u32 semsr; /* System External Interrupt Mask Register */ + u32 secnr; /* System External Interrupt Control Register */ + u32 sersr; /* System Error Status Register */ + u32 sermr; /* System Error Mask Register */ + u32 sercr; /* System Error Control Register */ u8 res2[4]; - u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ - u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ - u32 sefcr; /* System External Interrupt Force Register (SEI) */ - u32 serfr; /* System Error Force Register (SERR) */ + u32 sifcr_h; /* System Internal Interrupt Force Register - High */ + u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ + u32 sefcr; /* System External Interrupt Force Register */ + u32 serfr; /* System Error Force Register */ u32 scvcr; /* System Critical Interrupt Vector Register */ -#define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible - critical interrupt vector. */ -#define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */ -#define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC) u32 smvcr; /* System Management Interrupt Vector Register */ -#define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible - critical interrupt vector. */ -#define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */ -#define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC) u8 res3[0x98]; } ipic83xx_t; @@ -491,43 +163,14 @@ typedef struct ipic83xx { */ typedef struct arbiter83xx { u32 acr; /* Arbiter Configuration Register */ -#define ACR_COREDIS 0x10000000 /* Core disable. */ -#define ACR_COREDIS_SHIFT (31-7) -#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ -#define ACR_PIPE_DEP_SHIFT (31-15) -#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ -#define ACR_PCI_RPTCNT_SHIFT (31-19) -#define ACR_RPTCNT 0x00000700 /* Repeat count. */ -#define ACR_RPTCNT_SHIFT (31-23) -#define ACR_APARK 0x00000030 /* Address parking. */ -#define ACR_APARK_SHIFT (31-27) -#define ACR_PARKM 0x0000000F /* Parking master. */ -#define ACR_PARKM_SHIFT (31-31) -#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) u32 atr; /* Arbiter Timers Register */ -#define ATR_DTO 0x00FF0000 /* Data time out. */ -#define ATR_ATO 0x000000FF /* Address time out. */ -#define ATR_RES ~(ATR_DTO|ATR_ATO) u8 res[4]; - u32 aer; /* Arbiter Event Register (AE) */ - u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ - u32 amr; /* Arbiter Mask Register (AE) */ + u32 aer; /* Arbiter Event Register */ + u32 aidr; /* Arbiter Interrupt Definition Register */ + u32 amr; /* Arbiter Mask Register */ u32 aeatr; /* Arbiter Event Attributes Register */ -#define AEATR_EVENT 0x07000000 /* Event type. */ -#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ -#define AEATR_TBST 0x00000800 /* Transfer burst. */ -#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ -#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ -#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE) u32 aeadr; /* Arbiter Event Address Register */ - u32 aerr; /* Arbiter Event Response Register (AE) */ -#define AE_ETEA 0x00000020 /* Transfer error. */ -#define AE_RES_ 0x00000010 /* Reserved transfer type. */ -#define AE_ECW 0x00000008 /* External control word transfer type. */ -#define AE_AO 0x00000004 /* Address Only transfer type. */ -#define AE_DTO 0x00000002 /* Data time out. */ -#define AE_ATO 0x00000001 /* Address time out. */ -#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) + u32 aerr; /* Arbiter Event Response Register */ u8 res1[0xDC]; } arbiter83xx_t; @@ -535,184 +178,24 @@ typedef struct arbiter83xx { * Reset Module */ typedef struct reset83xx { - u32 rcwl; /* RCWL Register */ -#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ -#define RCWL_LBIUCM_SHIFT 31 -#define RCWL_DDRCM 0x40000000 /* DDRCM */ -#define RCWL_DDRCM_SHIFT 30 -#if defined (CONFIG_MPC8349) -#define RCWL_SVCOD 0x30000000 /* SVCOD */ -#endif -#define RCWL_SPMF 0x0f000000 /* SPMF */ -#define RCWL_SPMF_SHIFT 24 -#define RCWL_COREPLL 0x007F0000 /* COREPLL */ -#define RCWL_COREPLL_SHIFT 16 -#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ -#define RCWL_CEPDF 0x00000020 /* CEPDF */ -#define RCWL_CEPDF_SHIFT 5 -#define RCWL_CEPMF 0x0000001F /* CEPMF */ -#define RCWL_CEPMF_SHIFT 0 -#if defined (CONFIG_MPC8349) -#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) -#elif defined (CONFIG_MPC8360) -#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) -#endif - u32 rcwh; /* RCHL Register */ -#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#define RCWH_PCIHOST_SHIFT 31 -#if defined (CONFIG_MPC8349) -#define RCWH_PCI64 0x40000000 /* PCI64 */ -#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ -#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ -#elif defined (CONFIG_MPC8360) -#define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */ -#define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */ -#endif -#define RCWH_COREDIS 0x08000000 /* COREDIS */ -#define RCWH_BMS 0x04000000 /* BMS */ -#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ -#define RCWH_SWEN 0x00800000 /* SWEN */ -#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ -#if defined (CONFIG_MPC8349) -#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ -#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ -#define RCWH_TPR 0x00000100 /* TPR */ -#elif defined (CONFIG_MPC8360) -#define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */ -#endif -#define RCWH_TLE 0x00000008 /* TLE */ -#define RCWH_LALE 0x00000004 /* LALE */ -#if defined (CONFIG_MPC8349) -#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ - | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ - | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ - | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \ - | RCWH_TLE | RCWH_LALE) -#elif defined (CONFIG_MPC8360) -#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \ - |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \ - |RCWH_SDDRIOE |RCWH_TLE) -#endif + u32 rcwl; /* Reset Configuration Word Low Register */ + u32 rcwh; /* Reset Configuration Word High Register */ u8 res0[8]; - u32 rsr; /* Reset status Register */ -#define RSR_RSTSRC 0xE0000000 /* Reset source */ -#define RSR_RSTSRC_SHIFT 29 -#define RSR_BSF 0x00010000 /* Boot seq. fail */ -#define RSR_BSF_SHIFT 16 -#define RSR_SWSR 0x00002000 /* software soft reset */ -#define RSR_SWSR_SHIFT 13 -#define RSR_SWHR 0x00001000 /* software hard reset */ -#define RSR_SWHR_SHIFT 12 -#define RSR_JHRS 0x00000200 /* jtag hreset */ -#define RSR_JHRS_SHIFT 9 -#define RSR_JSRS 0x00000100 /* jtag sreset status */ -#define RSR_JSRS_SHIFT 8 -#define RSR_CSHR 0x00000010 /* checkstop reset status */ -#define RSR_CSHR_SHIFT 4 -#define RSR_SWRS 0x00000008 /* software watchdog reset status */ -#define RSR_SWRS_SHIFT 3 -#define RSR_BMRS 0x00000004 /* bus monitop reset status */ -#define RSR_BMRS_SHIFT 2 -#define RSR_SRS 0x00000002 /* soft reset status */ -#define RSR_SRS_SHIFT 1 -#define RSR_HRS 0x00000001 /* hard reset status */ -#define RSR_HRS_SHIFT 0 -#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) - u32 rmr; /* Reset mode Register */ -#define RMR_CSRE 0x00000001 /* checkstop reset enable */ -#define RMR_CSRE_SHIFT 0 -#define RMR_RES ~(RMR_CSRE) - u32 rpr; /* Reset protection Register */ - u32 rcr; /* Reset Control Register */ -#define RCR_SWHR 0x00000002 /* software hard reset */ -#define RCR_SWSR 0x00000001 /* software soft reset */ -#define RCR_RES ~(RCR_SWHR | RCR_SWSR) - u32 rcer; /* Reset Control Enable Register */ -#define RCER_CRE 0x00000001 /* software hard reset */ -#define RCER_RES ~(RCER_CRE) + u32 rsr; /* Reset Status Register */ + u32 rmr; /* Reset Mode Register */ + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ + u32 rcer; /* Reset Control Enable Register */ u8 res1[0xDC]; } reset83xx_t; +/* + * Clock Module + */ typedef struct clk83xx { - u32 spmr; /* system PLL mode Register */ -#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ -#define SPMR_DDRCM 0x40000000 /* DDRCM */ -#if defined (CONFIG_MPC8349) -#define SPMR_SVCOD 0x30000000 /* SVCOD */ -#endif -#define SPMR_SPMF 0x0F000000 /* SPMF */ -#define SPMR_CKID 0x00800000 /* CKID */ -#define SPMR_CKID_SHIFT 23 -#define SPMR_COREPLL 0x007F0000 /* COREPLL */ -#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ -#define SPMR_CEPDF 0x00000020 /* CEPDF */ -#define SPMR_CEPMF 0x0000001F /* CEPMF */ -#if defined (CONFIG_MPC8349) -#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ - | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ - | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) -#elif defined (CONFIG_MPC8360) -#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \ - | SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \ - | SPMR_CEPDF | SPMR_CEPMF) -#endif - u32 occr; /* output clock control Register */ -#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ -#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ -#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ -#if defined (CONFIG_MPC8349) -#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ -#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ -#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ -#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ -#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ -#endif -#define OCCR_PCICD0 0x00800000 /* PCICD0 */ -#define OCCR_PCICD1 0x00400000 /* PCICD1 */ -#define OCCR_PCICD2 0x00200000 /* PCICD2 */ -#if defined (CONFIG_MPC8349) -#define OCCR_PCICD3 0x00100000 /* PCICD3 */ -#define OCCR_PCICD4 0x00080000 /* PCICD4 */ -#define OCCR_PCICD5 0x00040000 /* PCICD5 */ -#define OCCR_PCICD6 0x00020000 /* PCICD6 */ -#define OCCR_PCICD7 0x00010000 /* PCICD7 */ -#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ -#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ -#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \ - | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \ - | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \ - | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \ - | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \ - | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR ) -#endif -#if defined (CONFIG_MPC8360) -#define OCCR_PCICR 0x00000002 /* PCI clock rate */ -#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \ - |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR ) -#endif - u32 sccr; /* system clock control Register */ -#if defined (CONFIG_MPC8349) -#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ -#define SCCR_TSEC1CM_SHIFT 30 -#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ -#define SCCR_TSEC2CM_SHIFT 28 -#endif -#define SCCR_ENCCM 0x03000000 /* ENCCM */ -#define SCCR_ENCCM_SHIFT 24 -#if defined (CONFIG_MPC8349) -#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ -#define SCCR_USBMPHCM_SHIFT 22 -#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ -#define SCCR_USBDRCM_SHIFT 20 -#endif -#define SCCR_PCICM 0x00010000 /* PCICM */ -#if defined (CONFIG_MPC8349) -#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ - | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) -#endif -#if defined (CONFIG_MPC8360) -#define SCCR_RES ~(SCCR_ENCCM | SCCR_PCICM) -#endif + u32 spmr; /* system PLL mode Register */ + u32 occr; /* output clock control Register */ + u32 sccr; /* system clock control Register */ u8 res0[0xF4]; } clk83xx_t; @@ -720,27 +203,14 @@ typedef struct clk83xx { * Power Management Control Module */ typedef struct pmc83xx { - u32 pmccr; /* PMC Configuration Register */ -#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ -#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ -#if defined (CONFIG_MPC8360) -#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ -#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) -#elif defined (CONFIG_MPC8349) -#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) -#endif - u32 pmcer; /* PMC Event Register */ -#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ -#define PMCER_RES ~(PMCER_PMCI) - u32 pmcmr; /* PMC Mask Register */ -#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ -#define PMCMR_RES ~(PMCMR_PMCIE) + u32 pmccr; /* PMC Configuration Register */ + u32 pmcer; /* PMC Event Register */ + u32 pmcmr; /* PMC Mask Register */ u8 res0[0xF4]; } pmc83xx_t; -#if defined (CONFIG_MPC8349) /* - * general purpose I/O module + * General purpose I/O module */ typedef struct gpio83xx { u32 dir; /* direction register */ @@ -751,124 +221,20 @@ typedef struct gpio83xx { u32 icr; /* external interrupt control register */ u8 res0[0xE8]; } gpio83xx_t; -#endif -#if defined (CONFIG_MPC8360) /* * QE Ports Interrupts Registers */ typedef struct qepi83xx { u8 res0[0xC]; u32 qepier; /* QE Ports Interrupt Event Register */ -#define QEPIER_PA15 0x80000000 -#define QEPIER_PA16 0x40000000 -#define QEPIER_PA29 0x20000000 -#define QEPIER_PA30 0x10000000 -#define QEPIER_PB3 0x08000000 -#define QEPIER_PB5 0x04000000 -#define QEPIER_PB12 0x02000000 -#define QEPIER_PB13 0x01000000 -#define QEPIER_PB26 0x00800000 -#define QEPIER_PB27 0x00400000 -#define QEPIER_PC27 0x00200000 -#define QEPIER_PC28 0x00100000 -#define QEPIER_PC29 0x00080000 -#define QEPIER_PD12 0x00040000 -#define QEPIER_PD13 0x00020000 -#define QEPIER_PD16 0x00010000 -#define QEPIER_PD17 0x00008000 -#define QEPIER_PD26 0x00004000 -#define QEPIER_PD27 0x00002000 -#define QEPIER_PE12 0x00001000 -#define QEPIER_PE13 0x00000800 -#define QEPIER_PE24 0x00000400 -#define QEPIER_PE25 0x00000200 -#define QEPIER_PE26 0x00000100 -#define QEPIER_PE27 0x00000080 -#define QEPIER_PE31 0x00000040 -#define QEPIER_PF20 0x00000020 -#define QEPIER_PG31 0x00000010 -#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \ - |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \ - |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \ - |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \ - |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \ - |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31) u32 qepimr; /* QE Ports Interrupt Mask Register */ -#define QEPIMR_PA15 0x80000000 -#define QEPIMR_PA16 0x40000000 -#define QEPIMR_PA29 0x20000000 -#define QEPIMR_PA30 0x10000000 -#define QEPIMR_PB3 0x08000000 -#define QEPIMR_PB5 0x04000000 -#define QEPIMR_PB12 0x02000000 -#define QEPIMR_PB13 0x01000000 -#define QEPIMR_PB26 0x00800000 -#define QEPIMR_PB27 0x00400000 -#define QEPIMR_PC27 0x00200000 -#define QEPIMR_PC28 0x00100000 -#define QEPIMR_PC29 0x00080000 -#define QEPIMR_PD12 0x00040000 -#define QEPIMR_PD13 0x00020000 -#define QEPIMR_PD16 0x00010000 -#define QEPIMR_PD17 0x00008000 -#define QEPIMR_PD26 0x00004000 -#define QEPIMR_PD27 0x00002000 -#define QEPIMR_PE12 0x00001000 -#define QEPIMR_PE13 0x00000800 -#define QEPIMR_PE24 0x00000400 -#define QEPIMR_PE25 0x00000200 -#define QEPIMR_PE26 0x00000100 -#define QEPIMR_PE27 0x00000080 -#define QEPIMR_PE31 0x00000040 -#define QEPIMR_PF20 0x00000020 -#define QEPIMR_PG31 0x00000010 -#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \ - |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \ - |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \ - |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \ - |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \ - |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31) u32 qepicr; /* QE Ports Interrupt Control Register */ -#define QEPICR_PA15 0x80000000 -#define QEPICR_PA16 0x40000000 -#define QEPICR_PA29 0x20000000 -#define QEPICR_PA30 0x10000000 -#define QEPICR_PB3 0x08000000 -#define QEPICR_PB5 0x04000000 -#define QEPICR_PB12 0x02000000 -#define QEPICR_PB13 0x01000000 -#define QEPICR_PB26 0x00800000 -#define QEPICR_PB27 0x00400000 -#define QEPICR_PC27 0x00200000 -#define QEPICR_PC28 0x00100000 -#define QEPICR_PC29 0x00080000 -#define QEPICR_PD12 0x00040000 -#define QEPICR_PD13 0x00020000 -#define QEPICR_PD16 0x00010000 -#define QEPICR_PD17 0x00008000 -#define QEPICR_PD26 0x00004000 -#define QEPICR_PD27 0x00002000 -#define QEPICR_PE12 0x00001000 -#define QEPICR_PE13 0x00000800 -#define QEPICR_PE24 0x00000400 -#define QEPICR_PE25 0x00000200 -#define QEPICR_PE26 0x00000100 -#define QEPICR_PE27 0x00000080 -#define QEPICR_PE31 0x00000040 -#define QEPICR_PF20 0x00000020 -#define QEPICR_PG31 0x00000010 -#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \ - |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \ - |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \ - |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \ - |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \ - |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31) u8 res1[0xE8]; } qepi83xx_t; /* - * general purpose I/O module + * QE Parallel I/O Ports */ typedef struct gpio_n { u32 podr; /* Open Drain Register */ @@ -879,238 +245,93 @@ typedef struct gpio_n { u32 ppar2; /* Pin Assignment Register 2 */ } gpio_n_t; -typedef struct gpio83xx { +typedef struct qegpio83xx { gpio_n_t ioport[0x7]; u8 res0[0x358]; -} gpio83xx_t; +} qepio83xx_t; /* * QE Secondary Bus Access Windows */ - typedef struct qesba83xx { u32 lbmcsar; /* Local bus memory controller start address */ -#define LBMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ -#define LBMCSAR_RES ~(LBMCSAR_SA) u32 sdmcsar; /* Secondary DDR memory controller start address */ -#define SDMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ -#define SDMCSAR_RES ~(SDMCSAR_SA) u8 res0[0x38]; u32 lbmcear; /* Local bus memory controller end address */ -#define LBMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ -#define LBMCEAR_RES ~(LBMCEAR_EA) u32 sdmcear; /* Secondary DDR memory controller end address */ -#define SDMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ -#define SDMCEAR_RES ~(SDMCEAR_EA) u8 res1[0x38]; - u32 lbmcar; /* Local bus memory controller attributes */ -#define LBMCAR_WEN 0x00000001 /* Forward transactions to the QE local bus */ -#define LBMCAR_RES ~(LBMCAR_WEN) + u32 lbmcar; /* Local bus memory controller attributes */ u32 sdmcar; /* Secondary DDR memory controller attributes */ -#define SDMCAR_WEN 0x00000001 /* Forward transactions to the second DDR bus */ -#define SDMCAR_RES ~(SDMCAR_WEN) - u8 res2[0x778]; + u8 res2[0x378]; } qesba83xx_t; -#endif /* * DDR Memory Controller Memory Map */ typedef struct ddr_cs_bnds { u32 csbnds; -#define CSBNDS_SA 0x00FF0000 -#define CSBNDS_SA_SHIFT 8 -#define CSBNDS_EA 0x000000FF -#define CSBNDS_EA_SHIFT 24 u8 res0[4]; } ddr_cs_bnds_t; typedef struct ddr83xx { - ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ + ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ u8 res0[0x60]; - u32 cs_config[4]; /**< Chip Select x Configuration */ -#define CSCONFIG_EN 0x80000000 -#define CSCONFIG_AP 0x00800000 -#define CSCONFIG_ROW_BIT 0x00000700 -#define CSCONFIG_ROW_BIT_12 0x00000000 -#define CSCONFIG_ROW_BIT_13 0x00000100 -#define CSCONFIG_ROW_BIT_14 0x00000200 -#define CSCONFIG_COL_BIT 0x00000007 -#define CSCONFIG_COL_BIT_8 0x00000000 -#define CSCONFIG_COL_BIT_9 0x00000001 -#define CSCONFIG_COL_BIT_10 0x00000002 -#define CSCONFIG_COL_BIT_11 0x00000003 - u8 res1[0x78]; - u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ -#define TIMING_CFG1_PRETOACT 0x70000000 -#define TIMING_CFG1_PRETOACT_SHIFT 28 -#define TIMING_CFG1_ACTTOPRE 0x0F000000 -#define TIMING_CFG1_ACTTOPRE_SHIFT 24 -#define TIMING_CFG1_ACTTORW 0x00700000 -#define TIMING_CFG1_ACTTORW_SHIFT 20 -#define TIMING_CFG1_CASLAT 0x00070000 -#define TIMING_CFG1_CASLAT_SHIFT 16 -#define TIMING_CFG1_REFREC 0x0000F000 -#define TIMING_CFG1_REFREC_SHIFT 12 -#define TIMING_CFG1_WRREC 0x00000700 -#define TIMING_CFG1_WRREC_SHIFT 8 -#define TIMING_CFG1_ACTTOACT 0x00000070 -#define TIMING_CFG1_ACTTOACT_SHIFT 4 -#define TIMING_CFG1_WRTORD 0x00000007 -#define TIMING_CFG1_WRTORD_SHIFT 0 -#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ -#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ - - u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ -#define TIMING_CFG2_CPO 0x0F000000 -#define TIMING_CFG2_CPO_SHIFT 24 -#define TIMING_CFG2_ACSM 0x00080000 -#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 -#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 -#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ - - u32 sdram_cfg; /**< SDRAM Control Configuration */ -#define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 -#define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 -#define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 - + u32 cs_config[4]; /* Chip Select x Configuration */ + u8 res1[0x70]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 ddr_data_init; /* SDRAM Data Initialization */ u8 res2[4]; - u32 sdram_mode; /**< SDRAM Mode Configuration */ -#define SDRAM_MODE_ESD 0xFFFF0000 -#define SDRAM_MODE_ESD_SHIFT 16 -#define SDRAM_MODE_SD 0x0000FFFF -#define SDRAM_MODE_SD_SHIFT 0 -#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ -#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ -#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ -#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ -#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ -#define DDR_MODE_WEAK 0x0002 /* weak drivers */ -#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ -#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ -#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ -#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ -#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ -#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ -#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ -#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ -#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ -#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ -#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ -#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ -#define DDR_MODE_MODEREG 0x0000 /* select mode register */ - - u8 res3[8]; - u32 sdram_interval; /**< SDRAM Interval Configuration */ -#define SDRAM_INTERVAL_REFINT 0x3FFF0000 -#define SDRAM_INTERVAL_REFINT_SHIFT 16 -#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF -#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 - u8 res9[8]; - u32 sdram_clk_cntl; -#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 -#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 - - u8 res4[0xCCC]; - u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ - u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ - u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ -#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ -#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ -#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ -#define ECC_ERR_INJECT_EEIM_SHIFT 0 - u8 res5[0x14]; - u32 capture_data_hi; /**< Memory Data Path Read Capture High */ - u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ - u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ -#define CAPTURE_ECC_ECE (0xff000000>>24) -#define CAPTURE_ECC_ECE_SHIFT 0 + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res3[0x14]; + u32 ddr_init_addr; /* DDR training initialization address */ + u32 ddr_init_ext_addr; /* DDR training initialization extended address */ + u8 res4[0xAA8]; + u32 ddr_ip_rev1; /* DDR IP block revision 1 */ + u32 ddr_ip_rev2; /* DDR IP block revision 2 */ + u8 res5[0x200]; + u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ + u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ u8 res6[0x14]; - u32 err_detect; /**< Memory Error Detect */ -#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ -#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ -#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ -#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ - u32 err_disable; /**< Memory Error Disable */ -#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ -#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ -#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ -#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED) - u32 err_int_en; /**< Memory Error Interrupt Enable */ -#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ -#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ -#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ -#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) - u32 capture_attributes; /**< Memory Error Attributes Capture */ -#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ -#define ECC_CAPT_ATTR_BNUM_SHIFT 28 -#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ -#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 -#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 -#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 -#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 -#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 -#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ -#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 -#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 -#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 -#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 -#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) -#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 -#define ECC_CAPT_ATTR_TSRC_I2C 0x9 -#define ECC_CAPT_ATTR_TSRC_JTAG 0xA -#define ECC_CAPT_ATTR_TSRC_PCI1 0xD -#define ECC_CAPT_ATTR_TSRC_PCI2 0xE -#define ECC_CAPT_ATTR_TSRC_DMA 0xF -#define ECC_CAPT_ATTR_TSRC_SHIFT 16 -#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ -#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 -#define ECC_CAPT_ATTR_TTYP_READ 0x2 -#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 -#define ECC_CAPT_ATTR_TTYP_SHIFT 12 -#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ - u32 capture_address; /**< Memory Error Address Capture */ - u32 capture_ext_address;/**< Memory Error Extended Address Capture */ - u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ -#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ -#define ECC_ERROR_MAN_SBET_SHIFT 16 -#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ -#define ECC_ERROR_MAN_SBEC_SHIFT 0 - u8 res7[0xA4]; + u32 capture_data_hi; /* Memory Data Path Read Capture High */ + u32 capture_data_lo; /* Memory Data Path Read Capture Low */ + u32 capture_ecc; /* Memory Data Path Read Capture ECC */ + u8 res7[0x14]; + u32 err_detect; /* Memory Error Detect */ + u32 err_disable; /* Memory Error Disable */ + u32 err_int_en; /* Memory Error Interrupt Enable */ + u32 capture_attributes; /* Memory Error Attributes Capture */ + u32 capture_address; /* Memory Error Address Capture */ + u32 capture_ext_address;/* Memory Error Extended Address Capture */ + u32 err_sbe; /* Memory Single-Bit ECC Error Management */ + u8 res8[0xA4]; u32 debug_reg; - u8 res8[0xFC]; + u8 res9[0xFC]; } ddr83xx_t; -/* - * I2C1 Controller - */ - /* * DUART */ typedef struct duart83xx { - u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ - u8 uier_udmb; /**< combined register for UIER and UDMB */ - u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ - u8 ulcr; /**< line control register */ - u8 umcr; /**< MODEM control register */ - u8 ulsr; /**< line status register */ - u8 umsr; /**< MODEM status register */ - u8 uscr; /**< scratch register */ + u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ + u8 uier_udmb; /* combined register for UIER and UDMB */ + u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ + u8 ulcr; /* line control register */ + u8 umcr; /* MODEM control register */ + u8 ulsr; /* line status register */ + u8 umsr; /* MODEM status register */ + u8 uscr; /* scratch register */ u8 res0[8]; - u8 udsr; /**< DMA status register */ + u8 udsr; /* DMA status register */ u8 res1[3]; u8 res2[0xEC]; } duart83xx_t; @@ -1119,75 +340,52 @@ typedef struct duart83xx { * Local Bus Controller Registers */ typedef struct lbus_bank { - u32 br; /**< Base Register */ - u32 or; /**< Base Register */ + u32 br; /* Base Register */ + u32 or; /* Option Register */ } lbus_bank_t; typedef struct lbus83xx { lbus_bank_t bank[8]; u8 res0[0x28]; - u32 mar; /**< UPM Address Register */ + u32 mar; /* UPM Address Register */ u8 res1[0x4]; - u32 mamr; /**< UPMA Mode Register */ - u32 mbmr; /**< UPMB Mode Register */ - u32 mcmr; /**< UPMC Mode Register */ + u32 mamr; /* UPMA Mode Register */ + u32 mbmr; /* UPMB Mode Register */ + u32 mcmr; /* UPMC Mode Register */ u8 res2[0x8]; - u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ - u32 mdr; /**< UPM Data Register */ + u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ + u32 mdr; /* UPM Data Register */ u8 res3[0x8]; - u32 lsdmr; /**< SDRAM Mode Register */ + u32 lsdmr; /* SDRAM Mode Register */ u8 res4[0x8]; - u32 lurt; /**< UPM Refresh Timer */ - u32 lsrt; /**< SDRAM Refresh Timer */ + u32 lurt; /* UPM Refresh Timer */ + u32 lsrt; /* SDRAM Refresh Timer */ u8 res5[0x8]; - u32 ltesr; /**< Transfer Error Status Register */ - u32 ltedr; /**< Transfer Error Disable Register */ - u32 lteir; /**< Transfer Error Interrupt Register */ - u32 lteatr; /**< Transfer Error Attributes Register */ - u32 ltear; /**< Transfer Error Address Register */ + u32 ltesr; /* Transfer Error Status Register */ + u32 ltedr; /* Transfer Error Disable Register */ + u32 lteir; /* Transfer Error Interrupt Register */ + u32 lteatr; /* Transfer Error Attributes Register */ + u32 ltear; /* Transfer Error Address Register */ u8 res6[0xC]; - u32 lbcr; /**< Configuration Register */ -#define LBCR_LDIS 0x80000000 -#define LBCR_LDIS_SHIFT 31 -#define LBCR_BCTLC 0x00C00000 -#define LBCR_BCTLC_SHIFT 22 -#define LBCR_LPBSE 0x00020000 -#define LBCR_LPBSE_SHIFT 17 -#define LBCR_EPAR 0x00010000 -#define LBCR_EPAR_SHIFT 16 -#define LBCR_BMT 0x0000FF00 -#define LBCR_BMT_SHIFT 8 - u32 lcrr; /**< Clock Ratio Register */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_SHIFT 0 - + u32 lbcr; /* Configuration Register */ + u32 lcrr; /* Clock Ratio Register */ u8 res7[0x28]; u8 res8[0xF00]; } lbus83xx_t; -#if defined (CONFIG_MPC8349) /* * Serial Peripheral Interface */ typedef struct spi83xx { - u32 mode; /**< mode register */ - u32 event; /**< event register */ - u32 mask; /**< mask register */ - u32 com; /**< command register */ + u32 mode; /* mode register */ + u32 event; /* event register */ + u32 mask; /* mask register */ + u32 com; /* command register */ u8 res0[0x10]; - u32 tx; /**< transmit register */ - u32 rx; /**< receive register */ - u8 res1[0xD8]; + u32 tx; /* transmit register */ + u32 rx; /* receive register */ + u8 res1[0xFD8]; } spi83xx_t; -#endif /* * DMA/Messaging Unit @@ -1197,21 +395,17 @@ typedef struct dma83xx { u32 omisr; /* 0x30 Outbound message interrupt status register */ u32 omimr; /* 0x34 Outbound message interrupt mask register */ u32 res1[0x6]; /* 0x38-0x49 reserved */ - u32 imr0; /* 0x50 Inbound message register 0 */ u32 imr1; /* 0x54 Inbound message register 1 */ u32 omr0; /* 0x58 Outbound message register 0 */ u32 omr1; /* 0x5C Outbound message register 1 */ - u32 odr; /* 0x60 Outbound doorbell register */ u32 res2; /* 0x64-0x67 reserved */ u32 idr; /* 0x68 Inbound doorbell register */ u32 res3[0x5]; /* 0x6C-0x79 reserved */ - u32 imisr; /* 0x80 Inbound message interrupt status register */ u32 imimr; /* 0x84 Inbound message interrupt mask register */ u32 res4[0x1E]; /* 0x88-0x99 reserved */ - u32 dmamr0; /* 0x100 DMA 0 mode register */ u32 dmasr0; /* 0x104 DMA 0 status register */ u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ @@ -1223,7 +417,6 @@ typedef struct dma83xx { u32 dmabcr0; /* 0x120 DMA 0 byte count register */ u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ u32 res8[0x16]; /* 0x128-0x179 reserved */ - u32 dmamr1; /* 0x180 DMA 1 mode register */ u32 dmasr1; /* 0x184 DMA 1 status register */ u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ @@ -1235,7 +428,6 @@ typedef struct dma83xx { u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ u32 res12[0x16]; /* 0x1A8-0x199 reserved */ - u32 dmamr2; /* 0x200 DMA 2 mode register */ u32 dmasr2; /* 0x204 DMA 2 status register */ u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ @@ -1247,7 +439,6 @@ typedef struct dma83xx { u32 dmabcr2; /* 0x220 DMA 2 byte count register */ u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ u32 res16[0x16]; /* 0x228-0x279 reserved */ - u32 dmamr3; /* 0x280 DMA 3 mode register */ u32 dmasr3; /* 0x284 DMA 3 status register */ u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ @@ -1258,39 +449,15 @@ typedef struct dma83xx { u32 res19; /* 0x29C reserved */ u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ - u32 dmagsr; /* 0x2A8 DMA general status register */ u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ } dma83xx_t; -/* DMAMRn bits */ -#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ -#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ -#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ -#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ -#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ - -/* DMASRn bits */ -#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ -#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ - /* * PCI Software Configuration Registers */ typedef struct pciconf83xx { u32 config_address; -#define PCI_CONFIG_ADDRESS_EN 0x80000000 -#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 -#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 -#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 -#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 -#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 -#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 -#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 -#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc u32 config_data; u32 int_ack; u8 res[116]; @@ -1313,34 +480,6 @@ typedef struct pci_outbound_window { */ typedef struct ios83xx { pot83xx_t pot[6]; -#define POTAR_TA_MASK 0x000fffff -#define POBAR_BA_MASK 0x000fffff -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ -#define POCMR_SE 0x20000000 /* streaming enable */ -#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ -#define POCMR_CM_MASK 0x000fffff -#define POCMR_CM_4G 0x00000000 -#define POCMR_CM_2G 0x00080000 -#define POCMR_CM_1G 0x000C0000 -#define POCMR_CM_512M 0x000E0000 -#define POCMR_CM_256M 0x000F0000 -#define POCMR_CM_128M 0x000F8000 -#define POCMR_CM_64M 0x000FC000 -#define POCMR_CM_32M 0x000FE000 -#define POCMR_CM_16M 0x000FF000 -#define POCMR_CM_8M 0x000FF800 -#define POCMR_CM_4M 0x000FFC00 -#define POCMR_CM_2M 0x000FFE00 -#define POCMR_CM_1M 0x000FFF00 -#define POCMR_CM_512K 0x000FFF80 -#define POCMR_CM_256K 0x000FFFC0 -#define POCMR_CM_128K 0x000FFFE0 -#define POCMR_CM_64K 0x000FFFF0 -#define POCMR_CM_32K 0x000FFFF8 -#define POCMR_CM_16K 0x000FFFFC -#define POCMR_CM_8K 0x000FFFFE -#define POCMR_CM_4K 0x000FFFFF u8 res0[0x60]; u32 pmcr; u8 res1[4]; @@ -1353,74 +492,13 @@ typedef struct ios83xx { */ typedef struct pcictrl83xx { u32 esr; -#define ESR_MERR 0x80000000 -#define ESR_APAR 0x00000400 -#define ESR_PCISERR 0x00000200 -#define ESR_MPERR 0x00000100 -#define ESR_TPERR 0x00000080 -#define ESR_NORSP 0x00000040 -#define ESR_TABT 0x00000020 u32 ecdr; -#define ECDR_APAR 0x00000400 -#define ECDR_PCISERR 0x00000200 -#define ECDR_MPERR 0x00000100 -#define ECDR_TPERR 0x00000080 -#define ECDR_NORSP 0x00000040 -#define ECDR_TABT 0x00000020 u32 eer; -#define EER_APAR 0x00000400 -#define EER_PCISERR 0x00000200 -#define EER_MPERR 0x00000100 -#define EER_TPERR 0x00000080 -#define EER_NORSP 0x00000040 -#define EER_TABT 0x00000020 u32 eatcr; -#define EATCR_ERRTYPR_MASK 0x70000000 -#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ -#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ -#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ -#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ -#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ -#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ -#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ -#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ -#define EATCR_BN_MASK 0x0f000000 /* beat number */ -#define EATCR_BN_1st 0x00000000 -#define EATCR_BN_2ed 0x01000000 -#define EATCR_BN_3rd 0x02000000 -#define EATCR_BN_4th 0x03000000 -#define EATCR_BN_5th 0x0400000 -#define EATCR_BN_6th 0x05000000 -#define EATCR_BN_7th 0x06000000 -#define EATCR_BN_8th 0x07000000 -#define EATCR_BN_9th 0x08000000 -#define EATCR_TS_MASK 0x00300000 /* transaction size */ -#define EATCR_TS_4 0x00000000 -#define EATCR_TS_1 0x00100000 -#define EATCR_TS_2 0x00200000 -#define EATCR_TS_3 0x00300000 -#define EATCR_ES_MASK 0x000f0000 /* error source */ -#define EATCR_ES_EM 0x00000000 /* external master */ -#define EATCR_ES_DMA 0x00050000 -#define EATCR_CMD_MASK 0x0000f000 -#if defined (CONFIG_MPC8349) -#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ -#endif -#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ -#if defined (CONFIG_MPC8349) -#define EATCR_HPB 0x00000004 /* high parity bit */ -#endif -#define EATCR_PB 0x00000002 /* parity bit */ -#define EATCR_VI 0x00000001 /* error information valid */ u32 eacr; u32 eeacr; -#if defined (CONFIG_MPC8349) u32 edlcr; u32 edhcr; -#elif defined (CONFIG_MPC8360) - u32 edcr; /* was edlcr */ - u8 res_edcr[0x4]; -#endif u32 gcr; u32 ecr; u32 gsr; @@ -1443,41 +521,8 @@ typedef struct pcictrl83xx { u8 res6[4]; u32 piwar0; u8 res7[132]; -#define PITAR_TA_MASK 0x000fffff -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 -#define PIWAR_IWS_MASK 0x0000003F -#define PIWAR_IWS_4K 0x0000000B -#define PIWAR_IWS_8K 0x0000000C -#define PIWAR_IWS_16K 0x0000000D -#define PIWAR_IWS_32K 0x0000000E -#define PIWAR_IWS_64K 0x0000000F -#define PIWAR_IWS_128K 0x00000010 -#define PIWAR_IWS_256K 0x00000011 -#define PIWAR_IWS_512K 0x00000012 -#define PIWAR_IWS_1M 0x00000013 -#define PIWAR_IWS_2M 0x00000014 -#define PIWAR_IWS_4M 0x00000015 -#define PIWAR_IWS_8M 0x00000016 -#define PIWAR_IWS_16M 0x00000017 -#define PIWAR_IWS_32M 0x00000018 -#define PIWAR_IWS_64M 0x00000019 -#define PIWAR_IWS_128M 0x0000001A -#define PIWAR_IWS_256M 0x0000001B -#define PIWAR_IWS_512M 0x0000001C -#define PIWAR_IWS_1G 0x0000001D -#define PIWAR_IWS_2G 0x0000001E } pcictrl83xx_t; -#if defined (CONFIG_MPC8349) /* * USB */ @@ -1491,7 +536,6 @@ typedef struct usb83xx { typedef struct tsec83xx { u8 fixme[0x1000]; } tsec83xx_t; -#endif /* * Security @@ -1500,581 +544,119 @@ typedef struct security83xx { u8 fixme[0x10000]; } security83xx_t; -#if defined (CONFIG_MPC8360) -/* - * iram - */ -typedef struct iram83xx { - u32 iadd; /* I-RAM address register */ - u32 idata; /* I-RAM data register */ - u8 res0[0x78]; -} iram83xx_t; - -/* - * Interrupt Controller - */ -typedef struct irq83xx { - u32 cicr; /* QE system interrupt configuration */ - u32 civec; /* QE system interrupt vector register */ - u32 cripnr; /* QE RISC interrupt pending register */ - u32 cipnr; /* QE system interrupt pending register */ - u32 cipxcc; /* QE interrupt priority register */ - u32 cipycc; /* QE interrupt priority register */ - u32 cipwcc; /* QE interrupt priority register */ - u32 cipzcc; /* QE interrupt priority register */ - u32 cimr; /* QE system interrupt mask register */ - u32 crimr; /* QE RISC interrupt mask register */ - u32 cicnr; /* QE system interrupt control register */ - u8 res0[0x4]; - u32 ciprta; /* QE system interrupt priority register for RISC tasks A */ - u32 ciprtb; /* QE system interrupt priority register for RISC tasks B */ - u8 res1[0x4]; - u32 cricr; /* QE system RISC interrupt control */ - u8 res2[0x20]; - u32 chivec; /* QE high system interrupt vector */ - u8 res3[0x1C]; -} irq83xx_t; - -/* - * Communications Processor - */ -typedef struct cp83xx { - u32 cecr; /* QE command register */ - u32 ceccr; /* QE controller configuration register */ - u32 cecdr; /* QE command data register */ - u8 res0[0xA]; - u16 ceter; /* QE timer event register */ - u8 res1[0x2]; - u16 cetmr; /* QE timers mask register */ - u32 cetscr; /* QE time-stamp timer control register */ - u32 cetsr1; /* QE time-stamp register 1 */ - u32 cetsr2; /* QE time-stamp register 2 */ - u8 res2[0x8]; - u32 cevter; /* QE virtual tasks event register */ - u32 cevtmr; /* QE virtual tasks mask register */ - u16 cercr; /* QE RAM control register */ - u8 res3[0x2]; - u8 res4[0x24]; - u16 ceexe1; /* QE external request 1 event register */ - u8 res5[0x2]; - u16 ceexm1; /* QE external request 1 mask register */ - u8 res6[0x2]; - u16 ceexe2; /* QE external request 2 event register */ - u8 res7[0x2]; - u16 ceexm2; /* QE external request 2 mask register */ - u8 res8[0x2]; - u16 ceexe3; /* QE external request 3 event register */ - u8 res9[0x2]; - u16 ceexm3; /* QE external request 3 mask register */ - u8 res10[0x2]; - u16 ceexe4; /* QE external request 4 event register */ - u8 res11[0x2]; - u16 ceexm4; /* QE external request 4 mask register */ - u8 res12[0x2]; - u8 res13[0x280]; -} cp83xx_t; - -/* - * QE Multiplexer - */ - -typedef struct qmx83xx { - u32 cmxgcr; /* CMX general clock route register */ - u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ - u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ - u32 cmxsi1syr; /* CMX SI1 SYNC route register */ - u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ - u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ - u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ - u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ - u32 cmxupcr; /* CMX UPC clock route register */ - u8 res0[0x1C]; -} qmx83xx_t; - -/* -* QE Timers -*/ - -typedef struct qet83xx { - u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */ - u8 res0[0x3]; - u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */ - u8 res1[0xB]; - u16 gtmdr1; /* Timer 1 mode register */ - u16 gtmdr2; /* Timer 2 mode register */ - u16 gtrfr1; /* Timer 1 reference register */ - u16 gtrfr2; /* Timer 2 reference register */ - u16 gtcpr1; /* Timer 1 capture register */ - u16 gtcpr2; /* Timer 2 capture register */ - u16 gtcnr1; /* Timer 1 counter */ - u16 gtcnr2; /* Timer 2 counter */ - u16 gtmdr3; /* Timer 3 mode register */ - u16 gtmdr4; /* Timer 4 mode register */ - u16 gtrfr3; /* Timer 3 reference register */ - u16 gtrfr4; /* Timer 4 reference register */ - u16 gtcpr3; /* Timer 3 capture register */ - u16 gtcpr4; /* Timer 4 capture register */ - u16 gtcnr3; /* Timer 3 counter */ - u16 gtcnr4; /* Timer 4 counter */ - u16 gtevr1; /* Timer 1 event register */ - u16 gtevr2; /* Timer 2 event register */ - u16 gtevr3; /* Timer 3 event register */ - u16 gtevr4; /* Timer 4 event register */ - u16 gtps; /* Timer 1 prescale register */ - u8 res2[0x46]; -} qet83xx_t; - -/* -* spi -*/ - -typedef struct spi83xx { - u8 res0[0x20]; - u32 spmode; /* SPI mode register */ - u8 res1[0x2]; - u8 spie; /* SPI event register */ - u8 res2[0x1]; - u8 res3[0x2]; - u8 spim; /* SPI mask register */ - u8 res4[0x1]; - u8 res5[0x1]; - u8 spcom; /* SPI command register */ - u8 res6[0x2]; - u32 spitd; /* SPI transmit data register (cpu mode) */ - u32 spird; /* SPI receive data register (cpu mode) */ - u8 res7[0x8]; -} spi83xx_t; - -/* -* mcc -*/ - -typedef struct mcc83xx { - u32 mcce; /* MCC event register */ - u32 mccm; /* MCC mask register */ - u32 mccf; /* MCC configuration register */ - u32 merl; /* MCC emergency request level register */ - u8 res0[0xF0]; -} mcc83xx_t; - -/* -* brg -*/ - -typedef struct brg83xx { - u32 brgc1; /* BRG1 configuration register */ - u32 brgc2; /* BRG2 configuration register */ - u32 brgc3; /* BRG3 configuration register */ - u32 brgc4; /* BRG4 configuration register */ - u32 brgc5; /* BRG5 configuration register */ - u32 brgc6; /* BRG6 configuration register */ - u32 brgc7; /* BRG7 configuration register */ - u32 brgc8; /* BRG8 configuration register */ - u32 brgc9; /* BRG9 configuration register */ - u32 brgc10; /* BRG10 configuration register */ - u32 brgc11; /* BRG11 configuration register */ - u32 brgc12; /* BRG12 configuration register */ - u32 brgc13; /* BRG13 configuration register */ - u32 brgc14; /* BRG14 configuration register */ - u32 brgc15; /* BRG15 configuration register */ - u32 brgc16; /* BRG16 configuration register */ - u8 res0[0x40]; -} brg83xx_t; - -/* -* USB -*/ - -typedef struct usb83xx { - u8 usmod; /* USB mode register */ - u8 usadd; /* USB address register */ - u8 uscom; /* USB command register */ - u8 res0[0x1]; - u16 usep0; /* USB endpoint register 0 */ - u16 usep1; /* USB endpoint register 1 */ - u16 usep2; /* USB endpoint register 2 */ - u16 usep3; /* USB endpoint register 3 */ - u8 res1[0x4]; - u16 usber; /* USB event register */ - u8 res2[0x2]; - u16 usbmr; /* USB mask register */ - u8 res3[0x1]; - u8 usbs; /* USB status register */ - u32 ussft; /* USB start of frame timer */ - u8 res4[0x24]; -} usb83xx_t; - -/* -* SI -*/ - -typedef struct si1_83xx { - u16 siamr1; /* SI1 TDMA mode register */ - u16 sibmr1; /* SI1 TDMB mode register */ - u16 sicmr1; /* SI1 TDMC mode register */ - u16 sidmr1; /* SI1 TDMD mode register */ - u8 siglmr1_h; /* SI1 global mode register high */ - u8 res0[0x1]; - u8 sicmdr1_h; /* SI1 command register high */ - u8 res2[0x1]; - u8 sistr1_h; /* SI1 status register high */ - u8 res3[0x1]; - u16 sirsr1_h; /* SI1 RAM shadow address register high */ - u8 sitarc1; /* SI1 RAM counter Tx TDMA */ - u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ - u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ - u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ - u8 sirarc1; /* SI1 RAM counter Rx TDMA */ - u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ - u8 sircrc1; /* SI1 RAM counter Rx TDMC */ - u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ - u8 res4[0x8]; - u16 siemr1; /* SI1 TDME mode register 16 bits */ - u16 sifmr1; /* SI1 TDMF mode register 16 bits */ - u16 sigmr1; /* SI1 TDMG mode register 16 bits */ - u16 sihmr1; /* SI1 TDMH mode register 16 bits */ - u8 siglmg1_l; /* SI1 global mode register low 8 bits */ - u8 res5[0x1]; - u8 sicmdr1_l; /* SI1 command register low 8 bits */ - u8 res6[0x1]; - u8 sistr1_l; /* SI1 status register low 8 bits */ - u8 res7[0x1]; - u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ - u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ - u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ - u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ - u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ - u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ - u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ - u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ - u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ - u8 res8[0x8]; - u32 siml1; /* SI1 multiframe limit register */ - u8 siedm1; /* SI1 extended diagnostic mode register */ - u8 res9[0xBB]; -} si1_83xx_t; - -/* -* SI Routing Tables -*/ - -typedef struct sir83xx { - u8 tx[0x400]; - u8 rx[0x400]; - u8 res0[0x800]; -} sir83xx_t; - -/* -* ucc -*/ - -typedef struct uslow { - u32 gumr_l; /* UCCx general mode register (low) */ - u32 gumr_h; /* UCCx general mode register (high) */ - u16 upsmr; /* UCCx protocol-specific mode register */ - u8 res0[0x2]; - u16 utodr; /* UCCx transmit on demand register */ - u16 udsr; /* UCCx data synchronization register */ - u16 ucce; /* UCCx event register */ - u8 res1[0x2]; - u16 uccm; /* UCCx mask register */ - u8 res2[0x1]; - u8 uccs; /* UCCx status register */ - u8 res3[0x1E8]; -} uslow_t; - -typedef struct ufast { - u32 gumr; /* UCCx general mode register */ - u32 upsmr; /* UCCx protocol-specific mode register */ - u16 utodr; /* UCCx transmit on demand register */ - u8 res0[0x2]; - u16 udsr; /* UCCx data synchronization register */ - u8 res1[0x2]; - u32 ucce; /* UCCx event register */ - u32 uccm; /* UCCx mask register. */ - u8 uccs; /* UCCx status register */ - u8 res2[0x7]; - u32 urfb; /* UCC receive FIFO base */ - u16 urfs; /* UCC receive FIFO size */ - u8 res3[0x2]; - u16 urfet; /* UCC receive FIFO emergency threshold */ - u16 urfset; /* UCC receive FIFO special emergency threshold */ - u32 utfb; /* UCC transmit FIFO base */ - u16 utfs; /* UCC transmit FIFO size */ - u8 res4[0x2]; - u16 utfet; /* UCC transmit FIFO emergency threshold */ - u8 res5[0x2]; - u16 utftt; /* UCC transmit FIFO transmit threshold */ - u8 res6[0x2]; - u16 utpt; /* UCC transmit polling timer */ - u32 urtry; /* UCC retry counter register */ - u8 res7[0x4C]; - u8 guemr; /* UCC general extended mode register */ - u8 res8[0x3]; - u8 res9[0x6C]; - u32 maccfg1; /* Mac configuration register #1 */ - u32 maccfg2; /* Mac configuration register #2 */ - u16 ipgifg; /* Interframe gap register */ - u8 res10[0x2]; - u32 hafdup; /* Half-duplex register */ - u8 res11[0xC]; - u32 emtr; /* Ethernet MAC test register */ - u32 miimcfg; /* MII mgmt configuration register */ - u32 miimcom; /* MII mgmt command register */ - u32 miimadd; /* MII mgmt address register */ - u32 miimcon; /* MII mgmt control register */ - u32 miistat; /* MII mgmt status register */ - u32 miimnd; /* MII mgmt indication register */ - u32 ifctl; /* Interface control register */ - u32 ifstat; /* Interface status register */ - u32 macstnaddr1; /* Station address part 1 register */ - u32 macstnaddr2; /* Station address part 2 register */ - u8 res12[0x8]; - u32 uempr; /* UCC Ethernet MAC parameter register */ - u32 utbipa; /* UCC TBI address */ - u16 uescr; /* UCC Ethernet statistics control register */ - u8 res13[0x26]; - u32 tx64; /* Transmit and receive 64-byte frame counter */ - u32 tx127; /* Transmit and receive 65- to 127-byte frame counter */ - u32 tx255; /* Transmit and receive 128- to 255-byte frame counter */ - u32 rx64; /* Receive and receive 64-byte frame counter */ - u32 rx127; /* Receive and receive 65- to 127-byte frame counter */ - u32 rx255; /* Receive and receive 128- to 255-byte frame counter */ - u32 txok; /* Transmit good bytes counter */ - u32 txcf; /* Transmit control frame counter */ - u32 tmca; /* Transmit multicast control frame counter */ - u32 tbca; /* Transmit broadcast packet counter */ - u32 rxfok; /* Receive frame OK counter */ - u32 rbyt; /* Receive good and bad bytes counter */ - u32 rxbok; /* Receive bytes OK counter */ - u32 rmca; /* Receive multicast packet counter */ - u32 rbca; /* Receive broadcast packet counter */ - u32 scar; /* Statistics carry register */ - u32 scam; /* Statistics carry mask register */ - u8 res14[0x3C]; -} ufast_t; - -typedef struct ucc83xx { - union { - uslow_t slow; - ufast_t fast; - }; -} ucc83xx_t; - -/* -* MultiPHY UTOPIA POS Controllers -*/ - -typedef struct upc83xx { - u32 upgcr; /* UTOPIA/POS general configuration register */ -#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ -#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ -#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ -#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing: */ -#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ - u32 uplpa; /* UTOPIA/POS last PHY address */ - u32 uphec; /* ATM HEC register */ - u32 upuc; /* UTOPIA/POS UCC configuration */ - u32 updc1; /* UTOPIA/POS device 1 configuration */ - u32 updc2; /* UTOPIA/POS device 2 configuration */ - u32 updc3; /* UTOPIA/POS device 3 configuration */ - u32 updc4; /* UTOPIA/POS device 4 configuration */ - u32 upstpa; /* UTOPIA/POS STPA threshold */ - u8 res0[0xC]; - u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ - u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ - u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ - u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ - u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ - u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ - u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ - u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ - u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ - u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ - u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ - u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ - u32 upde1; /* UTOPIA/POS device 1 event */ - u32 upde2; /* UTOPIA/POS device 2 event */ - u32 upde3; /* UTOPIA/POS device 3 event */ - u32 upde4; /* UTOPIA/POS device 4 event */ - u16 uprp1; - u16 uprp2; - u16 uprp3; - u16 uprp4; - u8 res1[0x8]; - u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ - u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ - u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ - u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ - u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ - u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ - u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ - u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ - u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ - u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ - u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ - u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ - u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ - u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ - u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ - u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ - u32 uper1; /* Device 1 port enable register */ - u32 uper2; /* Device 2 port enable register */ - u32 uper3; /* Device 3 port enable register */ - u32 uper4; /* Device 4 port enable register */ - u8 res2[0x150]; -} upc83xx_t; - -/* -* SDMA -*/ - -typedef struct sdma83xx { - u32 sdsr; /* Serial DMA status register */ - u32 sdmr; /* Serial DMA mode register */ - u32 sdtr1; /* SDMA system bus threshold register */ - u32 sdtr2; /* SDMA secondary bus threshold register */ - u32 sdhy1; /* SDMA system bus hysteresis register */ - u32 sdhy2; /* SDMA secondary bus hysteresis register */ - u32 sdta1; /* SDMA system bus address register */ - u32 sdta2; /* SDMA secondary bus address register */ - u32 sdtm1; /* SDMA system bus MSNUM register */ - u32 sdtm2; /* SDMA secondary bus MSNUM register */ - u8 res0[0x10]; - u32 sdaqr; /* SDMA address bus qualify register */ - u32 sdaqmr; /* SDMA address bus qualify mask register */ - u8 res1[0x4]; - u32 sdwbcr; /* SDMA CAM entries base register */ - u8 res2[0x38]; -} sdma83xx_t; - -/* -* Debug Space -*/ - -typedef struct dbg83xx { - u32 bpdcr; /* Breakpoint debug command register */ - u32 bpdsr; /* Breakpoint debug status register */ - u32 bpdmr; /* Breakpoint debug mask register */ - u32 bprmrr0; /* Breakpoint request mode risc register 0 */ - u32 bprmrr1; /* Breakpoint request mode risc register 1 */ - u8 res0[0x8]; - u32 bprmtr0; /* Breakpoint request mode trb register 0 */ - u32 bprmtr1; /* Breakpoint request mode trb register 1 */ - u8 res1[0x8]; - u32 bprmir; /* Breakpoint request mode immediate register */ - u32 bprmsr; /* Breakpoint request mode serial register */ - u32 bpemr; /* Breakpoint exit mode register */ - u8 res2[0x48]; -} dbg83xx_t; - -/* -* RISC Special Registers (Trap and Breakpoint) -*/ - -typedef struct rsp83xx { - u8 fixme[0x100]; -} rsp83xx_t; -#endif - +#if defined(CONFIG_MPC834X) typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ -#if defined (CONFIG_MPC8349) - gpio83xx_t pgio[2]; /* general purpose I/O module */ -#elif defined (CONFIG_MPC8360) - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ -#endif - u8 res0[0x200]; -#if defined (CONFIG_MPC8360) - u8 DLL_LBDDR[0x100]; -#endif - u8 DDL_DDR[0x100]; - u8 DDL_LBIU[0x100]; -#if defined (CONFIG_MPC8349) - u8 res1[0xE00]; -#elif defined (CONFIG_MPC8360) - u8 res1[0x200]; - gpio83xx_t gpio; /* General purpose I/O module */ - qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ -#endif - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res2[0x1300]; - duart83xx_t duart[2]; /* DUART */ -#if defined (CONFIG_MPC8349) - u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res4[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ - u8 res5[0xF00]; -#elif defined (CONFIG_MPC8360) - u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller */ - u8 res4[0x2000]; -#endif - dma83xx_t dma; /* DMA */ -#if defined (CONFIG_MPC8349) - pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ - u8 res6[0x19900]; - usb83xx_t usb; - tsec83xx_t tsec[2]; - u8 res7[0xA000]; - security83xx_t security; -#elif defined (CONFIG_MPC8360) - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res_5[128]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res6[0x4A00]; - ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ - u8 res7[0x22000]; - security83xx_t security; - u8 res8[0xC0000]; - iram83xx_t iram; /* IRAM */ - irq83xx_t irq; /* Interrupt Controller */ - cp83xx_t cp; /* Communications Processor */ - qmx83xx_t qmx; /* QE Multiplexer */ - qet83xx_t qet; /* QE Timers */ - spi83xx_t spi[0x2]; /* spi */ - mcc83xx_t mcc; /* mcc */ - brg83xx_t brg; /* brg */ - usb83xx_t usb; /* USB */ - si1_83xx_t si1; /* SI */ - u8 res9[0x800]; - sir83xx_t sir; /* SI Routing Tables */ - ucc83xx_t ucc1; /* ucc1 */ - ucc83xx_t ucc3; /* ucc3 */ - ucc83xx_t ucc5; /* ucc5 */ - ucc83xx_t ucc7; /* ucc7 */ - u8 res10[0x600]; - upc83xx_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ - ucc83xx_t ucc2; /* ucc2 */ - ucc83xx_t ucc4; /* ucc4 */ - ucc83xx_t ucc6; /* ucc6 */ - ucc83xx_t ucc8; /* ucc8 */ - u8 res11[0x600]; - upc83xx_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ - sdma83xx_t sdma; /* SDMA */ - dbg83xx_t dbg; /* Debug Space */ - rsp83xx_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint) */ - u8 res12[0x300]; - u8 res13[0x3A00]; - u8 res14[0x8000]; /* 0x108000 - 0x110000 */ - u8 res15[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ - u8 res16[0x24000]; /* 0x11C000 - 0x140000 */ - u8 res17[0xC0000]; /* 0x140000 - 0x200000 */ -#endif + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + gpio83xx_t gpio[2]; /* General purpose I/O module */ + u8 res0[0x200]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res1[0xE00]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res3[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res4[0x1000]; + spi83xx_t spi; /* Serial Peripheral Interface */ + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ + ios83xx_t ios; /* Sequencer */ + pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ + u8 res5[0x19900]; + usb83xx_t usb; + tsec83xx_t tsec[2]; + u8 res6[0xA000]; + security83xx_t security; + u8 res7[0xC0000]; } immap_t; +#elif defined(CONFIG_MPC8360) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + u8 res0[0x200]; + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + u8 res1[0x300]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res2[0x200]; + qepio83xx_t qepio; /* QE Parallel I/O ports */ + qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ + u8 res3[0x400]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res4[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res5[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res6[0x2000]; + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res7[128]; + ios83xx_t ios; /* Sequencer (IOS) */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res8[0x4A00]; + ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ + u8 res9[0x22000]; + security83xx_t security; + u8 res10[0xC0000]; + u8 qe[0x100000]; /* QE block */ +} immap_t; + +#elif defined(CONFIG_MPC832X) +typedef struct immap { + sysconf83xx_t sysconf; /* System configuration */ + wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk83xx_t rtc; /* Real Time Clock Module Registers */ + rtclk83xx_t pit; /* Periodic Interval Timer */ + gtm83xx_t gtm[2]; /* Global Timers Module */ + ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter83xx_t arbiter; /* System Arbiter Registers */ + reset83xx_t reset; /* Reset Module */ + clk83xx_t clk; /* System Clock Module */ + pmc83xx_t pmc; /* Power Management Control Module */ + qepi83xx_t qepi; /* QE Ports Interrupts Registers */ + u8 res0[0x300]; + u8 dll_ddr[0x100]; + u8 dll_lbc[0x100]; + u8 res1[0x200]; + qepio83xx_t qepio; /* QE Parallel I/O ports */ + u8 res2[0x800]; + ddr83xx_t ddr; /* DDR Memory Controller Memory */ + fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res3[0x1300]; + duart83xx_t duart[2]; /* DUART */ + u8 res4[0x900]; + lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res5[0x2000]; + dma83xx_t dma; /* DMA */ + pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ + u8 res6[128]; + ios83xx_t ios; /* Sequencer (IOS) */ + pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ + u8 res7[0x27A00]; + security83xx_t security; + u8 res8[0xC0000]; + u8 qe[0x100000]; /* QE block */ +} immap_t; +#endif + #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h index f38503206cc..950b9497f8a 100644 --- a/include/asm-ppc/immap_qe.h +++ b/include/asm-ppc/immap_qe.h @@ -547,4 +547,10 @@ typedef struct qe_immap { extern qe_map_t *qe_immr; +#if defined(CONFIG_MPC8360) +#define QE_MURAM_SIZE 0xc000UL +#elif defined(CONFIG_MPC832X) +#define QE_MURAM_SIZE 0x4000UL +#endif + #endif /* __IMMAP_QE_H__ */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h new file mode 100644 index 00000000000..cecb2258ffe --- /dev/null +++ b/include/configs/MPC832XEMDS.h @@ -0,0 +1,631 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83xx family */ +#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ +#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1 |\ + HRCWL_CE_PLL_VCO_DIV_2 |\ + HRCWL_CE_PLL_DIV_1X1 |\ + HRCWL_CE_TO_PLL_1X3) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#endif + +/* + * System IO Config + */ +#define CFG_SICRL 0x00000000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ + +#undef CONFIG_SPD_EEPROM +#if defined(CONFIG_SPD_EEPROM) +/* Determine DDR configuration from I2C interface + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ +#else +/* Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 128 /* MB */ +#define CFG_DDR_CS0_CONFIG 0x80840102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x3935d322 +#define CFG_DDR_TIMING_2 0x0f9048ca +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x44400232 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03200064 +#define CFG_DDR_CS0_BNDS 0x00000007 +#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ + +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * SDRAM on the Local Bus + */ +#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ + +/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON 0x0063b723 + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) + +#endif + +/* + * Windows to access PIB via local bus + */ +#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ +#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ + +/* + * CS2 on Local Bus, to PIB + */ +#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ +#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * CS3 on Local Bus, to PIB + */ +#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ +#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8323@0" +#define OF_SOC "soc8323@e0000000" +#define OF_QE "qe@e0100000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + + +#ifdef CONFIG_PCI + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "Freescale GETH" + +#define CONFIG_UEC_ETH1 /* ETH3 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ +#define CFG_UEC1_RX_CLK QE_CLK9 +#define CFG_UEC1_TX_CLK QE_CLK10 +#define CFG_UEC1_ETH_TYPE FAST_ETH +#define CFG_UEC1_PHY_ADDR 3 +#define CFG_UEC1_INTERFACE_MODE ENET_100_MII +#endif + +#define CONFIG_UEC_ETH2 /* ETH4 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 3 /* UCC4 */ +#define CFG_UEC2_RX_CLK QE_CLK7 +#define CFG_UEC2_TX_CLK QE_CLK8 +#define CFG_UEC2_ETH_TYPE FAST_ETH +#define CFG_UEC2_PHY_ADDR 4 +#define CFG_UEC2_INTERFACE_MODE ENET_100_MII +#endif + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_ETHADDR 00:04:9f:ef:03:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc832xemds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 5bed2d0a29f..0460be9e569 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -60,17 +60,6 @@ #endif #endif -#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) -#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ -#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ -#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ -#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ -#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ - | CFG_SCCR_TSEC1CM \ - | CFG_SCCR_TSEC2CM \ - | CFG_SCCR_ENCCM \ - | CFG_SCCR_USBCM ) - #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CFG_IMMR 0xE0000000 @@ -82,7 +71,7 @@ /* * DDR Setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ @@ -101,8 +90,15 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + #if defined(CONFIG_SPD_EEPROM) /* * Determine DDR configuration from I2C interface. @@ -113,6 +109,21 @@ * Manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS2_BNDS 0x0000000f +#define CFG_DDR_CS2_CONFIG 0x80330102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x38357322 +#define CFG_DDR_TIMING_2 0x2f9048c8 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47d00432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03cf0080 +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#else #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) #define CFG_DDR_TIMING_1 0x36332321 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ @@ -127,6 +138,7 @@ #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ #endif #endif +#endif /* * SDRAM on the Local Bus @@ -140,19 +152,20 @@ #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* flash size in MB */ +#define CFG_FLASH_SIZE 32 /* max flash size in MB */ /* #define CFG_FLASH_USE_BUFFER_WRITE */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ - -#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ @@ -197,7 +210,11 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ +/* + * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. + * if board has SRDAM on local bus, you can define CFG_LB_SDRAM + */ +#undef CFG_LB_SDRAM #ifdef CFG_LB_SDRAM /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ @@ -314,6 +331,7 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cbdbb2921db..37bbfb336d2 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -21,7 +21,7 @@ */ /* - MPC8349E-mITX board configuration file + MPC8349E-mITX and MPC8349E-mITX-GP board configuration file Memory map: @@ -31,11 +31,11 @@ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash + 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 - 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) - 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) + 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) + 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) I2C address list: Align. Board @@ -56,7 +56,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG +#if (TEXT_BASE == 0xFE000000) +#define CFG_LOWBOOT +#endif /* * High Level Configuration Options @@ -64,14 +66,26 @@ #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ -#define CONFIG_PCI +#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ + +/* On-board devices */ + +#ifdef CONFIG_MPC8349ITX #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ +#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ +#endif + +#define CONFIG_PCI #define CONFIG_RTC_DS1337 +#define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */ + +/* + * Device configurations + */ /* I2C */ -#define CONFIG_HARD_I2C - #ifdef CONFIG_HARD_I2C #define CONFIG_MISC_INIT_F @@ -111,120 +125,9 @@ #endif -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66666666 -#else -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif -#endif - -#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00003000 /* memtest region */ -#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ - -/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING -#define CFG_83XX_DDR_USES_CS0 - -#ifndef CONFIG_SPD_EEPROM -/* - * Manually set up DDR parameters - */ - #define CFG_DDR_SIZE 256 /* Mb */ - #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - - #define CFG_DDR_TIMING_1 0x26242321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ -#endif - -/* FLASH on the Local Bus */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ -#define CFG_FLASH_EMPTY_INFO - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) -#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ - -/* VSC7385 on the Local Bus */ -#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ - -#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) -#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ - OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ -#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ - -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ - -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ -#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ - OR_GPCM_SCY_9 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - +/* Compact Flash */ #ifdef CONFIG_COMPACT_FLASH -#define CFG_CF_BASE 0xF0000000 - -#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) - -#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ -#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ - -#undef CONFIG_IDE_RESET -#undef CONFIG_IDE_PREINIT - #define CFG_IDE_MAXBUS 1 #define CFG_IDE_MAXDEVICE 1 @@ -237,13 +140,108 @@ #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ -#endif - #define CONFIG_DOS_PARTITION -#define CFG_MID_FLASH_JUMP 0x7F000000 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#endif +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_83XX_DDR_USES_CS0 +#define CFG_MEMTEST_START 0x1000 /* memtest region */ +#define CFG_MEMTEST_END 0x2000 + +#ifdef CONFIG_HARD_I2C +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif + +#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ + #define CFG_DDR_SIZE 256 /* Mb */ + #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + + #define CFG_DDR_TIMING_1 0x26242321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ +#endif + +/* + *Flash on the Local Bus + */ + +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* The ITX has two flash chips, but the ITX-GP has only one. To support both +boards, we say we have two, but don't display a message if we find only one. */ +#define CFG_FLASH_QUIET_TEST +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ + +/* + * BRx, ORx, LBLAWBARx, and LBLAWARx + */ + +/* Flash */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385 + +#define CFG_VSC7385_BASE 0xF8000000 + +#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) +#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE +#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) + +#endif + +/* LED */ + +#define CFG_LED_BASE 0xF9000000 +#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +/* Compact Flash */ + +#ifdef CONFIG_COMPACT_FLASH + +#define CFG_CF_BASE 0xF0000000 + +#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) +#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) + +#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE +#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) + +#endif + +/* + * U-Boot memory configuration + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -253,10 +251,10 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -272,97 +270,9 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ - -#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ - OR_SDRAM_XAM | \ - ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ - ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ - OR_SDRAM_EAD) - #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - /* * Serial Port */ @@ -374,20 +284,16 @@ #define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_BAUDRATE 115200 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_BOARD_SETUP /* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 @@ -397,6 +303,9 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +/* + * PCI + */ #ifdef CONFIG_PCI #define CONFIG_MPC83XX_PCI2 @@ -447,14 +356,18 @@ #endif +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#endif + /* TSEC */ #ifdef CONFIG_TSEC_ENET -#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI -#endif - #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ @@ -468,6 +381,7 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_HAS_ETH1 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ @@ -479,14 +393,15 @@ #endif - /* * Environment */ +#define CONFIG_ENV_OVERWRITE + #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ @@ -533,16 +448,23 @@ /* Watchdog */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#ifdef CONFIG_WATCHDOG -#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 -#endif /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + #define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#ifdef CONFIG_MPC8349ITX +#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ +#endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -562,15 +484,15 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ +/* + * Cache Configuration + */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ #endif -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ @@ -578,12 +500,12 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1) -#ifdef PCI_64BIT +#ifdef CFG_LOWBOOT #define CFG_HRCW_HIGH (\ HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ + HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -596,7 +518,7 @@ HRCWH_PCI_HOST |\ HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -606,30 +528,32 @@ HRCWH_TSEC2M_IN_GMII ) #endif -/* System performance */ +/* + * System performance + */ #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ -/* System IO Config */ +/* + * System IO Config + */ #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) -#define CFG_HID0_INIT 0x000000000 - -#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE -/* DDR @ 0x00000000 */ +/* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* PCI @ 0x80000000 */ +/* PCI */ #ifdef CONFIG_PCI #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -706,97 +630,72 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 -#define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif -#if 1 -#define CONFIG_IPADDR 10.82.19.159 -#define CONFIG_SERVERIP 10.82.48.106 -#define CONFIG_GATEWAYIP 10.82.19.254 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs -#define CONFIG_BOOTFILE timur/uImage - -#define CONFIG_UBOOTPATH timur/u-boot.bin -#else #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_NETDEV eth0 +#ifdef CONFIG_MPC8349ITX #define CONFIG_HOSTNAME mpc8349emitx +#else +#define CONFIG_HOSTNAME mpc8349emitxgp +#endif + +/* Default path and filenames */ #define CONFIG_ROOTPATH /nfsroot/rootfs #define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH u-boot.bin -#endif - -#define CONFIG_UBOOTSTART fe700000 -#define CONFIG_UBOOTEND fe77ffff - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BAUDRATE 115200 - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTDELAY 6 +#ifdef CONFIG_MPC8349ITX +#define CONFIG_FDTFILE mpc8349emitx.dtb #else -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ +#define CONFIG_FDTFILE mpc8349emitxgp.dtb #endif +#define CONFIG_BOOTDELAY 0 + #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=ttyS0," MK_STR(CONFIG_BAUDRATE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ - "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "protect off FEF00000 FEF7FFFF; " \ - "erase FEF00000 FEF7FFFF; " \ - "cp.b $loadaddr FEF00000 $filesize; " \ - "protect on FEF00000 FEF7FFFF; " \ - "cmp.b $loadaddr FEF00000 $filesize\0" \ - "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ - "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ - "fdtfile=mpc8349emitx.dtb\0" \ - "" + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" #define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ + " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - + "setenv bootargs root=/dev/ram rw" \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #undef MK_STR #undef XMK_STR diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 8ad6551de73..d2af0e1dfc4 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -100,12 +100,19 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CFG_83XX_DDR_USES_CS0 -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #if defined(CONFIG_SPD_EEPROM) /* @@ -117,6 +124,21 @@ * Manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG 0x80330102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x38357322 +#define CFG_DDR_TIMING_2 0x2f9048c8 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47d00432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03cf0080 +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#else #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) #define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ #define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ @@ -124,6 +146,7 @@ #define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ #define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ #endif +#endif /* * Memory test @@ -168,7 +191,7 @@ #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ +#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ @@ -176,10 +199,12 @@ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ -#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM @@ -188,7 +213,7 @@ */ #define CFG_BCSR 0xF8000000 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ -#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ +#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */ #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ @@ -278,8 +303,8 @@ /* * Windows to access PIB via local bus */ -#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ -#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ +#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */ +#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */ /* * CS4 on Local Bus, to PIB @@ -309,6 +334,7 @@ #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER @@ -324,6 +350,7 @@ #define OF_CPU "PowerPC,8360@0" #define OF_SOC "soc8360@e0000000" +#define OF_QE "qe@e0100000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" @@ -609,7 +636,7 @@ "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ "fdtaddr=400000\0" \ - "fdtfile=mpc8349emds.dtb\0" \ + "fdtfile=mpc8360emds.dtb\0" \ "" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 728083b304c..ed0357791b4 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -57,17 +57,6 @@ */ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) -#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) -#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ -#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ -#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ -#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ -#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ - | CFG_SCCR_TSEC1CM \ - | CFG_SCCR_TSEC2CM \ - | CFG_SCCR_ENCCM \ - | CFG_SCCR_USBCM ) - /* board pre init: do not call, nothing to do */ #undef CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h new file mode 100644 index 00000000000..65aac5cefd3 --- /dev/null +++ b/include/configs/sbc8349.h @@ -0,0 +1,734 @@ +/* + * WindRiver SBC8349 U-Boot configuration file. + * Copyright (c) 2006, 2007 Wind River Systems, Inc. + * + * Paul Gortmaker + * Based on the MPC8349EMDS config. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * sbc8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC834X 1 /* MPC834X family */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ +#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ + +#undef CONFIG_PCI +/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ + +#else +/* + * Manually set up DDR parameters + * NB: manual DDR setup untested on sbc834x + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CFG_DDR_TIMING_1 0x36332321 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ +#else +/* the default burst length is 4 - for 64-bit data path */ +#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ +/* #define CFG_FLASH_USE_BUFFER_WRITE */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + BR_V) /* valid */ + +#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#undef CFG_LB_SDRAM /* if board has SDRAM on local bus */ + +#ifdef CFG_LB_SDRAM +/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + +#define CFG_OR2_PRELIM 0xFC006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8349@0" +#define OF_SOC "soc8349@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C1_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 +#define CFG_I2C_OFFSET CFG_I2C2_OFFSET +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE 0xB0000000 +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xE2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_64BIT +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_BCM5421S 1 +#define TSEC1_PHY_ADDR 0x19 +#define TSEC2_PHY_ADDR 0x1a +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#if 1 /*528/264*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*396/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_3X1) +#elif 0 /*264/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*132/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#elif 0 /*264/264 */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#endif + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK + +/* #define CFG_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST ) */ + + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT1L (0) +#define CFG_IBAT1U (0) +#define CFG_IBAT2L (0) +#define CFG_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e +#endif + +#define CONFIG_IPADDR 192.168.1.234 + +#define CONFIG_HOSTNAME SBC8349 +#define CONFIG_ROOTPATH /tftpboot/rootfs +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=sbc8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "fdtaddr=400000\0" \ + "fdtfile=sbc8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 03dd0cafd2d..c2a4ff58774 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -10,12 +10,6 @@ * the License, or (at your option) any later version. */ -/* - * mpc83xx.h - * - * MPC83xx specific definitions - */ - #ifndef __MPC83XX_H__ #define __MPC83XX_H__ @@ -24,406 +18,1005 @@ #include #endif -/* - * MPC83xx cpu provide RCR register to do reset thing specially. easier - * to implement +/* MPC83xx cpu provide RCR register to do reset thing specially */ - #define MPC83xx_RESET -/* - * System reset offset (PowerPC standard) +/* System reset offset (PowerPC standard) */ -#define EXC_OFF_SYS_RESET 0x0100 +#define EXC_OFF_SYS_RESET 0x0100 -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* IMMRBAR - Internal Memory Register Base Address */ -#define CONFIG_DEFAULT_IMMR 0xFF400000 +#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#define IMMRBAR 0x0000 /* Register offset to immr */ +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) -/* - * Watchdog +/* LAWBAR - Local Access Window Base Address Register */ -#define SWCRR 0x0204 -#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ -#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ -#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ -#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ -#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) +#define LBLAWBAR0 0x0020 /* Register offset to immr */ +#define LBLAWAR0 0x0024 +#define LBLAWBAR1 0x0028 +#define LBLAWAR1 0x002C +#define LBLAWBAR2 0x0030 +#define LBLAWAR2 0x0034 +#define LBLAWBAR3 0x0038 +#define LBLAWAR3 0x003C +#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ -#define SWCNR 0x0208 -#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. -#define SWCNR_RES ~(SWCNR_SWCN) - -#define SWSRR 0x020E - -/* - * Default Internal Memory Register Space (Freescale recomandation) +/* SPRIDR - System Part and Revision ID Register */ -#define IMMRBAR 0x0000 -#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ -#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ -/* - * Default Internal Memory Register Space (Freescale recomandation) +#define SPR_8349E_REV10 0x80300100 +#define SPR_8349_REV10 0x80310100 +#define SPR_8347E_REV10_TBGA 0x80320100 +#define SPR_8347_REV10_TBGA 0x80330100 +#define SPR_8347E_REV10_PBGA 0x80340100 +#define SPR_8347_REV10_PBGA 0x80350100 +#define SPR_8343E_REV10 0x80360100 +#define SPR_8343_REV10 0x80370100 + +#define SPR_8349E_REV11 0x80300101 +#define SPR_8349_REV11 0x80310101 +#define SPR_8347E_REV11_TBGA 0x80320101 +#define SPR_8347_REV11_TBGA 0x80330101 +#define SPR_8347E_REV11_PBGA 0x80340101 +#define SPR_8347_REV11_PBGA 0x80350101 +#define SPR_8343E_REV11 0x80360101 +#define SPR_8343_REV11 0x80370101 + +#define SPR_8349E_REV31 0x80300300 +#define SPR_8349_REV31 0x80310300 +#define SPR_8347E_REV31_TBGA 0x80320300 +#define SPR_8347_REV31_TBGA 0x80330300 +#define SPR_8347E_REV31_PBGA 0x80340300 +#define SPR_8347_REV31_PBGA 0x80350300 +#define SPR_8343E_REV31 0x80360300 +#define SPR_8343_REV31 0x80370300 + +#define SPR_8360E_REV10 0x80480010 +#define SPR_8360_REV10 0x80490010 +#define SPR_8360E_REV11 0x80480011 +#define SPR_8360_REV11 0x80490011 +#define SPR_8360E_REV12 0x80480012 +#define SPR_8360_REV12 0x80490012 +#define SPR_8360E_REV20 0x80480020 +#define SPR_8360_REV20 0x80490020 + +#define SPR_8323E_REV10 0x80620010 +#define SPR_8323_REV10 0x80630010 +#define SPR_8321E_REV10 0x80660010 +#define SPR_8321_REV10 0x80670010 +#define SPR_8323E_REV11 0x80620011 +#define SPR_8323_REV11 0x80630011 +#define SPR_8321E_REV11 0x80660011 +#define SPR_8321_REV11 0x80670011 + +/* SPCR - System Priority Configuration Register */ -#define LBLAWBAR0 0x0020 -#define LBLAWAR0 0x0024 -#define LBLAWBAR1 0x0028 -#define LBLAWAR1 0x002C -#define LBLAWBAR2 0x0030 -#define LBLAWAR2 0x0034 -#define LBLAWBAR3 0x0038 -#define LBLAWAR3 0x003C +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ +#define SPCR_PCIHPE_SHIFT (31-3) +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ +#define SPCR_PCIPR_SHIFT (31-7) +#define SPCR_OPT 0x00800000 /* Optimize */ +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ +#define SPCR_TBEN_SHIFT (31-9) +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ +#define SPCR_COREPR_SHIFT (31-11) -/* - * The device ID and revision numbers - */ -#define SPR_8349E_REV10 0x80300100 -#define SPR_8349_REV10 0x80310100 -#define SPR_8347E_REV10_TBGA 0x80320100 -#define SPR_8347_REV10_TBGA 0x80330100 -#define SPR_8347E_REV10_PBGA 0x80340100 -#define SPR_8347_REV10_PBGA 0x80350100 -#define SPR_8343E_REV10 0x80360100 -#define SPR_8343_REV10 0x80370100 - -#define SPR_8349E_REV11 0x80300101 -#define SPR_8349_REV11 0x80310101 -#define SPR_8347E_REV11_TBGA 0x80320101 -#define SPR_8347_REV11_TBGA 0x80330101 -#define SPR_8347E_REV11_PBGA 0x80340101 -#define SPR_8347_REV11_PBGA 0x80350101 -#define SPR_8343E_REV11 0x80360101 -#define SPR_8343_REV11 0x80370101 - -#define SPR_8360E_REV10 0x80480010 -#define SPR_8360_REV10 0x80490010 -#define SPR_8360E_REV11 0x80480011 -#define SPR_8360_REV11 0x80490011 -#define SPR_8360E_REV12 0x80480012 -#define SPR_8360_REV12 0x80490012 - -/* - * Base Registers & Option Registers - */ -#define BR0 0x5000 -#define BR1 0x5008 -#define BR2 0x5010 -#define BR3 0x5018 -#define BR4 0x5020 -#define BR5 0x5028 -#define BR6 0x5030 -#define BR7 0x5038 - -#define BR_BA 0xFFFF8000 -#define BR_BA_SHIFT 15 -#define BR_PS 0x00001800 -#define BR_PS_SHIFT 11 -#define BR_PS_8 0x00000800 /* Port Size 8 bit */ -#define BR_PS_16 0x00001000 /* Port Size 16 bit */ -#define BR_PS_32 0x00001800 /* Port Size 32 bit */ -#define BR_DECC 0x00000600 -#define BR_DECC_SHIFT 9 -#define BR_WP 0x00000100 -#define BR_WP_SHIFT 8 -#define BR_MSEL 0x000000E0 -#define BR_MSEL_SHIFT 5 -#define BR_MS_GPCM 0x00000000 /* GPCM */ -#define BR_MS_SDRAM 0x00000060 /* SDRAM */ -#define BR_MS_UPMA 0x00000080 /* UPMA */ -#define BR_MS_UPMB 0x000000A0 /* UPMB */ -#define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if defined (CONFIG_MPC8360) -#define BR_ATOM 0x0000000C -#define BR_ATOM_SHIFT 2 -#endif -#define BR_V 0x00000001 -#define BR_V_SHIFT 0 -#if defined (CONFIG_MPC8349) -#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) -#elif defined (CONFIG_MPC8360) -#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) +#if defined(CONFIG_MPC834X) +/* SPCR bits - MPC8349 specific */ +#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ +#define SPCR_TSEC1DP_SHIFT (31-19) +#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ +#define SPCR_TSEC1BDP_SHIFT (31-21) +#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ +#define SPCR_TSEC1EP_SHIFT (31-23) +#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ +#define SPCR_TSEC2DP_SHIFT (31-27) +#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ +#define SPCR_TSEC2BDP_SHIFT (31-29) +#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ +#define SPCR_TSEC2EP_SHIFT (31-31) #endif -#define OR0 0x5004 -#define OR1 0x500C -#define OR2 0x5014 -#define OR3 0x501C -#define OR4 0x5024 -#define OR5 0x502C -#define OR6 0x5034 -#define OR7 0x503C +/* SICRL/H - System I/O Configuration Register Low/High + */ +#if defined(CONFIG_MPC834X) +/* SICRL bits - MPC8349 specific */ +#define SICRL_LDP_A 0x80000000 +#define SICRL_USB1 0x40000000 +#define SICRL_USB0 0x20000000 +#define SICRL_UART 0x0C000000 +#define SICRL_GPIO1_A 0x02000000 +#define SICRL_GPIO1_B 0x01000000 +#define SICRL_GPIO1_C 0x00800000 +#define SICRL_GPIO1_D 0x00400000 +#define SICRL_GPIO1_E 0x00200000 +#define SICRL_GPIO1_F 0x00180000 +#define SICRL_GPIO1_G 0x00040000 +#define SICRL_GPIO1_H 0x00020000 +#define SICRL_GPIO1_I 0x00010000 +#define SICRL_GPIO1_J 0x00008000 +#define SICRL_GPIO1_K 0x00004000 +#define SICRL_GPIO1_L 0x00003000 -#define OR_GPCM_AM 0xFFFF8000 +/* SICRH bits - MPC8349 specific */ +#define SICRH_DDR 0x80000000 +#define SICRH_TSEC1_A 0x10000000 +#define SICRH_TSEC1_B 0x08000000 +#define SICRH_TSEC1_C 0x04000000 +#define SICRH_TSEC1_D 0x02000000 +#define SICRH_TSEC1_E 0x01000000 +#define SICRH_TSEC1_F 0x00800000 +#define SICRH_TSEC2_A 0x00400000 +#define SICRH_TSEC2_B 0x00200000 +#define SICRH_TSEC2_C 0x00100000 +#define SICRH_TSEC2_D 0x00080000 +#define SICRH_TSEC2_E 0x00040000 +#define SICRH_TSEC2_F 0x00020000 +#define SICRH_TSEC2_G 0x00010000 +#define SICRH_TSEC2_H 0x00008000 +#define SICRH_GPIO2_A 0x00004000 +#define SICRH_GPIO2_B 0x00002000 +#define SICRH_GPIO2_C 0x00001000 +#define SICRH_GPIO2_D 0x00000800 +#define SICRH_GPIO2_E 0x00000400 +#define SICRH_GPIO2_F 0x00000200 +#define SICRH_GPIO2_G 0x00000180 +#define SICRH_GPIO2_H 0x00000060 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 + +#elif defined(CONFIG_MPC8360) +/* SICRL bits - MPC8360 specific */ +#define SICRL_LDP_A 0xC0000000 +#define SICRL_LCLK_1 0x10000000 +#define SICRL_LCLK_2 0x08000000 +#define SICRL_SRCID_A 0x03000000 +#define SICRL_IRQ_CKSTP_A 0x00C00000 + +/* SICRH bits - MPC8360 specific */ +#define SICRH_DDR 0x80000000 +#define SICRH_SECONDARY_DDR 0x40000000 +#define SICRH_SDDROE 0x20000000 +#define SICRH_IRQ3 0x10000000 +#define SICRH_UC1EOBI 0x00000004 +#define SICRH_UC2E1OBI 0x00000002 +#define SICRH_UC2E2OBI 0x00000001 + +#elif defined(CONFIG_MPC832X) +/* SICRL bits - MPC832X specific */ +#define SICRL_LDP_LCS_A 0x80000000 +#define SICRL_IRQ_CKS 0x20000000 +#define SICRL_PCI_MSRC 0x10000000 +#define SICRL_URT_CTPR 0x06000000 +#define SICRL_IRQ_CTPR 0x00C00000 +#endif + +/* SWCRR - System Watchdog Control Register + */ +#define SWCRR 0x0204 /* Register offset to immr */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ +#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + +/* SWCNR - System Watchdog Counter Register + */ +#define SWCNR 0x0208 /* Register offset to immr */ +#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ +#define SWCNR_RES ~(SWCNR_SWCN) + +/* SWSRR - System Watchdog Service Register + */ +#define SWSRR 0x020E /* Register offset to immr */ + +/* ACR - Arbiter Configuration Register + */ +#define ACR_COREDIS 0x10000000 /* Core disable */ +#define ACR_COREDIS_SHIFT (31-7) +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ +#define ACR_PIPE_DEP_SHIFT (31-15) +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ +#define ACR_PCI_RPTCNT_SHIFT (31-19) +#define ACR_RPTCNT 0x00000700 /* Repeat count */ +#define ACR_RPTCNT_SHIFT (31-23) +#define ACR_APARK 0x00000030 /* Address parking */ +#define ACR_APARK_SHIFT (31-27) +#define ACR_PARKM 0x0000000F /* Parking master */ +#define ACR_PARKM_SHIFT (31-31) + +/* ATR - Arbiter Timers Register + */ +#define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_ATO 0x000000FF /* Address time out */ + +/* AER - Arbiter Event Register + */ +#define AER_ETEA 0x00000020 /* Transfer error */ +#define AER_RES 0x00000010 /* Reserved transfer type */ +#define AER_ECW 0x00000008 /* External control word transfer type */ +#define AER_AO 0x00000004 /* Address Only transfer type */ +#define AER_DTO 0x00000002 /* Data time out */ +#define AER_ATO 0x00000001 /* Address time out */ + +/* AEATR - Arbiter Event Address Register + */ +#define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type */ + +/* HRCWL - Hard Reset Configuration Word Low + */ +#define HRCWL_LBIUCM 0x80000000 +#define HRCWL_LBIUCM_SHIFT 31 +#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 + +#define HRCWL_DDRCM 0x40000000 +#define HRCWL_DDRCM_SHIFT 30 +#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 +#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 + +#define HRCWL_SPMF 0x0f000000 +#define HRCWL_SPMF_SHIFT 24 +#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 +#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 +#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 +#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 +#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 +#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 +#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 +#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 +#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 +#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 +#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 +#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 +#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 +#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 +#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 +#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 + +#define HRCWL_VCO_BYPASS 0x00000000 +#define HRCWL_VCO_1X2 0x00000000 +#define HRCWL_VCO_1X4 0x00200000 +#define HRCWL_VCO_1X8 0x00400000 + +#define HRCWL_COREPLL 0x007F0000 +#define HRCWL_COREPLL_SHIFT 16 +#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 +#define HRCWL_CORE_TO_CSB_1X1 0x00020000 +#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 +#define HRCWL_CORE_TO_CSB_2X1 0x00040000 +#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 +#define HRCWL_CORE_TO_CSB_3X1 0x00060000 + +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#define HRCWL_CEVCOD 0x000000C0 +#define HRCWL_CEVCOD_SHIFT 6 +#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 +#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 +#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 + +#define HRCWL_CEPDF 0x00000020 +#define HRCWL_CEPDF_SHIFT 5 +#define HRCWL_CE_PLL_DIV_1X1 0x00000000 +#define HRCWL_CE_PLL_DIV_2X1 0x00000020 + +#define HRCWL_CEPMF 0x0000001F +#define HRCWL_CEPMF_SHIFT 0 +#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 +#define HRCWL_CE_TO_PLL_1X2 0x00000002 +#define HRCWL_CE_TO_PLL_1X3 0x00000003 +#define HRCWL_CE_TO_PLL_1X4 0x00000004 +#define HRCWL_CE_TO_PLL_1X5 0x00000005 +#define HRCWL_CE_TO_PLL_1X6 0x00000006 +#define HRCWL_CE_TO_PLL_1X7 0x00000007 +#define HRCWL_CE_TO_PLL_1X8 0x00000008 +#define HRCWL_CE_TO_PLL_1X9 0x00000009 +#define HRCWL_CE_TO_PLL_1X10 0x0000000A +#define HRCWL_CE_TO_PLL_1X11 0x0000000B +#define HRCWL_CE_TO_PLL_1X12 0x0000000C +#define HRCWL_CE_TO_PLL_1X13 0x0000000D +#define HRCWL_CE_TO_PLL_1X14 0x0000000E +#define HRCWL_CE_TO_PLL_1X15 0x0000000F +#define HRCWL_CE_TO_PLL_1X16 0x00000010 +#define HRCWL_CE_TO_PLL_1X17 0x00000011 +#define HRCWL_CE_TO_PLL_1X18 0x00000012 +#define HRCWL_CE_TO_PLL_1X19 0x00000013 +#define HRCWL_CE_TO_PLL_1X20 0x00000014 +#define HRCWL_CE_TO_PLL_1X21 0x00000015 +#define HRCWL_CE_TO_PLL_1X22 0x00000016 +#define HRCWL_CE_TO_PLL_1X23 0x00000017 +#define HRCWL_CE_TO_PLL_1X24 0x00000018 +#define HRCWL_CE_TO_PLL_1X25 0x00000019 +#define HRCWL_CE_TO_PLL_1X26 0x0000001A +#define HRCWL_CE_TO_PLL_1X27 0x0000001B +#define HRCWL_CE_TO_PLL_1X28 0x0000001C +#define HRCWL_CE_TO_PLL_1X29 0x0000001D +#define HRCWL_CE_TO_PLL_1X30 0x0000001E +#define HRCWL_CE_TO_PLL_1X31 0x0000001F +#endif + +/* HRCWH - Hardware Reset Configuration Word High + */ +#define HRCWH_PCI_HOST 0x80000000 +#define HRCWH_PCI_HOST_SHIFT 31 +#define HRCWH_PCI_AGENT 0x00000000 + +#if defined(CONFIG_MPC834X) +#define HRCWH_32_BIT_PCI 0x00000000 +#define HRCWH_64_BIT_PCI 0x40000000 +#endif + +#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 + +#define HRCWH_PCI_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI_ARBITER_ENABLE 0x20000000 + +#if defined(CONFIG_MPC834X) +#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 +#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 + +#elif defined(CONFIG_MPC8360) +#define HRCWH_PCICKDRV_DISABLE 0x00000000 +#define HRCWH_PCICKDRV_ENABLE 0x10000000 +#endif + +#define HRCWH_CORE_DISABLE 0x08000000 +#define HRCWH_CORE_ENABLE 0x00000000 + +#define HRCWH_FROM_0X00000100 0x00000000 +#define HRCWH_FROM_0XFFF00100 0x04000000 + +#define HRCWH_BOOTSEQ_DISABLE 0x00000000 +#define HRCWH_BOOTSEQ_NORMAL 0x01000000 +#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 + +#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 +#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 + +#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 +#define HRCWH_ROM_LOC_PCI1 0x00100000 +#if defined(CONFIG_MPC834X) +#define HRCWH_ROM_LOC_PCI2 0x00200000 +#endif +#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 +#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 +#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 + +#if defined(CONFIG_MPC834X) +#define HRCWH_TSEC1M_IN_RGMII 0x00000000 +#define HRCWH_TSEC1M_IN_RTBI 0x00004000 +#define HRCWH_TSEC1M_IN_GMII 0x00008000 +#define HRCWH_TSEC1M_IN_TBI 0x0000C000 +#define HRCWH_TSEC2M_IN_RGMII 0x00000000 +#define HRCWH_TSEC2M_IN_RTBI 0x00001000 +#define HRCWH_TSEC2M_IN_GMII 0x00002000 +#define HRCWH_TSEC2M_IN_TBI 0x00003000 +#endif + +#if defined(CONFIG_MPC8360) +#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 +#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 +#endif + +#define HRCWH_BIG_ENDIAN 0x00000000 +#define HRCWH_LITTLE_ENDIAN 0x00000008 + +#define HRCWH_LALE_NORMAL 0x00000000 +#define HRCWH_LALE_EARLY 0x00000004 + +#define HRCWH_LDP_SET 0x00000000 +#define HRCWH_LDP_CLEAR 0x00000002 + +/* RSR - Reset Status Register + */ +#define RSR_RSTSRC 0xE0000000 /* Reset source */ +#define RSR_RSTSRC_SHIFT 29 +#define RSR_BSF 0x00010000 /* Boot seq. fail */ +#define RSR_BSF_SHIFT 16 +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ + RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ + RSR_BMRS | RSR_SRS | RSR_HRS) +/* RMR - Reset Mode Register + */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + +/* RCR - Reset Control Register + */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + +/* RCER - Reset Control Enable Register + */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + +/* SPMR - System PLL Mode Register + */ +#define SPMR_LBIUCM 0x80000000 +#define SPMR_DDRCM 0x40000000 +#define SPMR_SPMF 0x0F000000 +#define SPMR_CKID 0x00800000 +#define SPMR_CKID_SHIFT 23 +#define SPMR_COREPLL 0x007F0000 +#define SPMR_CEVCOD 0x000000C0 +#define SPMR_CEPDF 0x00000020 +#define SPMR_CEPMF 0x0000001F + +/* OCCR - Output Clock Control Register + */ +#define OCCR_PCICOE0 0x80000000 +#define OCCR_PCICOE1 0x40000000 +#define OCCR_PCICOE2 0x20000000 +#define OCCR_PCICOE3 0x10000000 +#define OCCR_PCICOE4 0x08000000 +#define OCCR_PCICOE5 0x04000000 +#define OCCR_PCICOE6 0x02000000 +#define OCCR_PCICOE7 0x01000000 +#define OCCR_PCICD0 0x00800000 +#define OCCR_PCICD1 0x00400000 +#define OCCR_PCICD2 0x00200000 +#define OCCR_PCICD3 0x00100000 +#define OCCR_PCICD4 0x00080000 +#define OCCR_PCICD5 0x00040000 +#define OCCR_PCICD6 0x00020000 +#define OCCR_PCICD7 0x00010000 +#define OCCR_PCI1CR 0x00000002 +#define OCCR_PCI2CR 0x00000001 +#define OCCR_PCICR OCCR_PCI1CR + +/* SCCR - System Clock Control Register + */ +#define SCCR_ENCCM 0x03000000 +#define SCCR_ENCCM_SHIFT 24 +#define SCCR_ENCCM_0 0x00000000 +#define SCCR_ENCCM_1 0x01000000 +#define SCCR_ENCCM_2 0x02000000 +#define SCCR_ENCCM_3 0x03000000 + +#define SCCR_PCICM 0x00010000 +#define SCCR_PCICM_SHIFT 16 + +/* SCCR bits - MPC8349 specific */ +#ifdef CONFIG_MPC834X +#define SCCR_TSEC1CM 0xc0000000 +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 +#define SCCR_TSEC1CM_1 0x40000000 +#define SCCR_TSEC1CM_2 0x80000000 +#define SCCR_TSEC1CM_3 0xC0000000 + +#define SCCR_TSEC2CM 0x30000000 +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_TSEC2CM_0 0x00000000 +#define SCCR_TSEC2CM_1 0x10000000 +#define SCCR_TSEC2CM_2 0x20000000 +#define SCCR_TSEC2CM_3 0x30000000 +#endif + +#define SCCR_USBMPHCM 0x00c00000 +#define SCCR_USBMPHCM_SHIFT 22 +#define SCCR_USBDRCM 0x00300000 +#define SCCR_USBDRCM_SHIFT 20 + +#define SCCR_USBCM_0 0x00000000 +#define SCCR_USBCM_1 0x00500000 +#define SCCR_USBCM_2 0x00A00000 +#define SCCR_USBCM_3 0x00F00000 + +/* CSn_BDNS - Chip Select memory Bounds Register + */ +#define CSBNDS_SA 0x00FF0000 +#define CSBNDS_SA_SHIFT 8 +#define CSBNDS_EA 0x000000FF +#define CSBNDS_EA_SHIFT 24 + +/* CSn_CONFIG - Chip Select Configuration Register + */ +#define CSCONFIG_EN 0x80000000 +#define CSCONFIG_AP 0x00800000 +#define CSCONFIG_ROW_BIT 0x00000700 +#define CSCONFIG_ROW_BIT_12 0x00000000 +#define CSCONFIG_ROW_BIT_13 0x00000100 +#define CSCONFIG_ROW_BIT_14 0x00000200 +#define CSCONFIG_COL_BIT 0x00000007 +#define CSCONFIG_COL_BIT_8 0x00000000 +#define CSCONFIG_COL_BIT_9 0x00000001 +#define CSCONFIG_COL_BIT_10 0x00000002 +#define CSCONFIG_COL_BIT_11 0x00000003 + +/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 + */ +#define TIMING_CFG1_PRETOACT 0x70000000 +#define TIMING_CFG1_PRETOACT_SHIFT 28 +#define TIMING_CFG1_ACTTOPRE 0x0F000000 +#define TIMING_CFG1_ACTTOPRE_SHIFT 24 +#define TIMING_CFG1_ACTTORW 0x00700000 +#define TIMING_CFG1_ACTTORW_SHIFT 20 +#define TIMING_CFG1_CASLAT 0x00070000 +#define TIMING_CFG1_CASLAT_SHIFT 16 +#define TIMING_CFG1_REFREC 0x0000F000 +#define TIMING_CFG1_REFREC_SHIFT 12 +#define TIMING_CFG1_WRREC 0x00000700 +#define TIMING_CFG1_WRREC_SHIFT 8 +#define TIMING_CFG1_ACTTOACT 0x00000070 +#define TIMING_CFG1_ACTTOACT_SHIFT 4 +#define TIMING_CFG1_WRTORD 0x00000007 +#define TIMING_CFG1_WRTORD_SHIFT 0 +#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ +#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ + +/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 + */ +#define TIMING_CFG2_CPO 0x0F800000 +#define TIMING_CFG2_CPO_SHIFT 23 +#define TIMING_CFG2_ACSM 0x00080000 +#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 +#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 + +/* DDR_SDRAM_MODE - DDR SDRAM Mode Register + */ +#define SDRAM_MODE_ESD 0xFFFF0000 +#define SDRAM_MODE_ESD_SHIFT 16 +#define SDRAM_MODE_SD 0x0000FFFF +#define SDRAM_MODE_SD_SHIFT 0 +#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ +#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +#define DDR_MODE_MODEREG 0x0000 /* select mode register */ + +/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register + */ +#define SDRAM_INTERVAL_REFINT 0x3FFF0000 +#define SDRAM_INTERVAL_REFINT_SHIFT 16 +#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF +#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 + +/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register + */ +#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 + +/* ECC_ERR_INJECT - Memory data path error injection mask ECC + */ +#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ +#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ +#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ +#define ECC_ERR_INJECT_EEIM_SHIFT 0 + +/* CAPTURE_ECC - Memory data path read capture ECC + */ +#define CAPTURE_ECC_ECE (0xff000000>>24) +#define CAPTURE_ECC_ECE_SHIFT 0 + +/* ERR_DETECT - Memory error detect + */ +#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ +#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ +#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ +#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ + +/* ERR_DISABLE - Memory error disable + */ +#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ +#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ +#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ +#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ + ECC_ERROR_DISABLE_MBED) +/* ERR_INT_EN - Memory error interrupt enable + */ +#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ +#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ + ECC_ERR_INT_EN_MSEE) +/* CAPTURE_ATTRIBUTES - Memory error attributes capture + */ +#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ +#define ECC_CAPT_ATTR_BNUM_SHIFT 28 +#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ +#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 +#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 +#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 +#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 +#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 +#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ +#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 +#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 +#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 +#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 +#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) +#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 +#define ECC_CAPT_ATTR_TSRC_I2C 0x9 +#define ECC_CAPT_ATTR_TSRC_JTAG 0xA +#define ECC_CAPT_ATTR_TSRC_PCI1 0xD +#define ECC_CAPT_ATTR_TSRC_PCI2 0xE +#define ECC_CAPT_ATTR_TSRC_DMA 0xF +#define ECC_CAPT_ATTR_TSRC_SHIFT 16 +#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ +#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 +#define ECC_CAPT_ATTR_TTYP_READ 0x2 +#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 +#define ECC_CAPT_ATTR_TTYP_SHIFT 12 +#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ + +/* ERR_SBE - Single bit ECC memory error management + */ +#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ +#define ECC_ERROR_MAN_SBET_SHIFT 16 +#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ +#define ECC_ERROR_MAN_SBEC_SHIFT 0 + +/* BR - Base Registers + */ +#define BR0 0x5000 /* Register offset to immr */ +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) +#define BR_ATOM 0x0000000C +#define BR_ATOM_SHIFT 2 +#endif +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 + +#if defined(CONFIG_MPC834X) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) +#elif defined(CONFIG_MPC8360) +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) +#endif + +/* OR - Option Registers + */ +#define OR0 0x5004 /* Register offset to immr */ +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 #define OR_GPCM_AM_SHIFT 15 -#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD 0x00001000 #define OR_GPCM_BCTLD_SHIFT 12 -#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT 0x00000800 #define OR_GPCM_CSNT_SHIFT 11 -#define OR_GPCM_ACS 0x00000600 -#define OR_GPCM_ACS_SHIFT 9 -#define OR_GPCM_ACS_0b10 0x00000400 -#define OR_GPCM_ACS_0b11 0x00000600 -#define OR_GPCM_XACS 0x00000100 -#define OR_GPCM_XACS_SHIFT 8 -#define OR_GPCM_SCY 0x000000F0 -#define OR_GPCM_SCY_SHIFT 4 -#define OR_GPCM_SCY_1 0x00000010 -#define OR_GPCM_SCY_2 0x00000020 -#define OR_GPCM_SCY_3 0x00000030 -#define OR_GPCM_SCY_4 0x00000040 -#define OR_GPCM_SCY_5 0x00000050 -#define OR_GPCM_SCY_6 0x00000060 -#define OR_GPCM_SCY_7 0x00000070 -#define OR_GPCM_SCY_8 0x00000080 -#define OR_GPCM_SCY_9 0x00000090 -#define OR_GPCM_SCY_10 0x000000a0 -#define OR_GPCM_SCY_11 0x000000b0 -#define OR_GPCM_SCY_12 0x000000c0 -#define OR_GPCM_SCY_13 0x000000d0 -#define OR_GPCM_SCY_14 0x000000e0 -#define OR_GPCM_SCY_15 0x000000f0 -#define OR_GPCM_SETA 0x00000008 -#define OR_GPCM_SETA_SHIFT 3 -#define OR_GPCM_TRLX 0x00000004 -#define OR_GPCM_TRLX_SHIFT 2 -#define OR_GPCM_EHTR 0x00000002 -#define OR_GPCM_EHTR_SHIFT 1 -#define OR_GPCM_EAD 0x00000001 -#define OR_GPCM_EAD_SHIFT 0 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_0b10 0x00000400 +#define OR_GPCM_ACS_0b11 0x00000600 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 -#define OR_UPM_AM 0xFFFF8000 -#define OR_UPM_AM_SHIFT 15 -#define OR_UPM_XAM 0x00006000 -#define OR_UPM_XAM_SHIFT 13 -#define OR_UPM_BCTLD 0x00001000 -#define OR_UPM_BCTLD_SHIFT 12 -#define OR_UPM_BI 0x00000100 -#define OR_UPM_BI_SHIFT 8 -#define OR_UPM_TRLX 0x00000004 -#define OR_UPM_TRLX_SHIFT 2 -#define OR_UPM_EHTR 0x00000002 -#define OR_UPM_EHTR_SHIFT 1 -#define OR_UPM_EAD 0x00000001 -#define OR_UPM_EAD_SHIFT 0 +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 -#define OR_SDRAM_AM 0xFFFF8000 -#define OR_SDRAM_AM_SHIFT 15 -#define OR_SDRAM_XAM 0x00006000 -#define OR_SDRAM_XAM_SHIFT 13 -#define OR_SDRAM_COLS 0x00001C00 -#define OR_SDRAM_COLS_SHIFT 10 -#define OR_SDRAM_ROWS 0x000001C0 -#define OR_SDRAM_ROWS_SHIFT 6 -#define OR_SDRAM_PMSEL 0x00000020 -#define OR_SDRAM_PMSEL_SHIFT 5 -#define OR_SDRAM_EAD 0x00000001 -#define OR_SDRAM_EAD_SHIFT 0 +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 -/* - * Hard Reset Configration Word - High +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + +#define LBLAWAR_EN 0x80000000 +#define LBLAWAR_4KB 0x0000000B +#define LBLAWAR_8KB 0x0000000C +#define LBLAWAR_16KB 0x0000000D +#define LBLAWAR_32KB 0x0000000E +#define LBLAWAR_64KB 0x0000000F +#define LBLAWAR_128KB 0x00000010 +#define LBLAWAR_256KB 0x00000011 +#define LBLAWAR_512KB 0x00000012 +#define LBLAWAR_1MB 0x00000013 +#define LBLAWAR_2MB 0x00000014 +#define LBLAWAR_4MB 0x00000015 +#define LBLAWAR_8MB 0x00000016 +#define LBLAWAR_16MB 0x00000017 +#define LBLAWAR_32MB 0x00000018 +#define LBLAWAR_64MB 0x00000019 +#define LBLAWAR_128MB 0x0000001A +#define LBLAWAR_256MB 0x0000001B +#define LBLAWAR_512MB 0x0000001C +#define LBLAWAR_1GB 0x0000001D +#define LBLAWAR_2GB 0x0000001E + +/* LBCR - Local Bus Configuration Register */ -#define HRCWH_PCI_AGENT 0x00000000 -#define HRCWH_PCI_HOST 0x80000000 +#define LBCR_LDIS 0x80000000 +#define LBCR_LDIS_SHIFT 31 +#define LBCR_BCTLC 0x00C00000 +#define LBCR_BCTLC_SHIFT 22 +#define LBCR_LPBSE 0x00020000 +#define LBCR_LPBSE_SHIFT 17 +#define LBCR_EPAR 0x00010000 +#define LBCR_EPAR_SHIFT 16 +#define LBCR_BMT 0x0000FF00 +#define LBCR_BMT_SHIFT 8 -#if defined (CONFIG_MPC8349) -#define HRCWH_32_BIT_PCI 0x00000000 -#define HRCWH_64_BIT_PCI 0x40000000 -#endif - -#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 -#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 - -#if defined (CONFIG_MPC8349) -#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 -#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 -#elif defined (CONFIG_MPC8360) -#define HRCWH_PCICKDRV_DISABLE 0x00000000 -#define HRCWH_PCICKDRV_ENABLE 0x10000000 -#endif - -#define HRCWH_CORE_DISABLE 0x08000000 -#define HRCWH_CORE_ENABLE 0x00000000 - -#define HRCWH_FROM_0X00000100 0x00000000 -#define HRCWH_FROM_0XFFF00100 0x04000000 - -#define HRCWH_BOOTSEQ_DISABLE 0x00000000 -#define HRCWH_BOOTSEQ_NORMAL 0x01000000 -#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 - -#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 -#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 - -#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 -#define HRCWH_ROM_LOC_PCI1 0x00100000 -#if defined (CONFIG_MPC8349) -#define HRCWH_ROM_LOC_PCI2 0x00200000 -#endif -#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 -#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 -#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 - -#if defined (CONFIG_MPC8349) -#define HRCWH_TSEC1M_IN_RGMII 0x00000000 -#define HRCWH_TSEC1M_IN_RTBI 0x00004000 -#define HRCWH_TSEC1M_IN_GMII 0x00008000 -#define HRCWH_TSEC1M_IN_TBI 0x0000C000 - -#define HRCWH_TSEC2M_IN_RGMII 0x00000000 -#define HRCWH_TSEC2M_IN_RTBI 0x00001000 -#define HRCWH_TSEC2M_IN_GMII 0x00002000 -#define HRCWH_TSEC2M_IN_TBI 0x00003000 -#endif - -#if defined (CONFIG_MPC8360) -#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 -#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 -#endif - -#define HRCWH_BIG_ENDIAN 0x00000000 -#define HRCWH_LITTLE_ENDIAN 0x00000008 - -#define HRCWH_LALE_NORMAL 0x00000000 -#define HRCWH_LALE_EARLY 0x00000004 - -#define HRCWH_LDP_SET 0x00000000 -#define HRCWH_LDP_CLEAR 0x00000002 - -/* - * Hard Reset Configration Word - Low +/* LCRR - Clock Ratio Register */ -#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 -#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_BUFCMDC_1 0x10000000 +#define LCRR_BUFCMDC_2 0x20000000 +#define LCRR_BUFCMDC_3 0x30000000 +#define LCRR_BUFCMDC_4 0x00000000 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_ECL_4 0x00000000 +#define LCRR_ECL_5 0x01000000 +#define LCRR_ECL_6 0x02000000 +#define LCRR_ECL_7 0x03000000 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_EADC_1 0x00010000 +#define LCRR_EADC_2 0x00020000 +#define LCRR_EADC_3 0x00030000 +#define LCRR_EADC_4 0x00000000 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_SHIFT 0 +#define LCRR_CLKDIV_2 0x00000002 +#define LCRR_CLKDIV_4 0x00000004 +#define LCRR_CLKDIV_8 0x00000008 -#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 -#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 - -#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 -#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 -#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 -#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 -#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 -#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 -#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 -#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 -#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 -#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 -#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 -#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 -#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 -#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 -#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 -#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 - -#define HRCWL_VCO_BYPASS 0x00000000 -#define HRCWL_VCO_1X2 0x00000000 -#define HRCWL_VCO_1X4 0x00200000 -#define HRCWL_VCO_1X8 0x00400000 - -#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 -#define HRCWL_CORE_TO_CSB_1X1 0x00020000 -#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 -#define HRCWL_CORE_TO_CSB_2X1 0x00040000 -#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 -#define HRCWL_CORE_TO_CSB_3X1 0x00060000 - -#if defined (CONFIG_MPC8360) -#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 -#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 -#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 - -#define HRCWL_CE_PLL_DIV_1X1 0x00000000 -#define HRCWL_CE_PLL_DIV_2X1 0x00000020 - -#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 -#define HRCWL_CE_TO_PLL_1X2 0x00000002 -#define HRCWL_CE_TO_PLL_1X3 0x00000003 -#define HRCWL_CE_TO_PLL_1X4 0x00000004 -#define HRCWL_CE_TO_PLL_1X5 0x00000005 -#define HRCWL_CE_TO_PLL_1X6 0x00000006 -#define HRCWL_CE_TO_PLL_1X7 0x00000007 -#define HRCWL_CE_TO_PLL_1X8 0x00000008 -#define HRCWL_CE_TO_PLL_1X9 0x00000009 -#define HRCWL_CE_TO_PLL_1X10 0x0000000A -#define HRCWL_CE_TO_PLL_1X11 0x0000000B -#define HRCWL_CE_TO_PLL_1X12 0x0000000C -#define HRCWL_CE_TO_PLL_1X13 0x0000000D -#define HRCWL_CE_TO_PLL_1X14 0x0000000E -#define HRCWL_CE_TO_PLL_1X15 0x0000000F -#define HRCWL_CE_TO_PLL_1X16 0x00000010 -#define HRCWL_CE_TO_PLL_1X17 0x00000011 -#define HRCWL_CE_TO_PLL_1X18 0x00000012 -#define HRCWL_CE_TO_PLL_1X19 0x00000013 -#define HRCWL_CE_TO_PLL_1X20 0x00000014 -#define HRCWL_CE_TO_PLL_1X21 0x00000015 -#define HRCWL_CE_TO_PLL_1X22 0x00000016 -#define HRCWL_CE_TO_PLL_1X23 0x00000017 -#define HRCWL_CE_TO_PLL_1X24 0x00000018 -#define HRCWL_CE_TO_PLL_1X25 0x00000019 -#define HRCWL_CE_TO_PLL_1X26 0x0000001A -#define HRCWL_CE_TO_PLL_1X27 0x0000001B -#define HRCWL_CE_TO_PLL_1X28 0x0000001C -#define HRCWL_CE_TO_PLL_1X29 0x0000001D -#define HRCWL_CE_TO_PLL_1X30 0x0000001E -#define HRCWL_CE_TO_PLL_1X31 0x0000001F -#endif - -/* - * LCRR - Clock Ratio Register (10.3.1.16) +/* DMAMR - DMA Mode Register */ -#define LCRR_DBYP 0x80000000 -#define LCRR_DBYP_SHIFT 31 -#define LCRR_BUFCMDC 0x30000000 -#define LCRR_BUFCMDC_1 0x10000000 -#define LCRR_BUFCMDC_2 0x20000000 -#define LCRR_BUFCMDC_3 0x30000000 -#define LCRR_BUFCMDC_4 0x00000000 -#define LCRR_BUFCMDC_SHIFT 28 -#define LCRR_ECL 0x03000000 -#define LCRR_ECL_4 0x00000000 -#define LCRR_ECL_5 0x01000000 -#define LCRR_ECL_6 0x02000000 -#define LCRR_ECL_7 0x03000000 -#define LCRR_ECL_SHIFT 24 -#define LCRR_EADC 0x00030000 -#define LCRR_EADC_1 0x00010000 -#define LCRR_EADC_2 0x00020000 -#define LCRR_EADC_3 0x00030000 -#define LCRR_EADC_4 0x00000000 -#define LCRR_EADC_SHIFT 16 -#define LCRR_CLKDIV 0x0000000F -#define LCRR_CLKDIV_2 0x00000002 -#define LCRR_CLKDIV_4 0x00000004 -#define LCRR_CLKDIV_8 0x00000008 -#define LCRR_CLKDIV_SHIFT 0 +#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ +#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ +#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ +#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ -/* - * SCCR-System Clock Control Register +/* DMASR - DMA Status Register */ -#define SCCR_TSEC1CM_0 0x00000000 -#define SCCR_TSEC1CM_1 0x40000000 -#define SCCR_TSEC1CM_2 0x80000000 -#define SCCR_TSEC1CM_3 0xC0000000 -#define SCCR_TSEC2CM_0 0x00000000 -#define SCCR_TSEC2CM_1 0x10000000 -#define SCCR_TSEC2CM_2 0x20000000 -#define SCCR_TSEC2CM_3 0x30000000 -#define SCCR_ENCCM_0 0x00000000 -#define SCCR_ENCCM_1 0x01000000 -#define SCCR_ENCCM_2 0x02000000 -#define SCCR_ENCCM_3 0x03000000 -#define SCCR_USBCM_0 0x00000000 -#define SCCR_USBCM_1 0x00500000 -#define SCCR_USBCM_2 0x00A00000 -#define SCCR_USBCM_3 0x00F00000 +#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ +#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ -#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ - | SCCR_TSEC2CM_3 \ - | SCCR_ENCCM_3 \ - | SCCR_USBCM_3 ) +/* CONFIG_ADDRESS - PCI Config Address Register + */ +#define PCI_CONFIG_ADDRESS_EN 0x80000000 +#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 +#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 +#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 +#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 +#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 +#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 +#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 +#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc -#define SCCR_DEFAULT 0xFFFFFFFF +/* POTAR - PCI Outbound Translation Address Register + */ +#define POTAR_TA_MASK 0x000fffff + +/* POBAR - PCI Outbound Base Address Register + */ +#define POBAR_BA_MASK 0x000fffff + +/* POCMR - PCI Outbound Comparision Mask Register + */ +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ +#define POCMR_SE 0x20000000 /* streaming enable */ +#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + +/* PITAR - PCI Inbound Translation Address Register + */ +#define PITAR_TA_MASK 0x000fffff + +/* PIBAR - PCI Inbound Base/Extended Address Register + */ +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff + +/* PIWAR - PCI Inbound Windows Attributes Register + */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E #endif /* __MPC83XX_H__ */