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drivers:mmc:sdhci: enable support for DT
This patch enables support for device tree for sdhci driver. Non DT case is still supported. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -53,6 +53,8 @@
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#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
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#define SDHCI_CTRL4_DRIVE_SHIFT (16)
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#define SDHCI_MAX_HOSTS 4
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int s5p_sdhci_init(u32 regbase, int index, int bus_width);
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static inline int s5p_mmc_init(int index, int bus_width)
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@ -62,4 +64,9 @@ static inline int s5p_mmc_init(int index, int bus_width)
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return s5p_sdhci_init(base, index, bus_width);
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}
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#ifdef CONFIG_OF_CONTROL
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int exynos_mmc_init(const void *blob);
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#endif
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#endif
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@ -8,8 +8,15 @@
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#include <common.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <asm/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/clk.h>
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#include <errno.h>
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#ifdef CONFIG_OF_CONTROL
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#include <asm/arch/pinmux.h>
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#endif
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static char *S5P_NAME = "SAMSUNG SDHCI";
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static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
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@ -86,3 +93,125 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
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return add_sdhci(host, 52000000, 400000);
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}
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#ifdef CONFIG_OF_CONTROL
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struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
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static int do_sdhci_init(struct sdhci_host *host)
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{
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int dev_id, flag;
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int err = 0;
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flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
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dev_id = host->index + PERIPH_ID_SDMMC0;
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if (fdt_gpio_isvalid(&host->pwr_gpio)) {
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gpio_direction_output(host->pwr_gpio.gpio, 1);
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err = exynos_pinmux_config(dev_id, flag);
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if (err) {
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debug("MMC not configured\n");
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return err;
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}
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}
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if (fdt_gpio_isvalid(&host->cd_gpio)) {
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gpio_direction_output(host->cd_gpio.gpio, 0xf);
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if (gpio_get_value(host->cd_gpio.gpio))
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return -ENODEV;
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err = exynos_pinmux_config(dev_id, flag);
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if (err) {
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printf("external SD not configured\n");
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return err;
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}
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}
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host->name = S5P_NAME;
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host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
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SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_WAIT_SEND_CMD;
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host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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host->set_control_reg = &s5p_sdhci_set_control_reg;
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host->set_clock = set_mmc_clk;
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host->host_caps = MMC_MODE_HC;
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return add_sdhci(host, 52000000, 400000);
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}
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static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
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{
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int bus_width, dev_id;
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unsigned int base;
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/* Get device id */
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dev_id = pinmux_decode_periph_id(blob, node);
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if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
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debug("MMC: Can't get device id\n");
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return -1;
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}
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host->index = dev_id - PERIPH_ID_SDMMC0;
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/* Get bus width */
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bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
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if (bus_width <= 0) {
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debug("MMC: Can't get bus-width\n");
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return -1;
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}
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host->bus_width = bus_width;
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/* Get the base address from the device node */
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base = fdtdec_get_addr(blob, node, "reg");
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if (!base) {
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debug("MMC: Can't get base address\n");
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return -1;
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}
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host->ioaddr = (void *)base;
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fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio);
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fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
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return 0;
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}
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static int process_nodes(const void *blob, int node_list[], int count)
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{
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struct sdhci_host *host;
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int i, node;
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debug("%s: count = %d\n", __func__, count);
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/* build sdhci_host[] for each controller */
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for (i = 0; i < count; i++) {
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node = node_list[i];
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if (node <= 0)
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continue;
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host = &sdhci_host[i];
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if (sdhci_get_config(blob, node, host)) {
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printf("%s: failed to decode dev %d\n", __func__, i);
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return -1;
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}
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do_sdhci_init(host);
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}
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return 0;
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}
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int exynos_mmc_init(const void *blob)
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{
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int count;
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int node_list[SDHCI_MAX_HOSTS];
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count = fdtdec_find_aliases_for_id(blob, "mmc",
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COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
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SDHCI_MAX_HOSTS);
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process_nodes(blob, node_list, count);
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return 1;
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}
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#endif
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@ -82,6 +82,7 @@ enum fdt_compat_id {
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COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
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COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
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COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
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COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
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COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
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COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
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COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
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@ -12,6 +12,7 @@
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#include <asm/io.h>
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#include <mmc.h>
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#include <fdtdec.h>
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/*
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* Controller registers
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@ -244,6 +245,10 @@ struct sdhci_host {
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const struct sdhci_ops *ops;
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int index;
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int bus_width;
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struct fdt_gpio_state pwr_gpio; /* Power GPIO */
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struct fdt_gpio_state cd_gpio; /* Card Detect GPIO */
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void (*set_control_reg)(struct sdhci_host *host);
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void (*set_clock)(int dev_index, unsigned int div);
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uint voltages;
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@ -55,6 +55,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
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COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
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COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
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COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
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COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"),
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COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"),
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COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
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COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
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