mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-26 13:44:29 +08:00
Merge branch 'master' of /home/wd/git/u-boot/master/
This commit is contained in:
Wolfgang Denk
commit
356cd17cc2
@ -607,7 +607,7 @@ Thomas Lange <thomas@corelatus.se>
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dbau1x00 MIPS32 Au1000
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gth2 MIPS32 Au1000
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Vlad Lungu <vlad@comsys.ro>
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Vlad Lungu <vlad.lungu@windriver.com>
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qemu_mips MIPS32
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#########################################################################
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2
Makefile
2
Makefile
@ -424,7 +424,7 @@ $(obj)System.map: $(obj)u-boot
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# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep.
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# the dep file is only include in this top level makefile to determine when
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# to regenerate the autoconf.mk file.
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$(obj)include/autoconf.mk: $(obj)include/config.h $(VERSION_FILE)
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$(obj)include/autoconf.mk: $(obj)include/config.h
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@$(XECHO) Generating include/autoconf.mk ; \
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set -e ; \
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: Generate the dependancies ; \
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1
README
1
README
@ -623,7 +623,6 @@ The following options need to be configured:
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CONFIG_CMD_SPI * SPI serial bus support
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CONFIG_CMD_USB * USB support
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CONFIG_CMD_VFD * VFD support (TRAB)
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CONFIG_CMD_BSP * Board SPecific functions
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CONFIG_CMD_CDP * Cisco Discover Protocol support
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CONFIG_CMD_FSL * Microblaze FSL support
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@ -1,4 +1,4 @@
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By Vlad Lungu vlad@comsys.ro 2007-Oct-01
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By Vlad Lungu vlad.lungu@windriver.com 2007-Oct-01
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----------------------------------------
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Qemu is a full system emulator. See
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@ -9,3 +9,7 @@ Limitations & comments
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Supports the "-m mips" configuration of qemu: serial,NE2000,IDE.
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Support is big endian only for now (or at least this is what I tested).
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Derived from au1x00 with a lot of things cut out.
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Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
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recent qemu versions. When using emulated flash, launch with
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-pflash <filename> and erase mips_bios.bin.
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@ -1,6 +1,6 @@
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/*
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* (C) Copyright 2007
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* Vlad Lungu vlad@comsys.ro
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* Vlad Lungu vlad.lungu@windriver.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -52,10 +52,6 @@
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# include <status_led.h>
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#endif
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#ifndef __PPC__
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#include <asm/io.h>
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#endif
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#ifdef CONFIG_IDE_8xx_DIRECT
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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@ -93,6 +93,7 @@ static table_entry_t uimage_arch[] = {
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{ IH_ARCH_MIPS64, "mips64", "MIPS 64 Bit", },
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{ IH_ARCH_NIOS, "nios", "NIOS", },
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{ IH_ARCH_NIOS2, "nios2", "NIOS II", },
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{ IH_ARCH_PPC, "powerpc", "PowerPC", },
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{ IH_ARCH_PPC, "ppc", "PowerPC", },
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{ IH_ARCH_S390, "s390", "IBM S390", },
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{ IH_ARCH_SH, "sh", "SuperH", },
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@ -329,14 +329,28 @@ _GLOBAL(dcache_status)
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blr
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/*
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* Invalidate L2 cache using L2I and polling L2IP
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* Invalidate L2 cache using L2I and polling L2IP or L2I
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*/
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_GLOBAL(l2cache_invalidate)
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sync
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mfspr r3, l2cr
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oris r3, r3, L2CR_L2I@h
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sync
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mtspr l2cr, r3
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sync
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mfspr r3, PVR
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sync
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rlwinm r3, r3, 16,16,31
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cmpli 0,r3,0x8000 /* 7451, 7441 */
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beq 0,inv_7450
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cmpli 0,r3,0x8001 /* 7455, 7445 */
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beq 0,inv_7450
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cmpli 0,r3,0x8002 /* 7457, 7447 */
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beq 0,inv_7450
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cmpli 0,r3,0x8003 /* 7447A */
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beq 0,inv_7450
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cmpli 0,r3,0x8004 /* 7448 */
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beq 0,inv_7450
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invl2:
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mfspr r3, l2cr
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andi. r3, r3, L2CR_L2IP
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@ -348,6 +362,11 @@ invl2:
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mtspr l2cr, r3
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sync
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blr
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inv_7450:
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mfspr r3, l2cr
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andis. r3, r3, L2CR_L2I@h
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bne inv_7450
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blr
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/*
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* Enable L2 cache
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@ -69,4 +69,4 @@ int usb_cpu_init_fail (void)
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}
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# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
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#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
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#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) */
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@ -338,7 +338,7 @@ _GLOBAL(l2cache_invalidate)
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invl2:
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mfspr r3, l2cr
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andi. r3, r3, L2CR_L2I@h
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andis. r3, r3, L2CR_L2I@h
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bne invl2
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blr
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96
disk/part.c
96
disk/part.c
@ -109,44 +109,45 @@ void dev_print (block_dev_desc_t *dev_desc)
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lbaint_t lba512;
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#endif
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if (dev_desc->type==DEV_TYPE_UNKNOWN) {
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puts ("not available\n");
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return;
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}
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if (dev_desc->if_type==IF_TYPE_SCSI) {
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printf ("(%d:%d) ", dev_desc->target,dev_desc->lun);
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}
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if (dev_desc->if_type==IF_TYPE_IDE) {
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printf ("Model: %s Firm: %s Ser#: %s\n",
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dev_desc->vendor,
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dev_desc->revision,
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dev_desc->product);
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}
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if (dev_desc->if_type==IF_TYPE_SATA) {
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printf ("Model: %s Firm: %s Ser#: %s\n",
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dev_desc->vendor,
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dev_desc->revision,
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dev_desc->product);
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} else {
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printf ("Vendor: %s Prod.: %s Rev: %s\n",
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switch (dev_desc->type) {
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case IF_TYPE_SCSI:
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printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n",
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dev_desc->target,dev_desc->lun,
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dev_desc->vendor,
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dev_desc->product,
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dev_desc->revision);
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break;
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case IF_TYPE_IDE:
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case IF_TYPE_SATA:
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printf ("Model: %s Firm: %s Ser#: %s\n",
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dev_desc->vendor,
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dev_desc->revision,
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dev_desc->product);
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break;
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case DEV_TYPE_UNKNOWN:
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default:
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puts ("not available\n");
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return;
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}
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puts (" Type: ");
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if (dev_desc->removable)
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puts ("Removable ");
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switch (dev_desc->type & 0x1F) {
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case DEV_TYPE_HARDDISK: puts ("Hard Disk");
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break;
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case DEV_TYPE_CDROM: puts ("CD ROM");
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break;
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case DEV_TYPE_OPDISK: puts ("Optical Device");
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break;
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case DEV_TYPE_TAPE: puts ("Tape");
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break;
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default: printf ("# %02X #", dev_desc->type & 0x1F);
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break;
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case DEV_TYPE_HARDDISK:
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puts ("Hard Disk");
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break;
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case DEV_TYPE_CDROM:
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puts ("CD ROM");
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break;
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case DEV_TYPE_OPDISK:
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puts ("Optical Device");
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break;
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case DEV_TYPE_TAPE:
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puts ("Tape");
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break;
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default:
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printf ("# %02X #", dev_desc->type & 0x1F);
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break;
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}
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puts ("\n");
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if ((dev_desc->lba * dev_desc->blksz)>0L) {
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@ -281,20 +282,27 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
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{
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puts ("\nPartition Map for ");
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switch (dev_desc->if_type) {
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case IF_TYPE_IDE: puts ("IDE");
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break;
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case IF_TYPE_SATA: puts ("SATA");
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break;
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case IF_TYPE_SCSI: puts ("SCSI");
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break;
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case IF_TYPE_ATAPI: puts ("ATAPI");
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break;
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case IF_TYPE_USB: puts ("USB");
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break;
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case IF_TYPE_DOC: puts ("DOC");
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break;
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default: puts ("UNKNOWN");
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break;
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case IF_TYPE_IDE:
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puts ("IDE");
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break;
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case IF_TYPE_SATA:
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puts ("SATA");
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break;
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case IF_TYPE_SCSI:
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puts ("SCSI");
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break;
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case IF_TYPE_ATAPI:
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puts ("ATAPI");
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break;
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case IF_TYPE_USB:
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puts ("USB");
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break;
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case IF_TYPE_DOC:
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puts ("DOC");
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break;
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default:
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puts ("UNKNOWN");
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break;
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}
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printf (" device %d -- Partition Type: %s\n\n",
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dev_desc->dev, type);
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@ -9,7 +9,7 @@ The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
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completely without NOR FLASH. This can be done by using the NAND
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boot feature of the 440 NAND flash controller (NDFC).
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Here a short desciption of the different boot stages:
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Here a short description of the different boot stages:
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a) IPL (Initial Program Loader, integrated inside CPU)
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------------------------------------------------------
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4
include/.gitignore
vendored
4
include/.gitignore
vendored
@ -1,7 +1,7 @@
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/autoconf.mk*
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/asm
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/asm-blackfin/arch
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/asm-ppc/arch
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/asm-*/arch
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/asm-*/proc
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/bmp_logo.h
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/config.h
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/config.mk
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@ -56,9 +56,11 @@
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/* ethernet */
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#ifdef XILINX_EMAC_BASEADDR
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#define CONFIG_XILINX_EMAC 1
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#define CFG_ENET
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#else
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#ifdef XILINX_EMACLITE_BASEADDR
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#define CONFIG_XILINX_EMACLITE 1
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#define CFG_ENET
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#endif
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#endif
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#undef ET_DEBUG
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@ -70,18 +72,28 @@
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#endif
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/* interrupt controller */
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#ifdef XILINX_INTC_BASEADDR
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#define CFG_INTC_0 1
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#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
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#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
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#endif
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/* timer */
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#ifdef XILINX_TIMER_BASEADDR
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#if (XILINX_TIMER_IRQ != -1)
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#define CFG_TIMER_0 1
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#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
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#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
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#define FREQUENCE XILINX_CLOCK_FREQ
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#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
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#endif
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#else
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#ifdef XILINX_CLOCK_FREQ
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#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
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#else
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#error BAD CLOCK FREQ
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#endif
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#endif
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/* FSL */
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/* #define CFG_FSL_2 */
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/* #define FSL_INTR_2 1 */
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@ -195,7 +207,12 @@
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MFSL
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#define CONFIG_CMD_PING
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#ifndef CFG_ENET
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#undef CONFIG_CMD_NET
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#else
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#define CONFIG_CMD_PING
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#endif
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#if defined(CONFIG_SYSTEMACE)
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#define CONFIG_CMD_EXT2
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@ -63,9 +63,11 @@
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/* ethernet */
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#ifdef XILINX_EMAC_BASEADDR
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#define CONFIG_XILINX_EMAC 1
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#define CFG_ENET
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#else
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#ifdef XILINX_EMACLITE_BASEADDR
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#define CONFIG_XILINX_EMACLITE 1
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#define CFG_ENET
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#endif
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#endif
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#undef ET_DEBUG
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@ -77,18 +79,28 @@
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#endif
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/* interrupt controller */
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#ifdef XILINX_INTC_BASEADDR
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#define CFG_INTC_0 1
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#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
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#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
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#endif
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/* timer */
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#ifdef XILINX_TIMER_BASEADDR
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#if (XILINX_TIMER_IRQ != -1)
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#define CFG_TIMER_0 1
|
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#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
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#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
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#define FREQUENCE XILINX_CLOCK_FREQ
|
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#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
|
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#endif
|
||||
#else
|
||||
#ifdef XILINX_CLOCK_FREQ
|
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#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
|
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|
||||
#else
|
||||
#error BAD CLOCK FREQ
|
||||
#endif
|
||||
#endif
|
||||
/*
|
||||
* memory layout - Example
|
||||
* TEXT_BASE = 0x3600_0000;
|
||||
@ -162,7 +174,12 @@
|
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#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_CACHE
|
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#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_PING
|
||||
|
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#ifndef CFG_ENET
|
||||
#undef CONFIG_CMD_NET
|
||||
#else
|
||||
#define CONFIG_CMD_PING
|
||||
#endif
|
||||
|
||||
#ifdef XILINX_SYSACE_BASEADDR
|
||||
#define CONFIG_CMD_EXT2
|
||||
|
||||
Loading…
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Block a user