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net: dwc_eth_qos: Split STM32 glue into separate file
Move STM32 glue code into separate file to contain the STM32 specific code outside of the DWMAC core code. No functional change. Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Christophe ROULLIER<christophe.roullier@foss.st.com>
This commit is contained in:
Marek Vasut
Patrice Chotard
parent
f5667d7740
commit
343742661b
@ -23,6 +23,7 @@ obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
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obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
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obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
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obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
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obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o
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obj-$(CONFIG_E1000) += e1000.o
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obj-$(CONFIG_E1000_SPI) += e1000_spi.o
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obj-$(CONFIG_EEPRO100) += eepro100.o
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@ -295,58 +295,6 @@ err:
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#endif
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}
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static int eqos_start_clks_stm32(struct udevice *dev)
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{
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#ifdef CONFIG_CLK
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struct eqos_priv *eqos = dev_get_priv(dev);
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int ret;
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debug("%s(dev=%p):\n", __func__, dev);
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ret = clk_enable(&eqos->clk_master_bus);
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if (ret < 0) {
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pr_err("clk_enable(clk_master_bus) failed: %d\n", ret);
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goto err;
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}
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ret = clk_enable(&eqos->clk_rx);
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if (ret < 0) {
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pr_err("clk_enable(clk_rx) failed: %d\n", ret);
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goto err_disable_clk_master_bus;
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}
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ret = clk_enable(&eqos->clk_tx);
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if (ret < 0) {
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pr_err("clk_enable(clk_tx) failed: %d\n", ret);
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goto err_disable_clk_rx;
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}
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if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
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ret = clk_enable(&eqos->clk_ck);
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if (ret < 0) {
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pr_err("clk_enable(clk_ck) failed: %d\n", ret);
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goto err_disable_clk_tx;
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}
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eqos->clk_ck_enabled = true;
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}
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#endif
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debug("%s: OK\n", __func__);
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return 0;
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#ifdef CONFIG_CLK
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err_disable_clk_tx:
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clk_disable(&eqos->clk_tx);
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err_disable_clk_rx:
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clk_disable(&eqos->clk_rx);
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err_disable_clk_master_bus:
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clk_disable(&eqos->clk_master_bus);
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err:
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debug("%s: FAILED: %d\n", __func__, ret);
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return ret;
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#endif
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}
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static int eqos_stop_clks_tegra186(struct udevice *dev)
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{
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#ifdef CONFIG_CLK
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@ -365,22 +313,6 @@ static int eqos_stop_clks_tegra186(struct udevice *dev)
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return 0;
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}
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static int eqos_stop_clks_stm32(struct udevice *dev)
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{
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#ifdef CONFIG_CLK
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struct eqos_priv *eqos = dev_get_priv(dev);
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debug("%s(dev=%p):\n", __func__, dev);
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clk_disable(&eqos->clk_tx);
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clk_disable(&eqos->clk_rx);
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clk_disable(&eqos->clk_master_bus);
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#endif
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debug("%s: OK\n", __func__);
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return 0;
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}
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static int eqos_start_resets_tegra186(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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@ -493,17 +425,6 @@ static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
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#endif
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}
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static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
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{
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#ifdef CONFIG_CLK
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struct eqos_priv *eqos = dev_get_priv(dev);
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return clk_get_rate(&eqos->clk_master_bus);
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#else
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return 0;
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#endif
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}
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static int eqos_set_full_duplex(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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@ -1415,57 +1336,6 @@ err_free_reset_eqos:
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return ret;
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}
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static int eqos_probe_resources_stm32(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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int ret;
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phy_interface_t interface;
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debug("%s(dev=%p):\n", __func__, dev);
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interface = eqos->config->interface(dev);
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if (interface == PHY_INTERFACE_MODE_NA) {
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pr_err("Invalid PHY interface\n");
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return -EINVAL;
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}
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ret = board_interface_eth_init(dev, interface);
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if (ret)
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return -EINVAL;
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ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
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if (ret) {
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pr_err("clk_get_by_name(master_bus) failed: %d\n", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
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if (ret) {
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pr_err("clk_get_by_name(rx) failed: %d\n", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
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if (ret) {
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pr_err("clk_get_by_name(tx) failed: %d\n", ret);
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goto err_probe;
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}
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/* Get ETH_CLK clocks (optional) */
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ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
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if (ret)
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pr_warn("No phy clock provided %d", ret);
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debug("%s: OK\n", __func__);
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return 0;
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err_probe:
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debug("%s: returns %d\n", __func__, ret);
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return ret;
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}
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static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev)
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{
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return PHY_INTERFACE_MODE_MII;
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@ -1484,12 +1354,6 @@ static int eqos_remove_resources_tegra186(struct udevice *dev)
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return 0;
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}
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static int eqos_remove_resources_stm32(struct udevice *dev)
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{
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debug("%s(dev=%p):\n", __func__, dev);
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return 0;
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}
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static int eqos_probe(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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@ -1633,35 +1497,6 @@ static const struct eqos_config __maybe_unused eqos_tegra186_config = {
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.ops = &eqos_tegra186_ops
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};
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static struct eqos_ops eqos_stm32_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_stm32,
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.eqos_remove_resources = eqos_remove_resources_stm32,
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.eqos_stop_resets = eqos_null_ops,
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.eqos_start_resets = eqos_null_ops,
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.eqos_stop_clks = eqos_stop_clks_stm32,
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.eqos_start_clks = eqos_start_clks_stm32,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_null_ops,
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.eqos_get_enetaddr = eqos_null_ops,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
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};
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static const struct eqos_config __maybe_unused eqos_stm32_config = {
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.reg_access_always_ok = false,
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.mdio_wait = 10000,
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.swr_wait = 50,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
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.axi_bus_width = EQOS_AXI_WIDTH_64,
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.interface = dev_read_phy_mode,
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.ops = &eqos_stm32_ops
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};
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static const struct udevice_id eqos_ids[] = {
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#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
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{
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@ -290,4 +290,5 @@ int eqos_null_ops(struct udevice *dev);
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extern struct eqos_config eqos_imx_config;
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extern struct eqos_config eqos_rockchip_config;
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extern struct eqos_config eqos_qcom_config;
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extern struct eqos_config eqos_stm32_config;
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extern struct eqos_config eqos_jh7110_config;
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196
drivers/net/dwc_eth_qos_stm32.c
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196
drivers/net/dwc_eth_qos_stm32.c
Normal file
@ -0,0 +1,196 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024, Marek Vasut <marex@denx.de>
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*
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* This is code moved from drivers/net/dwc_eth_qos.c , which is:
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*/
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#include <common.h>
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#include <asm/cache.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <errno.h>
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#include <eth_phy.h>
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#include <log.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <phy.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <linux/delay.h>
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#include "dwc_eth_qos.h"
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static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
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{
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#ifdef CONFIG_CLK
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struct eqos_priv *eqos = dev_get_priv(dev);
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return clk_get_rate(&eqos->clk_master_bus);
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#else
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return 0;
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#endif
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}
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static int eqos_start_clks_stm32(struct udevice *dev)
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{
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#ifdef CONFIG_CLK
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struct eqos_priv *eqos = dev_get_priv(dev);
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int ret;
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debug("%s(dev=%p):\n", __func__, dev);
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ret = clk_enable(&eqos->clk_master_bus);
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if (ret < 0) {
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pr_err("clk_enable(clk_master_bus) failed: %d", ret);
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goto err;
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}
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ret = clk_enable(&eqos->clk_rx);
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if (ret < 0) {
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pr_err("clk_enable(clk_rx) failed: %d", ret);
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goto err_disable_clk_master_bus;
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}
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ret = clk_enable(&eqos->clk_tx);
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if (ret < 0) {
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pr_err("clk_enable(clk_tx) failed: %d", ret);
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goto err_disable_clk_rx;
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}
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if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
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ret = clk_enable(&eqos->clk_ck);
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if (ret < 0) {
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pr_err("clk_enable(clk_ck) failed: %d", ret);
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goto err_disable_clk_tx;
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}
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eqos->clk_ck_enabled = true;
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}
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#endif
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debug("%s: OK\n", __func__);
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return 0;
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#ifdef CONFIG_CLK
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err_disable_clk_tx:
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clk_disable(&eqos->clk_tx);
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err_disable_clk_rx:
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clk_disable(&eqos->clk_rx);
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err_disable_clk_master_bus:
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clk_disable(&eqos->clk_master_bus);
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err:
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debug("%s: FAILED: %d\n", __func__, ret);
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return ret;
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#endif
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}
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static int eqos_stop_clks_stm32(struct udevice *dev)
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{
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#ifdef CONFIG_CLK
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struct eqos_priv *eqos = dev_get_priv(dev);
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debug("%s(dev=%p):\n", __func__, dev);
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clk_disable(&eqos->clk_tx);
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clk_disable(&eqos->clk_rx);
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clk_disable(&eqos->clk_master_bus);
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#endif
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debug("%s: OK\n", __func__);
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return 0;
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}
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static int eqos_probe_resources_stm32(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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int ret;
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phy_interface_t interface;
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debug("%s(dev=%p):\n", __func__, dev);
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interface = eqos->config->interface(dev);
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if (interface == PHY_INTERFACE_MODE_NA) {
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pr_err("Invalid PHY interface\n");
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return -EINVAL;
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}
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ret = board_interface_eth_init(dev, interface);
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if (ret)
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return -EINVAL;
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ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
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if (ret) {
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pr_err("clk_get_by_name(master_bus) failed: %d", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
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if (ret) {
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pr_err("clk_get_by_name(rx) failed: %d", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
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if (ret) {
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pr_err("clk_get_by_name(tx) failed: %d", ret);
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goto err_probe;
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}
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/* Get ETH_CLK clocks (optional) */
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ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
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if (ret)
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pr_warn("No phy clock provided %d", ret);
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debug("%s: OK\n", __func__);
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return 0;
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err_probe:
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debug("%s: returns %d\n", __func__, ret);
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return ret;
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}
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static int eqos_remove_resources_stm32(struct udevice *dev)
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{
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debug("%s(dev=%p):\n", __func__, dev);
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return 0;
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}
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static struct eqos_ops eqos_stm32_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_stm32,
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.eqos_remove_resources = eqos_remove_resources_stm32,
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.eqos_stop_resets = eqos_null_ops,
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.eqos_start_resets = eqos_null_ops,
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.eqos_stop_clks = eqos_stop_clks_stm32,
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.eqos_start_clks = eqos_start_clks_stm32,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_null_ops,
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.eqos_get_enetaddr = eqos_null_ops,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
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};
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struct eqos_config __maybe_unused eqos_stm32_config = {
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.reg_access_always_ok = false,
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.mdio_wait = 10000,
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.swr_wait = 50,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
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.axi_bus_width = EQOS_AXI_WIDTH_64,
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.interface = dev_read_phy_mode,
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.ops = &eqos_stm32_ops
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};
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