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rockchip: google: gru: Migrate to use IO-domain driver

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Switch to use the IO-domain driver to configure IO-domain based on
device tree instead of a setup_iodomain() function.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman 2024-03-12 23:36:21 +00:00 committed by Kever Yang
parent 95a9cb3666
commit 3330c8880c
3 changed files with 2 additions and 35 deletions
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35
board/google/gru/gru.c
View File

@ -3,18 +3,9 @@
* Copyright 2018 Google
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#define GRF_IO_VSEL_BT656_SHIFT 0
#define GRF_IO_VSEL_AUDIO_SHIFT 1
#define PMUGRF_CON0_VSEL_SHIFT 8
#define PMUGRF_CON0_VOL_SHIFT 9
#ifdef CONFIG_SPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
@ -63,29 +54,3 @@ int board_early_init_r(void)
return 0;
}
#endif
static void setup_iodomain(void)
{
struct rk3399_grf_regs *grf =
syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
struct rk3399_pmugrf_regs *pmugrf =
syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
/* BT656 and audio is in 1.8v domain */
rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
1 << GRF_IO_VSEL_AUDIO_SHIFT));
/*
* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
* and explicitly configure that PMU1830_VOL to be 1.8V
*/
rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
1 << PMUGRF_CON0_VOL_SHIFT));
}
int rockchip_early_misc_init_r(void)
{
setup_iodomain();
return 0;
}

1
configs/chromebook_bob_defconfig
View File

@ -66,6 +66,7 @@ CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y

1
configs/chromebook_kevin_defconfig
View File

@ -67,6 +67,7 @@ CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y