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video: dcu: Add DCU driver support
This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang <alison.wang@freescale.com>
This commit is contained in:
Wang Huan
York Sun
parent
6209e14cb0
commit
327def5060
@ -24,6 +24,7 @@
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#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
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#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
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#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
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#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
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@ -60,6 +61,9 @@
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#define CONFIG_SYS_FSL_WDOG_BE
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#define CONFIG_SYS_FSL_DSPI_BE
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#define CONFIG_SYS_FSL_QSPI_BE
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#define CONFIG_SYS_FSL_DCU_BE
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#define DCU_LAYER_MAX_NUM 16
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#define CONFIG_SYS_FSL_SRDS_1
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@ -15,6 +15,7 @@ obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
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exynos_mipi_dsi_lowlevel.o
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obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
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obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
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obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
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obj-$(CONFIG_L5F31188) += l5f31188.o
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obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
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obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
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365
drivers/video/fsl_dcu_fb.c
Normal file
365
drivers/video/fsl_dcu_fb.c
Normal file
@ -0,0 +1,365 @@
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* FSL DCU Framebuffer driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_dcu_fb.h>
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#include <linux/fb.h>
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#include <malloc.h>
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#include <video_fb.h>
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#include "videomodes.h"
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/* Convert the X,Y resolution pair into a single number */
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#define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
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#ifdef CONFIG_SYS_FSL_DCU_LE
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#define dcu_read32 in_le32
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#define dcu_write32 out_le32
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#elif defined(CONFIG_SYS_FSL_DCU_BE)
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#define dcu_read32 in_be32
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#define dcu_write32 out_be32
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#endif
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#define DCU_MODE_BLEND_ITER(x) ((x) << 20)
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#define DCU_MODE_RASTER_EN (1 << 14)
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#define DCU_MODE_NORMAL 1
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#define DCU_MODE_COLORBAR 3
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#define DCU_BGND_R(x) ((x) << 16)
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#define DCU_BGND_G(x) ((x) << 8)
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#define DCU_BGND_B(x) (x)
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#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
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#define DCU_DISP_SIZE_DELTA_X(x) (x)
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#define DCU_HSYN_PARA_BP(x) ((x) << 22)
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#define DCU_HSYN_PARA_PW(x) ((x) << 11)
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#define DCU_HSYN_PARA_FP(x) (x)
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#define DCU_VSYN_PARA_BP(x) ((x) << 22)
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#define DCU_VSYN_PARA_PW(x) ((x) << 11)
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#define DCU_VSYN_PARA_FP(x) (x)
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#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6)
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#define DCU_SYN_POL_NEG_REMAIN (0 << 5)
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#define DCU_SYN_POL_INV_VS_LOW (1 << 1)
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#define DCU_SYN_POL_INV_HS_LOW (1)
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#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
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#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
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#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
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#define DCU_UPDATE_MODE_MODE (1 << 31)
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#define DCU_UPDATE_MODE_READREG (1 << 30)
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#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
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#define DCU_CTRLDESCLN_1_WIDTH(x) (x)
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#define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
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#define DCU_CTRLDESCLN_2_POSX(x) (x)
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#define DCU_CTRLDESCLN_4_EN (1 << 31)
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#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
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#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
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#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
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#define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
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#define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
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#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
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#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
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#define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
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#define DCU_CTRLDESCLN_4_AB(x) (x)
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#define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
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#define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
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#define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
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#define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
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#define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
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#define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
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#define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
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#define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
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#define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
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#define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
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#define BPP_16_RGB565 4
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#define BPP_24_RGB888 5
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#define BPP_32_ARGB8888 6
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/*
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* This setting is used for the TWR_LCD_RGB card
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*/
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static struct fb_videomode fsl_dcu_mode_480_272 = {
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.name = "480x272-60",
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.refresh = 60,
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.xres = 480,
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.yres = 272,
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.pixclock = 91996,
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.left_margin = 2,
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.right_margin = 2,
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.upper_margin = 1,
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.lower_margin = 1,
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.hsync_len = 41,
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.vsync_len = 2,
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.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED
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};
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/*
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* This setting is used for Siliconimage SiI9022A HDMI
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*/
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static struct fb_videomode fsl_dcu_mode_640_480 = {
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.name = "640x480-60",
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.refresh = 60,
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.xres = 640,
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.yres = 480,
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.pixclock = 39722,
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.left_margin = 48,
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.right_margin = 16,
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.upper_margin = 33,
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.lower_margin = 10,
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.hsync_len = 96,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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};
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/*
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* DCU register map
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*/
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struct dcu_reg {
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u32 desc_cursor[4];
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u32 mode;
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u32 bgnd;
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u32 disp_size;
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u32 hsyn_para;
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u32 vsyn_para;
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u32 synpol;
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u32 threshold;
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u32 int_status;
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u32 int_mask;
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u32 colbar[8];
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u32 div_ratio;
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u32 sign_calc[2];
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u32 crc_val;
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u8 res_064[0x6c-0x64];
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u32 parr_err_status1;
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u8 res_070[0x7c-0x70];
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u32 parr_err_status3;
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u32 mparr_err_status1;
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u8 res_084[0x90-0x84];
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u32 mparr_err_status3;
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u32 threshold_inp_buf[2];
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u8 res_09c[0xa0-0x9c];
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u32 luma_comp;
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u32 chroma_red;
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u32 chroma_green;
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u32 chroma_blue;
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u32 crc_pos;
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u32 lyr_intpol_en;
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u32 lyr_luma_comp;
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u32 lyr_chrm_red;
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u32 lyr_chrm_grn;
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u32 lyr_chrm_blue;
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u8 res_0c4[0xcc-0xc8];
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u32 update_mode;
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u32 underrun;
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u8 res_0d4[0x100-0xd4];
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u32 gpr;
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u32 slr_l[2];
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u32 slr_disp_size;
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u32 slr_hvsync_para;
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u32 slr_pol;
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u32 slr_l_transp[2];
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u8 res_120[0x200-0x120];
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u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
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};
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static struct fb_info info;
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static void reset_total_layers(void)
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{
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struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
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int i;
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for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
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dcu_write32(®s->ctrldescl[i][0], 0);
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dcu_write32(®s->ctrldescl[i][1], 0);
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dcu_write32(®s->ctrldescl[i][2], 0);
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dcu_write32(®s->ctrldescl[i][3], 0);
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dcu_write32(®s->ctrldescl[i][4], 0);
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dcu_write32(®s->ctrldescl[i][5], 0);
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dcu_write32(®s->ctrldescl[i][6], 0);
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dcu_write32(®s->ctrldescl[i][7], 0);
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dcu_write32(®s->ctrldescl[i][8], 0);
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dcu_write32(®s->ctrldescl[i][9], 0);
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dcu_write32(®s->ctrldescl[i][10], 0);
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}
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dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
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}
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static int layer_ctrldesc_init(int index, u32 pixel_format)
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{
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struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
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unsigned int bpp = BPP_24_RGB888;
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dcu_write32(®s->ctrldescl[index][0],
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DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) |
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DCU_CTRLDESCLN_1_WIDTH(info.var.xres));
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dcu_write32(®s->ctrldescl[index][1],
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DCU_CTRLDESCLN_2_POSY(0) |
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DCU_CTRLDESCLN_2_POSX(0));
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dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base);
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switch (pixel_format) {
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case 16:
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bpp = BPP_16_RGB565;
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break;
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case 24:
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bpp = BPP_24_RGB888;
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break;
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case 32:
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bpp = BPP_32_ARGB8888;
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break;
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default:
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printf("unsupported color depth: %u\n", pixel_format);
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}
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dcu_write32(®s->ctrldescl[index][3],
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DCU_CTRLDESCLN_4_EN |
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DCU_CTRLDESCLN_4_TRANS(0xff) |
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DCU_CTRLDESCLN_4_BPP(bpp) |
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DCU_CTRLDESCLN_4_AB(0));
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dcu_write32(®s->ctrldescl[index][4],
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DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
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DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
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DCU_CTRLDESCLN_5_CKMAX_B(0xff));
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dcu_write32(®s->ctrldescl[index][5],
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DCU_CTRLDESCLN_6_CKMIN_R(0) |
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DCU_CTRLDESCLN_6_CKMIN_G(0) |
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DCU_CTRLDESCLN_6_CKMIN_B(0));
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dcu_write32(®s->ctrldescl[index][6],
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DCU_CTRLDESCLN_7_TILE_VER(0) |
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DCU_CTRLDESCLN_7_TILE_HOR(0));
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dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
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dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
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dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
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return 0;
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}
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int fsl_dcu_init(unsigned int xres, unsigned int yres,
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unsigned int pixel_format)
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{
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struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
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unsigned int div, mode;
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/* Memory allocation for framebuffer */
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info.screen_size =
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info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
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info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
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roundup(info.screen_size, ARCH_DMA_MINALIGN));
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memset(info.screen_base, 0, info.screen_size);
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reset_total_layers();
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div = dcu_set_pixel_clock(info.var.pixclock);
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dcu_write32(®s->div_ratio, (div - 1));
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dcu_write32(®s->disp_size,
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DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
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DCU_DISP_SIZE_DELTA_X(info.var.xres / 16));
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dcu_write32(®s->hsyn_para,
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DCU_HSYN_PARA_BP(info.var.left_margin) |
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DCU_HSYN_PARA_PW(info.var.hsync_len) |
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DCU_HSYN_PARA_FP(info.var.right_margin));
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dcu_write32(®s->vsyn_para,
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DCU_VSYN_PARA_BP(info.var.upper_margin) |
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DCU_VSYN_PARA_PW(info.var.vsync_len) |
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DCU_VSYN_PARA_FP(info.var.lower_margin));
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dcu_write32(®s->synpol,
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DCU_SYN_POL_INV_PXCK_FALL |
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DCU_SYN_POL_NEG_REMAIN |
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DCU_SYN_POL_INV_VS_LOW |
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DCU_SYN_POL_INV_HS_LOW);
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dcu_write32(®s->bgnd,
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DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
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dcu_write32(®s->mode,
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DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) |
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DCU_MODE_RASTER_EN);
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dcu_write32(®s->threshold,
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DCU_THRESHOLD_LS_BF_VS(0x3) |
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DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
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DCU_THRESHOLD_OUT_BUF_LOW(0));
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mode = dcu_read32(®s->mode);
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dcu_write32(®s->mode, mode | DCU_MODE_NORMAL);
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layer_ctrldesc_init(0, pixel_format);
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return 0;
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}
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void *video_hw_init(void)
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{
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static GraphicDevice ctfb;
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const char *options;
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unsigned int depth = 0, freq = 0;
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struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
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if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
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&options))
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return NULL;
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/* Find the monitor port, which is a required option */
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if (!options)
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return NULL;
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if (strncmp(options, "monitor=", 8) != 0)
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return NULL;
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switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) {
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case RESOLUTION(480, 272):
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fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
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break;
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case RESOLUTION(640, 480):
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fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
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break;
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default:
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printf("unsupported resolution %ux%u\n",
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ctfb.winSizeX, ctfb.winSizeY);
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}
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info.var.xres = fsl_dcu_mode_db->xres;
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info.var.yres = fsl_dcu_mode_db->yres;
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info.var.bits_per_pixel = 32;
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info.var.pixclock = fsl_dcu_mode_db->pixclock;
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info.var.left_margin = fsl_dcu_mode_db->left_margin;
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info.var.right_margin = fsl_dcu_mode_db->right_margin;
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info.var.upper_margin = fsl_dcu_mode_db->upper_margin;
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info.var.lower_margin = fsl_dcu_mode_db->lower_margin;
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info.var.hsync_len = fsl_dcu_mode_db->hsync_len;
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info.var.vsync_len = fsl_dcu_mode_db->vsync_len;
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info.var.sync = fsl_dcu_mode_db->sync;
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info.var.vmode = fsl_dcu_mode_db->vmode;
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info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
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if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY,
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options + 8, fsl_dcu_mode_db) < 0)
|
||||
return NULL;
|
||||
|
||||
ctfb.frameAdrs = (unsigned int)info.screen_base;
|
||||
ctfb.plnSizeX = ctfb.winSizeX;
|
||||
ctfb.plnSizeY = ctfb.winSizeY;
|
||||
|
||||
ctfb.gdfBytesPP = 4;
|
||||
ctfb.gdfIndex = GDF_32BIT_X888RGB;
|
||||
|
||||
ctfb.memSize = info.screen_size;
|
||||
|
||||
return &ctfb;
|
||||
}
|
||||
16
include/fsl_dcu_fb.h
Normal file
16
include/fsl_dcu_fb.h
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* FSL DCU Framebuffer driver
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <linux/fb.h>
|
||||
|
||||
int fsl_dcu_init(unsigned int xres, unsigned int yres,
|
||||
unsigned int pixel_format);
|
||||
|
||||
/* Prototypes for external board-specific functions */
|
||||
int platform_dcu_init(unsigned int xres, unsigned int yres,
|
||||
const char *port, struct fb_videomode *dcu_fb_videomode);
|
||||
unsigned int dcu_set_pixel_clock(unsigned int pixclock);
|
||||
Loading…
Reference in New Issue
Block a user