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ppc4xx: Update PMC405 board support
This patch prepares the good old PMC405 board support for upcoming PMC405V2 patches. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
c553b5f4a0
commit
2f6eb9170b
@ -21,8 +21,4 @@
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# MA 02111-1307 USA
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#
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#
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# esd PMC405 boards
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#
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TEXT_BASE = 0xFFFC0000
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TEXT_BASE = 0xFFF80000
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@ -2,7 +2,7 @@
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* (C) Copyright 2001-2003
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2005
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* (C) Copyright 2005-2009
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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@ -26,6 +26,7 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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@ -77,16 +78,16 @@ int board_early_init_f (void)
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CONFIG_SYS_NONMONARCH | \
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CONFIG_SYS_REV1_2) << 5));
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if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
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if (!(in_be32((void*)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
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/* rev 1.2 boards */
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mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
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CONFIG_SYS_SELF_RST) << 5));
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}
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out32(GPIO0_OR, 0);
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out_be32((void*)GPIO0_OR, CONFIG_SYS_VPEN);
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/* setup for output */
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out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \
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CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY);
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out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \
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CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
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/*
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* - check if rev1_2 is low, then:
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@ -103,14 +104,15 @@ int misc_init_r (void)
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gd->bd->bi_flashoffset = 0;
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/* deassert EREADY# */
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out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY);
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out_be32((void*)GPIO0_OR,
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in_be32((void*)GPIO0_OR) | CONFIG_SYS_XEREADY);
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return (0);
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}
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ushort pmc405_pci_subsys_deviceid(void)
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{
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ulong val;
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val = in32(GPIO0_IR);
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val = in_be32((void*)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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/* check monarch# signal */
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if (val & CONFIG_SYS_NONMONARCH)
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@ -137,7 +139,7 @@ int checkboard (void)
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else
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puts(str);
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val = in32(GPIO0_IR);
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val = in_be32((void*)GPIO0_IR);
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if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
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puts(" rev1.2 (");
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if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
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@ -40,11 +40,20 @@
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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/* Only interrupt boot if space is pressed. */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#undef CONFIG_AUTOBOOT_DELAY_STR
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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@ -106,7 +115,7 @@
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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@ -122,18 +131,18 @@
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
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#define CONFIG_SYS_BASE_BAUD 691200
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#define CONFIG_SYS_BASE_BAUD 806400
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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@ -158,8 +167,6 @@
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
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#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
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@ -180,10 +187,12 @@
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
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#define CONFIG_PRAM 0 /* use pram variable to overwrite */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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@ -200,6 +209,7 @@
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
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#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
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@ -207,23 +217,6 @@
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
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/*
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* JFFS2 partitions - second bank contains u-boot
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* No command line, one static partition, whole device
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*/
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0x01b00000
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#define CONFIG_JFFS2_PART_OFFSET 0x00400000
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/*
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* mtdparts command line support
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* Note: fake mtd_id used, no linux mtd map file
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*/
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=pmc405-0"
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#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)"
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/*
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* Environment Variable setup
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*/
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@ -240,14 +233,17 @@
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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/*
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@ -287,7 +283,7 @@
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* FPGA stuff
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*/
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#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
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#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
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#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */
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/* FPGA program pin configuration */
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#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
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@ -302,6 +298,7 @@
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/*
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* GPIOs
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*/
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#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
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#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
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#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
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#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
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@ -339,4 +336,7 @@
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#endif /* __CONFIG_H */
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