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tegra: Enhance clock support to handle 16-bit clock divisors
I2C ports have a 16-bit clock divisor. Add code to handle this special case so that I2C speeds below 150KHz are supported. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass
Albert ARIBAUD
parent
c67822704b
commit
2e33559f3d
@ -68,6 +68,7 @@ enum clock_type_id {
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CLOCK_TYPE_MCPT,
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CLOCK_TYPE_PCM,
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CLOCK_TYPE_PCMT,
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CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
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CLOCK_TYPE_PCXTS,
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CLOCK_TYPE_PDCT,
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@ -99,6 +100,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
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{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
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{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
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};
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@ -212,8 +214,8 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
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/* 0x08 */
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TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
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@ -247,7 +249,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
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TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
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/* 0x28 */
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@ -257,7 +259,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
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/* 0x30 */
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@ -519,14 +521,16 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source)
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* Given the parent's rate and the required rate for the children, this works
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* out the peripheral clock divider to use, in 7.1 binary format.
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*
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* @param divider_bits number of divider bits (8 or 16)
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* @param parent_rate clock rate of parent clock in Hz
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* @param rate required clock rate for this clock
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* @return divider which should be used
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*/
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static int clk_div7_1_get_divider(unsigned long parent_rate,
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static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
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unsigned long rate)
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{
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u64 divider = parent_rate * 2;
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unsigned max_divider = 1 << divider_bits;
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divider += rate - 1;
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do_div(divider, rate);
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@ -534,7 +538,7 @@ static int clk_div7_1_get_divider(unsigned long parent_rate,
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if ((s64)divider - 2 < 0)
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return 0;
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if ((s64)divider - 2 > 255)
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if ((s64)divider - 2 >= max_divider)
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return -1;
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return divider - 2;
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@ -572,6 +576,7 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
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* required child clock rate. This function assumes that a second-stage
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* divisor is available which can divide by powers of 2 from 1 to 256.
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*
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* @param divider_bits number of divider bits (8 or 16)
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* @param parent_rate clock rate of parent clock in Hz
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* @param rate required clock rate for this clock
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* @param extra_div value for the second-stage divisor (not set if this
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@ -579,8 +584,8 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
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* @return divider which should be used, or -1 if nothing is valid
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*
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*/
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static int find_best_divider(unsigned long parent_rate, unsigned long rate,
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int *extra_div)
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static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
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unsigned long rate, int *extra_div)
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{
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int shift;
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int best_divider = -1;
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@ -589,7 +594,8 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate,
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/* try dividers from 1 to 256 and find closest match */
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for (shift = 0; shift <= 8 && best_error > 0; shift++) {
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unsigned divided_parent = parent_rate >> shift;
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int divider = clk_div7_1_get_divider(divided_parent, rate);
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int divider = clk_get_divider(divider_bits, divided_parent,
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rate);
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unsigned effective_rate = get_rate_from_divider(divided_parent,
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divider);
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int error = rate - effective_rate;
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@ -615,10 +621,11 @@ static int find_best_divider(unsigned long parent_rate, unsigned long rate,
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* @param periph_id peripheral to start
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* @param source PLL id of required parent clock
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* @param mux_bits Set to number of bits in mux register: 2 or 4
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* @param divider_bits Set to number of divider bits (8 or 16)
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* @return mux value (0-4, or -1 if not found)
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*/
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static int get_periph_clock_source(enum periph_id periph_id,
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enum clock_id parent, int *mux_bits)
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enum clock_id parent, int *mux_bits, int *divider_bits)
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{
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enum clock_type_id type;
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enum periphc_internal_id internal_id;
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@ -632,11 +639,18 @@ static int get_periph_clock_source(enum periph_id periph_id,
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type = clock_periph_type[internal_id];
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assert(clock_type_id_isvalid(type));
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/* Special case here for the clock with a 4-bit source mux */
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/*
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* Special cases here for the clock with a 4-bit source mux and I2C
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* with its 16-bit divisor
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*/
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if (type == CLOCK_TYPE_PCXTS)
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*mux_bits = 4;
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else
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*mux_bits = 2;
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if (type == CLOCK_TYPE_PCMT16)
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*divider_bits = 16;
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else
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*divider_bits = 8;
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for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
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if (clock_source[type][mux] == parent)
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@ -662,24 +676,22 @@ static int get_periph_clock_source(enum periph_id periph_id,
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* Adjust peripheral PLL to use the given divider and source.
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*
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* @param periph_id peripheral to adjust
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* @param parent Required parent clock (for source mux)
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* @param divider Required divider in 7.1 format
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* @param source Source number (0-3 or 0-7)
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* @param mux_bits Number of mux bits (2 or 4)
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* @param divider Required divider in 7.1 or 15.1 format
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* @return 0 if ok, -1 on error (requesting a parent clock which is not valid
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* for this peripheral)
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*/
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static int adjust_periph_pll(enum periph_id periph_id,
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enum clock_id parent, unsigned divider)
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static int adjust_periph_pll(enum periph_id periph_id, int source,
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int mux_bits, unsigned divider)
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{
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u32 *reg = get_periph_source_reg(periph_id);
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unsigned source;
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int mux_bits;
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clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
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divider << OUT_CLK_DIVISOR_SHIFT);
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udelay(1);
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/* work out the source clock and set it */
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source = get_periph_clock_source(periph_id, parent, &mux_bits);
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if (source < 0)
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return -1;
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if (mux_bits == 4) {
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@ -697,14 +709,21 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
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enum clock_id parent, unsigned rate, int *extra_div)
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{
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unsigned effective_rate;
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int mux_bits, divider_bits, source;
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int divider;
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/* work out the source clock and set it */
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source = get_periph_clock_source(periph_id, parent, &mux_bits,
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÷r_bits);
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if (extra_div)
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divider = find_best_divider(pll_rate[parent], rate, extra_div);
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divider = find_best_divider(divider_bits, pll_rate[parent],
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rate, extra_div);
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else
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divider = clk_div7_1_get_divider(pll_rate[parent], rate);
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divider = clk_get_divider(divider_bits, pll_rate[parent],
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rate);
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assert(divider >= 0);
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if (adjust_periph_pll(periph_id, parent, divider))
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if (adjust_periph_pll(periph_id, source, mux_bits, divider))
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return -1U;
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debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
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get_periph_source_reg(periph_id),
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@ -125,9 +125,15 @@ struct clk_rst_ctlr {
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#define OSC_FREQ_SHIFT 30
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#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
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/* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 */
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/*
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* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
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* but can be 16. We could use knowledge we have to restrict the mask in
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* the 8-bit cases (the divider_bits value returned by
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* get_periph_clock_source()) but it does not seem worth it since the code
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* already checks the ranges of values it is writing, in clk_get_divider().
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*/
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#define OUT_CLK_DIVISOR_SHIFT 0
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#define OUT_CLK_DIVISOR_MASK (255 << OUT_CLK_DIVISOR_SHIFT)
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#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
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#define OUT_CLK_SOURCE_SHIFT 30
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#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
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