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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

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This switches all boards with the Allwinner H616/H618/H313/H700 SoCs over to
use OF_UPSTREAM. We are doing it for this SoC family only since the DTs
between the U-Boot and the kernel repo are exactly identical, whereas other
families have one compatibility fix in U-Boot to allow booting older kernels.
Other will follow if this plays out well.

The biggest chunk otherwise is adding support for an Anbernic game console,
using the H700 SoC. For that we need to enhance the DRAM support code, and
pick two DT commits from the mainline kernel/DT rebasing repo, followed
by the defconfig patch.

On top of that two small fixes for the old Allwinner A80.

Gitlab CI passed, and I booted that briefly on some boards, including an
H616 and an H618 one (with LPDDR4).
This commit is contained in:
Tom Rini 2024-10-13 20:25:41 -06:00
commit 29e5dbc55c
35 changed files with 162 additions and 3319 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/dts/Makefile
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@ -721,13 +721,6 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-pine-h64-model-b.dtb \
sun50i-h6-tanix-tx6.dtb \
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h313-tanix-tx1.dtb \
sun50i-h616-orangepi-zero2.dtb \
sun50i-h618-orangepi-zero2w.dtb \
sun50i-h618-orangepi-zero3.dtb \
sun50i-h618-transpeed-8k618-t.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \

183
arch/arm/dts/sun50i-h313-tanix-tx1.dts
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@ -1,183 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Tanix TX1";
compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616";
aliases {
serial0 = &uart0;
ethernet0 = &sdio_wifi;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
key {
label = "hidden";
linux,code = <BTN_0>;
gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */
};
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_BLUE>;
gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
default-state = "on";
};
};
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
pinctrl-0 = <&x32clk_fanout_pin>;
pinctrl-names = "default";
reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC input */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci0 {
status = "okay";
};
&ir {
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
sdio_wifi: wifi@1 {
reg = <1>;
};
};
&mmc2 {
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_aldo1>;
bus-width = <8>;
non-removable;
max-frequency = <100000000>;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
status = "okay";
};
&ohci0 {
status = "okay";
};
&pio {
vcc-pc-supply = <&reg_aldo1>;
vcc-pf-supply = <&reg_dldo1>;
vcc-pg-supply = <&reg_aldo1>;
vcc-ph-supply = <&reg_dldo1>;
vcc-pi-supply = <&reg_dldo1>;
};
&r_i2c {
status = "okay";
axp313: pmic@36 {
compatible = "x-powers,axp313a";
reg = <0x36>;
#interrupt-cells = <1>;
interrupt-controller;
vin1-supply = <&reg_vcc5v>;
vin2-supply = <&reg_vcc5v>;
vin3-supply = <&reg_vcc5v>;
regulators {
/* Supplies VCC-PLL, so needs to be always on. */
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8";
};
/* Supplies VCC-IO, so needs to be always on. */
reg_dldo1: dldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3";
};
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdc2: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1120000>;
regulator-name = "vdd-cpu";
};
reg_dcdc3: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vdd-dram";
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbotg {
dr_mode = "host"; /* USB A type receptable */
status = "okay";
};
&usbphy {
status = "okay";
};

35
arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts
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@ -1,35 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>.
*/
/dts-v1/;
#include "sun50i-h616-bigtreetech-cb1.dtsi"
/ {
model = "BigTreeTech CB1";
compatible = "bigtreetech,cb1-manta", "bigtreetech,cb1", "allwinner,sun50i-h616";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&ehci1 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

143
arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi
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@ -1,143 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
ethernet0 = &rtl8189ftv;
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
};
};
reg_vcc5v: regulator-vcc5v {
/* board wide 5V supply from carrier boards */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_vcc33_wifi: vcc33-wifi {
compatible = "regulator-fixed";
regulator-name = "vcc33-wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_vcc5v>;
};
reg_vcc_wifi_io: vcc-wifi-io {
compatible = "regulator-fixed";
regulator-name = "vcc-wifi-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&reg_vcc33_wifi>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clock-names = "ext_clock";
reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
post-power-on-delay-ms = <200>;
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&mmc0 {
vmmc-supply = <&reg_dldo1>;
/* Card detection pin is not connected */
broken-cd;
bus-width = <4>;
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_vcc33_wifi>;
vqmmc-supply = <&reg_vcc_wifi_io>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
mmc-ddr-1_8v;
status = "okay";
rtl8189ftv: wifi@1 {
reg = <1>;
};
};
&r_i2c {
status = "okay";
axp313a: pmic@36 {
compatible = "x-powers,axp313a";
reg = <0x36>;
interrupt-controller;
#interrupt-cells = <1>;
regulators {
reg_dcdc1: dcdc1 {
regulator-name = "vdd-gpu-sys";
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-always-on;
};
reg_dcdc2: dcdc2 {
regulator-name = "vdd-cpu";
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-ramp-delay = <200>;
regulator-always-on;
};
reg_dcdc3: dcdc3 {
regulator-name = "vcc-dram";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reg_aldo1: aldo1 {
regulator-name = "vcc-1v8-pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_dldo1: dldo1 {
regulator-name = "vcc-3v3-io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&usbphy {
status = "okay";
};

63
arch/arm/dts/sun50i-h616-bigtreetech-pi.dts
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@ -1,63 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Martin Botka <martin@biqu3d.com>.
*/
/dts-v1/;
#include "sun50i-h616-bigtreetech-cb1.dtsi"
/ {
model = "BigTreeTech Pi";
compatible = "bigtreetech,pi", "allwinner,sun50i-h616";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&ir {
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

115
arch/arm/dts/sun50i-h616-cpu-opp.dtsi
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@ -1,115 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2023 Martin Botka <martin@somainline.org>
/ {
cpu_opp_table: opp-table-cpu {
compatible = "allwinner,sun50i-h616-operating-points";
nvmem-cells = <&cpu_speed_grade>;
opp-shared;
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x1f>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x12>;
};
opp-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x0d>;
};
opp-792000000 {
opp-hz = /bits/ 64 <792000000>;
opp-microvolt-speed1 = <900000>;
opp-microvolt-speed4 = <940000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x12>;
};
opp-936000000 {
opp-hz = /bits/ 64 <936000000>;
opp-microvolt = <900000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x0d>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt-speed0 = <950000>;
opp-microvolt-speed1 = <940000>;
opp-microvolt-speed2 = <950000>;
opp-microvolt-speed3 = <950000>;
opp-microvolt-speed4 = <1020000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x1f>;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt-speed0 = <1000000>;
opp-microvolt-speed2 = <1000000>;
opp-microvolt-speed3 = <1000000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x0d>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt-speed0 = <1050000>;
opp-microvolt-speed1 = <1020000>;
opp-microvolt-speed2 = <1050000>;
opp-microvolt-speed3 = <1050000>;
opp-microvolt-speed4 = <1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x1f>;
};
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x1d>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x0d>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt-speed1 = <1100000>;
opp-microvolt-speed3 = <1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
opp-supported-hw = <0x0a>;
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opp_table>;
};
&cpu1 {
operating-points-v2 = <&cpu_opp_table>;
};
&cpu2 {
operating-points-v2 = <&cpu_opp_table>;
};
&cpu3 {
operating-points-v2 = <&cpu_opp_table>;
};

131
arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
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@ -1,131 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Arm Ltd.
*
* DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.
* Excludes PMIC nodes and properties, since they are different between the two.
*/
#include "sun50i-h616.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
ethernet0 = &emac0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
default-state = "on";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
};
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the USB-C socket */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_vcc5v>;
enable-active-high;
gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
};
};
&ehci1 {
status = "okay";
};
/* USB 2 & 3 are on headers only. */
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
phy-handle = <&ext_rgmii_phy>;
status = "okay";
};
&mdio0 {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
status = "okay";
};
&ohci1 {
status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbotg {
/*
* PHY0 pins are connected to a USB-C socket, but a role switch
* is not implemented: both CC pins are pulled to GND.
* The VBUS pins power the device, so a fixed peripheral mode
* is the best choice.
* The board can be powered via GPIOs, in this case port0 *can*
* act as a host (with a cable/adapter ignoring CC), as VBUS is
* then provided by the GPIOs. Any user of this setup would
* need to adjust the DT accordingly: dr_mode set to "host",
* enabling OHCI0 and EHCI0.
*/
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

145
arch/arm/dts/sun50i-h616-orangepi-zero2.dts
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@ -1,145 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616-orangepi-zero.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
/ {
model = "OrangePi Zero2";
compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
};
&cpu0 {
cpu-supply = <&reg_dcdca>;
};
&emac0 {
allwinner,rx-delay-ps = <3100>;
allwinner,tx-delay-ps = <700>;
phy-mode = "rgmii";
phy-supply = <&reg_dcdce>;
};
&mmc0 {
vmmc-supply = <&reg_dcdce>;
};
&r_rsb {
status = "okay";
axp305: pmic@745 {
compatible = "x-powers,axp305", "x-powers,axp805",
"x-powers,axp806";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x745>;
x-powers,self-working-mode;
vina-supply = <&reg_vcc5v>;
vinb-supply = <&reg_vcc5v>;
vinc-supply = <&reg_vcc5v>;
vind-supply = <&reg_vcc5v>;
vine-supply = <&reg_vcc5v>;
aldoin-supply = <&reg_vcc5v>;
bldoin-supply = <&reg_vcc5v>;
cldoin-supply = <&reg_vcc5v>;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-sys";
};
reg_aldo2: aldo2 { /* 3.3V on headers */
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3-ext";
};
reg_aldo3: aldo3 { /* 3.3V on headers */
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3-ext2";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8";
};
bldo2 {
/* unused */
};
bldo3 {
/* unused */
};
bldo4 {
/* unused */
};
cldo1 {
/* reserved */
};
cldo2 {
/* unused */
};
cldo3 {
/* unused */
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vdd-dram";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-eth-mmc";
};
sw {
/* unused */
};
};
};
};
&pio {
vcc-pc-supply = <&reg_aldo1>;
vcc-pf-supply = <&reg_aldo1>;
vcc-pg-supply = <&reg_bldo1>;
vcc-ph-supply = <&reg_aldo1>;
vcc-pi-supply = <&reg_aldo1>;
};

207
arch/arm/dts/sun50i-h616-x96-mate.dts
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@ -1,207 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "X96 Mate";
compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC input */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&cpu0 {
cpu-supply = <&reg_dcdca>;
};
&ehci0 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ir {
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_dcdce>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
status = "okay";
};
&mmc2 {
vmmc-supply = <&reg_dcdce>;
vqmmc-supply = <&reg_bldo1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&r_rsb {
status = "okay";
axp305: pmic@745 {
compatible = "x-powers,axp305", "x-powers,axp805",
"x-powers,axp806";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x745>;
x-powers,self-working-mode;
vina-supply = <&reg_vcc5v>;
vinb-supply = <&reg_vcc5v>;
vinc-supply = <&reg_vcc5v>;
vind-supply = <&reg_vcc5v>;
vine-supply = <&reg_vcc5v>;
aldoin-supply = <&reg_vcc5v>;
bldoin-supply = <&reg_vcc5v>;
cldoin-supply = <&reg_vcc5v>;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-sys";
};
/* Enabled by the Android BSP */
reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3-ext";
status = "disabled";
};
/* Enabled by the Android BSP */
reg_aldo3: aldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3-ext2";
status = "disabled";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8";
};
/* Enabled by the Android BSP */
reg_bldo2: bldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8-2";
status = "disabled";
};
bldo3 {
/* unused */
};
bldo4 {
/* unused */
};
cldo1 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc2v5";
};
cldo2 {
/* unused */
};
cldo3 {
/* unused */
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <1360000>;
regulator-max-microvolt = <1360000>;
regulator-name = "vdd-dram";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-eth-mmc";
};
sw {
/* unused */
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbotg {
dr_mode = "host"; /* USB A type receptable */
status = "okay";
};
&usbphy {
status = "okay";
};

930
arch/arm/dts/sun50i-h616.dtsi
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@ -1,930 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2020 Arm Ltd.
// based on the H6 dtsi, which is:
// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h616-ccu.h>
#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/sun50i-h616-ccu.h>
#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
clocks = <&ccu CLK_CPUX>;
#cooling-cells = <2>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* 256 KiB reserved for Trusted Firmware-A (BL31).
* This is added by BL31 itself, but some bootloaders fail
* to propagate this into the DTB handed to kernels.
*/
secmon@40000000 {
reg = <0x0 0x40000000 0x0 0x40000>;
no-map;
};
};
osc24M: osc24M-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
arm,no-tick-in-suspend;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h616-system-control";
reg = <0x03000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@28000 {
compatible = "mmio-sram";
reg = <0x00028000 0x30000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00028000 0x30000>;
};
};
ccu: clock@3001000 {
compatible = "allwinner,sun50i-h616-ccu";
reg = <0x03001000 0x1000>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
dma: dma-controller@3002000 {
compatible = "allwinner,sun50i-h616-dma",
"allwinner,sun50i-a100-dma";
reg = <0x03002000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
clock-names = "bus", "mbus";
dma-channels = <16>;
dma-requests = <49>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <1>;
};
sid: efuse@3006000 {
compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
reg = <0x03006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
cpu_speed_grade: cpu-speed-grade@0 {
reg = <0x0 2>;
};
};
watchdog: watchdog@30090a0 {
compatible = "allwinner,sun50i-h616-wdt",
"allwinner,sun6i-a31-wdt";
reg = <0x030090a0 0x20>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h616-pinctrl";
reg = <0x0300b000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
ext_rgmii_pins: rgmii-pins {
pins = "PI0", "PI1", "PI2", "PI3", "PI4",
"PI5", "PI7", "PI8", "PI9", "PI10",
"PI11", "PI12", "PI13", "PI14", "PI15",
"PI16";
function = "emac0";
drive-strength = <40>;
};
i2c0_pins: i2c0-pins {
pins = "PI5", "PI6";
function = "i2c0";
};
i2c3_ph_pins: i2c3-ph-pins {
pins = "PH4", "PH5";
function = "i2c3";
};
ir_rx_pin: ir-rx-pin {
pins = "PH10";
function = "ir_rx";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
drive-strength = <30>;
bias-pull-up;
};
/omit-if-no-ref/
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
bias-pull-up;
};
mmc2_pins: mmc2-pins {
pins = "PC0", "PC1", "PC5", "PC6",
"PC8", "PC9", "PC10", "PC11",
"PC13", "PC14", "PC15", "PC16";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
/omit-if-no-ref/
spi0_pins: spi0-pins {
pins = "PC0", "PC2", "PC4";
function = "spi0";
};
/omit-if-no-ref/
spi0_cs0_pin: spi0-cs0-pin {
pins = "PC3";
function = "spi0";
};
/omit-if-no-ref/
spi1_pins: spi1-pins {
pins = "PH6", "PH7", "PH8";
function = "spi1";
};
/omit-if-no-ref/
spi1_cs0_pin: spi1-cs0-pin {
pins = "PH5";
function = "spi1";
};
spdif_tx_pin: spdif-tx-pin {
pins = "PH4";
function = "spdif";
};
uart0_ph_pins: uart0-ph-pins {
pins = "PH0", "PH1";
function = "uart0";
};
/omit-if-no-ref/
uart1_pins: uart1-pins {
pins = "PG6", "PG7";
function = "uart1";
};
/omit-if-no-ref/
uart1_rts_cts_pins: uart1-rts-cts-pins {
pins = "PG8", "PG9";
function = "uart1";
};
/omit-if-no-ref/
x32clk_fanout_pin: x32clk-fanout-pin {
pins = "PG10";
function = "clock";
};
};
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>,
<0x03022000 0x2000>,
<0x03024000 0x2000>,
<0x03026000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
mmc0: mmc@4020000 {
compatible = "allwinner,sun50i-h616-mmc",
"allwinner,sun50i-a100-mmc";
reg = <0x04020000 0x1000>;
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "disabled";
max-frequency = <150000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-3_3v;
cap-sdio-irq;
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@4021000 {
compatible = "allwinner,sun50i-h616-mmc",
"allwinner,sun50i-a100-mmc";
reg = <0x04021000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "disabled";
max-frequency = <150000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-3_3v;
cap-sdio-irq;
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@4022000 {
compatible = "allwinner,sun50i-h616-emmc",
"allwinner,sun50i-a100-emmc";
reg = <0x04022000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
status = "disabled";
max-frequency = <150000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-3_3v;
cap-sdio-irq;
#address-cells = <1>;
#size-cells = <0>;
};
uart0: serial@5000000 {
compatible = "snps,dw-apb-uart";
reg = <0x05000000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
dmas = <&dma 14>, <&dma 14>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
uart1: serial@5000400 {
compatible = "snps,dw-apb-uart";
reg = <0x05000400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
dmas = <&dma 15>, <&dma 15>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
uart2: serial@5000800 {
compatible = "snps,dw-apb-uart";
reg = <0x05000800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
dmas = <&dma 16>, <&dma 16>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
uart3: serial@5000c00 {
compatible = "snps,dw-apb-uart";
reg = <0x05000c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART3>;
dmas = <&dma 17>, <&dma 17>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
uart4: serial@5001000 {
compatible = "snps,dw-apb-uart";
reg = <0x05001000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART4>;
dmas = <&dma 18>, <&dma 18>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
uart5: serial@5001400 {
compatible = "snps,dw-apb-uart";
reg = <0x05001400 0x400>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART5>;
dmas = <&dma 19>, <&dma 19>;
dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART5>;
status = "disabled";
};
i2c0: i2c@5002000 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
dmas = <&dma 43>, <&dma 43>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@5002400 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002400 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
dmas = <&dma 44>, <&dma 44>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@5002800 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002800 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
dmas = <&dma 45>, <&dma 45>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@5002c00 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002c00 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
dmas = <&dma 46>, <&dma 46>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c4: i2c@5003000 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05003000 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C4>;
dmas = <&dma 47>, <&dma 47>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_I2C4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi0: spi@5010000 {
compatible = "allwinner,sun50i-h616-spi",
"allwinner,sun8i-h3-spi";
reg = <0x05010000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma 22>, <&dma 22>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@5011000 {
compatible = "allwinner,sun50i-h616-spi",
"allwinner,sun8i-h3-spi";
reg = <0x05011000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_SPI1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac0: ethernet@5020000 {
compatible = "allwinner,sun50i-h616-emac0",
"allwinner,sun50i-a64-emac";
reg = <0x05020000 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&ccu CLK_BUS_EMAC0>;
clock-names = "stmmaceth";
resets = <&ccu RST_BUS_EMAC0>;
reset-names = "stmmaceth";
syscon = <&syscon>;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
spdif: spdif@5093000 {
compatible = "allwinner,sun50i-h616-spdif";
reg = <0x05093000 0x400>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
clock-names = "apb", "spdif";
resets = <&ccu RST_BUS_SPDIF>;
dmas = <&dma 2>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pin>;
#sound-dai-cells = <0>;
status = "disabled";
};
ths: thermal-sensor@5070400 {
compatible = "allwinner,sun50i-h616-ths";
reg = <0x05070400 0x400>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>;
clock-names = "bus";
resets = <&ccu RST_BUS_THS>;
nvmem-cells = <&ths_calibration>;
nvmem-cell-names = "calibration";
allwinner,sram = <&syscon>;
#thermal-sensor-cells = <1>;
};
usbotg: usb@5100000 {
compatible = "allwinner,sun50i-h616-musb",
"allwinner,sun8i-h3-musb";
reg = <0x05100000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
status = "disabled";
};
usbphy: phy@5100400 {
compatible = "allwinner,sun50i-h616-usb-phy";
reg = <0x05100400 0x24>,
<0x05101800 0x14>,
<0x05200800 0x14>,
<0x05310800 0x14>,
<0x05311800 0x14>;
reg-names = "phy_ctrl",
"pmu0",
"pmu1",
"pmu2",
"pmu3";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>,
<&ccu CLK_USB_PHY2>,
<&ccu CLK_USB_PHY3>,
<&ccu CLK_BUS_EHCI2>;
clock-names = "usb0_phy",
"usb1_phy",
"usb2_phy",
"usb3_phy",
"pmu2_clk";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>,
<&ccu RST_USB_PHY2>,
<&ccu RST_USB_PHY3>;
reset-names = "usb0_reset",
"usb1_reset",
"usb2_reset",
"usb3_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@5101000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05101000 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_BUS_EHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ohci0: usb@5101400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05101400 0x100>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ehci1: usb@5200000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05200000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_BUS_EHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>,
<&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@5200400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05200400 0x100>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ehci2: usb@5310000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05310000 0x100>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI2>,
<&ccu CLK_BUS_EHCI2>,
<&ccu CLK_USB_OHCI2>;
resets = <&ccu RST_BUS_OHCI2>,
<&ccu RST_BUS_EHCI2>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ohci2: usb@5310400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05310400 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI2>,
<&ccu CLK_USB_OHCI2>;
resets = <&ccu RST_BUS_OHCI2>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ehci3: usb@5311000 {
compatible = "allwinner,sun50i-h616-ehci",
"generic-ehci";
reg = <0x05311000 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI3>,
<&ccu CLK_BUS_EHCI3>,
<&ccu CLK_USB_OHCI3>;
resets = <&ccu RST_BUS_OHCI3>,
<&ccu RST_BUS_EHCI3>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
};
ohci3: usb@5311400 {
compatible = "allwinner,sun50i-h616-ohci",
"generic-ohci";
reg = <0x05311400 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI3>,
<&ccu CLK_USB_OHCI3>;
resets = <&ccu RST_BUS_OHCI3>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
};
rtc: rtc@7000000 {
compatible = "allwinner,sun50i-h616-rtc";
reg = <0x07000000 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
<&ccu CLK_PLL_SYSTEM_32K>;
clock-names = "bus", "hosc",
"pll-32k";
#clock-cells = <1>;
};
r_ccu: clock@7010000 {
compatible = "allwinner,sun50i-h616-r-ccu";
reg = <0x07010000 0x210>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};
nmi_intc: interrupt-controller@7010320 {
compatible = "allwinner,sun50i-h616-nmi",
"allwinner,sun9i-a80-nmi";
reg = <0x07010320 0xc>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
};
r_pio: pinctrl@7022000 {
compatible = "allwinner,sun50i-h616-r-pinctrl";
reg = <0x07022000 0x400>;
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
/omit-if-no-ref/
r_i2c_pins: r-i2c-pins {
pins = "PL0", "PL1";
function = "s_i2c";
};
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
};
};
ir: ir@7040000 {
compatible = "allwinner,sun50i-h616-ir",
"allwinner,sun6i-a31-ir";
reg = <0x07040000 0x400>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1_IR>,
<&r_ccu CLK_IR>;
clock-names = "apb", "ir";
resets = <&r_ccu RST_R_APB1_IR>;
pinctrl-names = "default";
pinctrl-0 = <&ir_rx_pin>;
status = "disabled";
};
r_i2c: i2c@7081400 {
compatible = "allwinner,sun50i-h616-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x07081400 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_I2C>;
dmas = <&dma 48>, <&dma 48>;
dma-names = "rx", "tx";
resets = <&r_ccu RST_R_APB2_I2C>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
r_rsb: rsb@7083000 {
compatible = "allwinner,sun50i-h616-rsb",
"allwinner,sun8i-a23-rsb";
reg = <0x07083000 0x400>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_RSB>;
clock-frequency = <3000000>;
resets = <&r_ccu RST_R_APB2_RSB>;
pinctrl-names = "default";
pinctrl-0 = <&r_rsb_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <500>;
polling-delay = <1000>;
thermal-sensors = <&ths 2>;
sustainable-power = <1000>;
trips {
cpu_threshold: cpu-trip-0 {
temperature = <60000>;
type = "passive";
hysteresis = <0>;
};
cpu_target: cpu-trip-1 {
temperature = <70000>;
type = "passive";
hysteresis = <0>;
};
cpu_critical: cpu-trip-2 {
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
};
gpu-thermal {
polling-delay-passive = <500>;
polling-delay = <1000>;
thermal-sensors = <&ths 0>;
sustainable-power = <1100>;
trips {
gpu_temp_critical: gpu-trip-0 {
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
};
ve-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 1>;
trips {
ve_temp_critical: ve-trip-0 {
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
};
ddr-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 3>;
trips {
ddr_temp_critical: ddr-trip-0 {
temperature = <110000>;
type = "critical";
hysteresis = <0>;
};
};
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) Jisheng Zhang <jszhang@kernel.org>
*/
#include "sun50i-h616.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_aldo1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
status = "okay";
};
&r_i2c {
status = "okay";
axp313: pmic@36 {
compatible = "x-powers,axp313a";
reg = <0x36>;
#interrupt-cells = <1>;
interrupt-controller;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8-pll";
};
reg_dldo1: dldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3-io";
};
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdc2: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdc3: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-dram";
};
};
};
};
&pio {
vcc-pc-supply = <&reg_dldo1>;
vcc-pf-supply = <&reg_dldo1>;
vcc-pg-supply = <&reg_aldo1>;
vcc-ph-supply = <&reg_dldo1>;
vcc-pi-supply = <&reg_dldo1>;
};

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arch/arm/dts/sun50i-h618-longanpi-3h.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) Jisheng Zhang <jszhang@kernel.org>
*/
/dts-v1/;
#include "sun50i-h618-longan-module-3h.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Sipeed Longan Pi 3H";
compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618";
aliases {
ethernet0 = &emac0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_ORANGE>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <0>;
gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
};
led-1 {
color = <LED_COLOR_ID_ORANGE>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */
};
};
reg_vcc5v: regulator-vcc5v {
/* board wide 5V supply directly from the USB-C socket */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_vcc5v>;
};
};
&axp313 {
vin1-supply = <&reg_vcc5v>;
vin2-supply = <&reg_vcc5v>;
vin3-supply = <&reg_vcc5v>;
};
&ehci1 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&ehci2 {
status = "okay";
};
&ohci2 {
status = "okay";
};
/* WiFi & BT combo module is connected to this Host */
&ehci3 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
allwinner,rx-delay-ps = <3100>;
allwinner,tx-delay-ps = <700>;
phy-supply = <&reg_vcc3v3>;
status = "okay";
};
&mdio0 {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&uart0 {
status = "okay";
};
&usbotg {
/*
* PHY0 pins are connected to a USB-C socket, but a role switch
* is not implemented: both CC pins are pulled to GND.
* The VBUS pins power the device, so a fixed peripheral mode
* is the best choice.
* The board can be powered via GPIOs, in this case port0 *can*
* act as a host (with a cable/adapter ignoring CC), as VBUS is
* then provided by the GPIOs. Any user of this setup would
* need to adjust the DT accordingly: dr_mode set to "host",
* enabling OHCI0 and EHCI0.
*/
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_vcc5v>;
usb2_vbus-supply = <&reg_vcc5v>;
status = "okay";
};

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arch/arm/dts/sun50i-h618-orangepi-zero2w.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
/ {
model = "OrangePi Zero 2W";
compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
};
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the USB-C socket */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_vcc3v3: vcc3v3 {
/* SY8089 DC/DC converter */
compatible = "regulator-fixed";
regulator-name = "vcc-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_vcc5v>;
regulator-always-on;
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci1 {
status = "okay";
};
/* USB 2 & 3 are on the FPC connector (or the exansion board) */
&mmc0 {
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&ohci1 {
status = "okay";
};
&pio {
vcc-pc-supply = <&reg_dldo1>;
vcc-pf-supply = <&reg_dldo1>; /* internally via VCC-IO */
vcc-pg-supply = <&reg_aldo1>;
vcc-ph-supply = <&reg_dldo1>; /* internally via VCC-IO */
vcc-pi-supply = <&reg_dldo1>;
};
&r_i2c {
status = "okay";
axp313: pmic@36 {
compatible = "x-powers,axp313a";
reg = <0x36>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
vin1-supply = <&reg_vcc5v>;
vin2-supply = <&reg_vcc5v>;
vin3-supply = <&reg_vcc5v>;
regulators {
/* Supplies VCC-PLL and DRAM */
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8";
};
/* Supplies VCC-IO, so needs to be always on. */
reg_dldo1: dldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3";
};
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdc2: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdc3: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-dram";
};
};
};
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbotg {
/*
* PHY0 pins are connected to a USB-C socket, but a role switch
* is not implemented: both CC pins are pulled to GND.
* The VBUS pins power the device, so a fixed peripheral mode
* is the best choice.
* The board can be powered via GPIOs, in this case port0 *can*
* act as a host (with a cable/adapter ignoring CC), as VBUS is
* then provided by the GPIOs. Any user of this setup would
* need to adjust the DT accordingly: dr_mode set to "host",
* enabling OHCI0 and EHCI0.
*/
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_vcc5v>;
status = "okay";
};

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arch/arm/dts/sun50i-h618-orangepi-zero3.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616-orangepi-zero.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
/ {
model = "OrangePi Zero3";
compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&emac0 {
allwinner,tx-delay-ps = <700>;
phy-mode = "rgmii-rxid";
phy-supply = <&reg_dldo1>;
};
&ext_rgmii_phy {
motorcomm,clk-out-frequency-hz = <125000000>;
};
&mmc0 {
/*
* The schematic shows the card detect pin wired up to PF6, via an
* inverter, but it just doesn't work.
*/
broken-cd;
vmmc-supply = <&reg_dldo1>;
};
&r_i2c {
status = "okay";
axp313: pmic@36 {
compatible = "x-powers,axp313a";
reg = <0x36>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
vin1-supply = <&reg_vcc5v>;
vin2-supply = <&reg_vcc5v>;
vin3-supply = <&reg_vcc5v>;
regulators {
/* Supplies VCC-PLL, so needs to be always on. */
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8";
};
/* Supplies VCC-IO, so needs to be always on. */
reg_dldo1: dldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3";
};
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdc2: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdc3: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-dram";
};
};
};
};
&pio {
vcc-pc-supply = <&reg_dldo1>;
vcc-pf-supply = <&reg_dldo1>;
vcc-pg-supply = <&reg_aldo1>;
vcc-ph-supply = <&reg_dldo1>;
vcc-pi-supply = <&reg_dldo1>;
};

189
arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts
View File

@ -1,189 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include "sun50i-h616-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Transpeed 8K618-T";
compatible = "transpeed,8k618-t", "allwinner,sun50i-h618";
aliases {
ethernet1 = &sdio_wifi;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC input */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_vcc3v3: vcc3v3 {
/* discrete 3.3V regulator */
compatible = "regulator-fixed";
regulator-name = "vcc-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
pinctrl-0 = <&x32clk_fanout_pin>;
pinctrl-names = "default";
reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&ir {
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_dldo1>;
cd-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */
bus-width = <4>;
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
sdio_wifi: wifi@1 {
reg = <1>;
};
};
&mmc2 {
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_aldo1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&r_i2c {
status = "okay";
axp313: pmic@36 {
compatible = "x-powers,axp313a";
reg = <0x36>;
#interrupt-cells = <1>;
interrupt-controller;
vin1-supply = <&reg_vcc5v>;
vin2-supply = <&reg_vcc5v>;
vin3-supply = <&reg_vcc5v>;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8-pll";
};
reg_dldo1: dldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3-io-mmc";
};
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdc2: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdc3: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1360000>;
regulator-max-microvolt = <1360000>;
regulator-name = "vdd-dram";
};
};
};
};
&pio {
vcc-pc-supply = <&reg_aldo1>;
vcc-pg-supply = <&reg_dldo1>;
vcc-ph-supply = <&reg_dldo1>;
vcc-pi-supply = <&reg_dldo1>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
uart-has-rtscts;
status = "okay";
};
&usbotg {
dr_mode = "host"; /* USB A type receptable */
status = "okay";
};
&usbphy {
status = "okay";
};

327
arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts
View File

@ -1,327 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Anbernic RG35XX 2024";
chassis-type = "handset";
compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio_keys_gamepad: gpio-keys-gamepad {
compatible = "gpio-keys";
button-a {
label = "Action-Pad A";
gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_EAST>;
};
button-b {
label = "Action-Pad B";
gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_SOUTH>;
};
button-down {
label = "D-Pad Down";
gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_DPAD_DOWN>;
};
button-l1 {
label = "Key L1";
gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_TL>;
};
button-l2 {
label = "Key L2";
gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_TL2>;
};
button-left {
label = "D-Pad left";
gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_DPAD_LEFT>;
};
button-menu {
label = "Key Menu";
gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_MODE>;
};
button-r1 {
label = "Key R1";
gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_TR>;
};
button-r2 {
label = "Key R2";
gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_TR2>;
};
button-right {
label = "D-Pad Right";
gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_DPAD_RIGHT>;
};
button-select {
label = "Key Select";
gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_SELECT>;
};
button-start {
label = "Key Start";
gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_START>;
};
button-up {
label = "D-Pad Up";
gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_DPAD_UP>;
};
button-x {
label = "Action-Pad X";
gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_NORTH>;
};
button-y {
label = "Action Pad Y";
gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_WEST>;
};
};
gpio-keys-volume {
compatible = "gpio-keys";
autorepeat;
button-vol-up {
label = "Key Volume Up";
gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEUP>;
};
button-vol-down {
label = "Key Volume Down";
gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */
default-state = "on";
};
};
reg_vcc5v: regulator-vcc5v { /* USB-C power input */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&cpu0 {
cpu-supply = <&reg_dcdc1>;
};
&ehci0 {
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_cldo3>;
disable-wp;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
status = "okay";
};
&ohci0 {
status = "okay";
};
&pio {
vcc-pa-supply = <&reg_cldo3>;
vcc-pc-supply = <&reg_cldo3>;
vcc-pe-supply = <&reg_cldo3>;
vcc-pf-supply = <&reg_cldo3>;
vcc-pg-supply = <&reg_aldo4>;
vcc-ph-supply = <&reg_cldo3>;
vcc-pi-supply = <&reg_cldo3>;
};
&r_rsb {
status = "okay";
axp717: pmic@3a3 {
compatible = "x-powers,axp717";
reg = <0x3a3>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
vin1-supply = <&reg_vcc5v>;
vin2-supply = <&reg_vcc5v>;
vin3-supply = <&reg_vcc5v>;
vin4-supply = <&reg_vcc5v>;
regulators {
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdc2: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <940000>;
regulator-max-microvolt = <940000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdc3: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-dram";
};
reg_aldo1: aldo1 {
/* 1.8v - unused */
};
reg_aldo2: aldo2 {
/* 1.8v - unused */
};
reg_aldo3: aldo3 {
/* 1.8v - unused */
};
reg_aldo4: aldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-pg";
};
reg_bldo1: bldo1 {
/* 1.8v - unused */
};
reg_bldo2: bldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-pll";
};
reg_bldo3: bldo3 {
/* 2.8v - unused */
};
reg_bldo4: bldo4 {
/* 1.2v - unused */
};
reg_cldo1: cldo1 {
/* 3.3v - audio codec - not yet implemented */
};
reg_cldo2: cldo2 {
/* 3.3v - unused */
};
reg_cldo3: cldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-io";
};
reg_cldo4: cldo4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
reg_boost: boost {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5200000>;
regulator-name = "boost";
};
reg_cpusldo: cpusldo {
/* unused */
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */
&usbotg {
dr_mode = "peripheral"; /* USB type-C receptable */
status = "okay";
};
&usbphy {
status = "okay";
};

36
arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts
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@ -1,36 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>.
* Copyright (C) 2024 Chris Morgan <macroalpha82@gmail.com>.
*/
#include "sun50i-h700-anbernic-rg35xx-plus.dts"
/ {
model = "Anbernic RG35XX H";
compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700";
};
&gpio_keys_gamepad {
button-thumbl {
label = "GPIO Thumb Left";
gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_THUMBL>;
};
button-thumbr {
label = "GPIO Thumb Right";
gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */
linux,input-type = <EV_KEY>;
linux,code = <BTN_THUMBR>;
};
};
&ehci1 {
status = "okay";
};
&ohci1 {
status = "okay";
};

53
arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts
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@ -1,53 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>.
*/
#include "sun50i-h700-anbernic-rg35xx-2024.dts"
/ {
model = "Anbernic RG35XX Plus";
compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700";
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
pinctrl-0 = <&x32clk_fanout_pin>;
pinctrl-names = "default";
post-power-on-delay-ms = <200>;
reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
};
};
/* SDIO WiFi RTL8821CS */
&mmc1 {
vmmc-supply = <&reg_cldo4>;
vqmmc-supply = <&reg_aldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
sdio_wifi: wifi@1 {
reg = <1>;
interrupt-parent = <&pio>;
interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */
interrupt-names = "host-wake";
};
};
/* Bluetooth RTL8821CS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */
host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */
};
};

18
arch/arm/mach-sunxi/Kconfig
View File

@ -108,6 +108,23 @@ config DRAM_SUN50I_H616_TPR12
default 0x0
help
TPR12 value from vendor DRAM settings.
choice
prompt "H616 PHY pin mapping selection"
default DRAM_SUN50I_H616_PHY_ADDR_MAP_0
config DRAM_SUN50I_H616_PHY_ADDR_MAP_0
bool "H313/H616/H618"
help
The pin mapping selection used by the H313, H616, H618, and
possibly other dies which use the H616 DRAM controller.
config DRAM_SUN50I_H616_PHY_ADDR_MAP_1
bool "H700"
help
The pin mapping selection used by the H700 and possibly other
dies which use the H616 DRAM controller.
endchoice
endif
config SUN6I_PRCM
@ -437,6 +454,7 @@ config MACH_SUN50I_H616
select ARM64
select DRAM_SUN50I_H616
select SUN50I_GEN_H6
imply OF_UPSTREAM
endchoice

143
arch/arm/mach-sunxi/dram_sun50i_h616.c
View File

@ -55,8 +55,8 @@ static void mbus_configure_port(u8 port,
writel_relaxed(cfg1, &mctl_com->master[port].cfg1);
}
#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
mbus_configure_port(port, bwlimit, false, \
#define MBUS_CONF(port, priority, qos, acs, bwl0, bwl1, bwl2) \
mbus_configure_port(port, true, priority, \
MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
static void mctl_set_master_priority(void)
@ -68,24 +68,25 @@ static void mctl_set_master_priority(void)
writel(399, &mctl_com->tmr);
writel(BIT(16), &mctl_com->bwcr);
MBUS_CONF( 0, true, HIGHEST, 0, 256, 128, 100);
MBUS_CONF( 1, true, HIGH, 0, 1536, 1400, 256);
MBUS_CONF( 2, true, HIGHEST, 0, 512, 256, 96);
MBUS_CONF( 3, true, HIGH, 0, 256, 100, 80);
MBUS_CONF( 4, true, HIGH, 2, 8192, 5500, 5000);
MBUS_CONF( 5, true, HIGH, 2, 100, 64, 32);
MBUS_CONF( 6, true, HIGH, 2, 100, 64, 32);
MBUS_CONF( 8, true, HIGH, 0, 256, 128, 64);
MBUS_CONF(11, true, HIGH, 0, 256, 128, 100);
MBUS_CONF(14, true, HIGH, 0, 1024, 256, 64);
MBUS_CONF(16, true, HIGHEST, 6, 8192, 2800, 2400);
MBUS_CONF(21, true, HIGHEST, 6, 2048, 768, 512);
MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32);
MBUS_CONF(26, true, HIGH, 2, 8192, 5500, 5000);
MBUS_CONF(37, true, HIGH, 0, 256, 128, 64);
MBUS_CONF(38, true, HIGH, 2, 100, 64, 32);
MBUS_CONF(39, true, HIGH, 2, 8192, 5500, 5000);
MBUS_CONF(40, true, HIGH, 2, 100, 64, 32);
MBUS_CONF(0, false, HIGHEST, 0, 256, 128, 100);
MBUS_CONF(1, false, HIGH, 0, 1536, 1400, 256);
MBUS_CONF(2, false, HIGHEST, 0, 512, 256, 96);
MBUS_CONF(3, false, HIGH, 0, 256, 100, 80);
MBUS_CONF(4, false, HIGH, 2, 8192, 5500, 5000);
MBUS_CONF(5, false, HIGH, 2, 100, 64, 32);
MBUS_CONF(6, false, HIGH, 2, 100, 64, 32);
MBUS_CONF(8, false, HIGH, 0, 256, 128, 64);
MBUS_CONF(11, false, HIGH, 0, 256, 128, 100);
MBUS_CONF(14, false, HIGH, 0, 1024, 256, 64);
MBUS_CONF(16, false, HIGHEST, 6, 8192, 2800, 2400);
MBUS_CONF(21, false, HIGHEST, 6, 2048, 768, 512);
MBUS_CONF(22, false, HIGH, 0, 256, 128, 100);
MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32);
MBUS_CONF(26, false, HIGH, 2, 8192, 5500, 5000);
MBUS_CONF(37, false, HIGH, 0, 256, 128, 64);
MBUS_CONF(38, false, HIGH, 2, 100, 64, 32);
MBUS_CONF(39, false, HIGH, 2, 8192, 5500, 5000);
MBUS_CONF(40, false, HIGH, 2, 100, 64, 32);
dmb();
}
@ -225,6 +226,26 @@ static void mctl_set_addrmap(const struct dram_config *config)
mctl_ctl->addrmap[8] = 0x3F3F;
}
#ifdef CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1
static const u8 phy_init[] = {
#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b,
0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a,
0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19,
0x06, 0x09, 0x0f
#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19,
0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
0x08, 0x01, 0x1a
#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
0x18, 0x04, 0x1a
#endif
};
#else /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */
static const u8 phy_init[] = {
#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333
0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,
@ -243,7 +264,7 @@ static const u8 phy_init[] = {
0x18, 0x03, 0x1a
#endif
};
#endif /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */
#define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f)
static void mctl_phy_configure_odt(const struct dram_para *para)
{
@ -293,14 +314,22 @@ static void mctl_phy_configure_odt(const struct dram_para *para)
dmb();
}
static bool mctl_phy_write_leveling(const struct dram_config *config)
static bool mctl_phy_write_leveling(const struct dram_para *para,
const struct dram_config *config)
{
bool result = true;
u32 val;
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x80);
writel(4, SUNXI_DRAM_PHY0_BASE + 0xc);
writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10);
if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
/* MR2 value */
writel(0x1b, SUNXI_DRAM_PHY0_BASE + 0xc);
writel(0, SUNXI_DRAM_PHY0_BASE + 0x10);
} else {
writel(4, SUNXI_DRAM_PHY0_BASE + 0xc);
writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10);
}
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
@ -859,9 +888,9 @@ static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para,
}
break;
case SUNXI_DRAM_TYPE_LPDDR4:
if (para->tpr2 & 1) {
writel(val, SUNXI_DRAM_PHY0_BASE + 0x788);
} else {
writel(val, SUNXI_DRAM_PHY0_BASE + 0x788);
if (config->ranks == 2) {
val = (para->tpr10 >> 11) & 0x1e;
writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
};
break;
@ -986,12 +1015,16 @@ static bool mctl_phy_init(const struct dram_para *para,
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, 0x20);
}
clrbits_le32(&mctl_com->unk_0x500, 0x200);
udelay(1);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8);
mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
udelay(1000);
writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58);
clrbits_le32(&mctl_com->unk_0x500, 0x200);
writel(0, &mctl_ctl->swctl);
setbits_le32(&mctl_ctl->dfimisc, 1);
@ -1010,6 +1043,8 @@ static bool mctl_phy_init(const struct dram_para *para,
mctl_await_completion(&mctl_ctl->swstat, 1, 1);
mctl_await_completion(&mctl_ctl->statr, 3, 1);
udelay(200);
writel(0, &mctl_ctl->swctl);
clrbits_le32(&mctl_ctl->dfimisc, 1);
@ -1080,19 +1115,27 @@ static bool mctl_phy_init(const struct dram_para *para,
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0xb04, &mctl_ctl->mrctrl1);
udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0xc72, &mctl_ctl->mrctrl1);
udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0xe09, &mctl_ctl->mrctrl1);
udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
writel(0x1624, &mctl_ctl->mrctrl1);
udelay(10);
writel(0x80000030, &mctl_ctl->mrctrl0);
udelay(10);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
break;
case SUNXI_DRAM_TYPE_DDR4:
@ -1108,7 +1151,7 @@ static bool mctl_phy_init(const struct dram_para *para,
if (para->tpr10 & TPR10_WRITE_LEVELING) {
for (i = 0; i < 5; i++)
if (mctl_phy_write_leveling(config))
if (mctl_phy_write_leveling(para, config))
break;
if (i == 5) {
debug("write leveling failed!\n");
@ -1234,9 +1277,6 @@ static bool mctl_ctrl_init(const struct dram_para *para,
setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30));
setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30));
if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
setbits_le32(&mctl_ctl->dbictl, 0x1);
setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
@ -1248,8 +1288,10 @@ static bool mctl_ctrl_init(const struct dram_para *para,
setbits_le32(&mctl_ctl->clken, BIT(8));
clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x300);
udelay(1);
/* this write seems to enable PHY MMIO region */
setbits_le32(&mctl_com->unk_0x500, BIT(24));
udelay(1);
if (!mctl_phy_init(para, config))
return false;
@ -1321,28 +1363,33 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para,
static void mctl_auto_detect_dram_size(const struct dram_para *para,
struct dram_config *config)
{
/* detect row address bits */
config->cols = 8;
unsigned int shift;
/* max. config for columns, but not rows */
config->cols = 11;
config->rows = 13;
mctl_core_init(para, config);
shift = config->bus_full_width + 1;
/* detect column address bits */
for (config->cols = 8; config->cols < 11; config->cols++) {
if (mctl_mem_matches(1ULL << (config->cols + shift)))
break;
}
debug("detected %u columns\n", config->cols);
/* reconfigure to make sure that all active rows are accessible */
config->rows = 18;
mctl_core_init(para, config);
/* detect row address bits */
shift = config->bus_full_width + 4 + config->cols;
for (config->rows = 13; config->rows < 18; config->rows++) {
/* 8 banks, 8 bit per byte and 16/32 bit width */
if (mctl_mem_matches((1 << (config->rows + config->cols +
4 + config->bus_full_width))))
break;
}
/* detect column address bits */
config->cols = 11;
mctl_core_init(para, config);
for (config->cols = 8; config->cols < 11; config->cols++) {
/* 8 bits per byte and 16/32 bit width */
if (mctl_mem_matches(1 << (config->cols + 1 +
config->bus_full_width)))
if (mctl_mem_matches(1ULL << (config->rows + shift)))
break;
}
debug("detected %u rows\n", config->rows);
}
static unsigned long mctl_calc_size(const struct dram_config *config)

2
arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
View File

@ -23,7 +23,7 @@ void mctl_set_timing_params(const struct dram_para *para)
u8 trcd = max(ns_to_t(18), 2);
u8 trc = ns_to_t(65);
u8 txp = max(ns_to_t(8), 2);
u8 trtp = max(ns_to_t(8), 4);
u8 trtp = 4;
u8 trp = ns_to_t(21);
u8 tras = ns_to_t(42);
u16 trefi = ns_to_t(3904) / 32;

5
board/sunxi/MAINTAINERS
View File

@ -132,6 +132,11 @@ M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/Ampe_A76_defconfig
ANBERNIC RG35XX-2024
M: Chris Morgan <macromorgan@hotmail.com>
S: Maintained
F: configs/anbernic_rg35xx_h700_defconfig
BANANAPI M1 PLUS
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

27
configs/anbernic_rg35xx_h700_defconfig Normal file
View File

@ -0,0 +1,27 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h700-anbernic-rg35xx-2024"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e
CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e
CONFIG_DRAM_SUN50I_H616_ODT_EN=0x7887bbbb
CONFIG_DRAM_SUN50I_H616_TPR2=0x1
CONFIG_DRAM_SUN50I_H616_TPR6=0x40808080
CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6633
CONFIG_DRAM_SUN50I_H616_TPR11=0x1b1f1e1c
CONFIG_DRAM_SUN50I_H616_TPR12=0x06060606
CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1=y
CONFIG_MACH_SUN50I_H616=y
CONFIG_SUNXI_DRAM_H616_LPDDR4=y
CONFIG_DRAM_CLK=672
CONFIG_R_I2C_ENABLE=y
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_REGULATOR_AXP=y
CONFIG_AXP717_POWER=y
CONFIG_AXP_DCDC2_VOLT=940
CONFIG_AXP_DCDC3_VOLT=1100

2
configs/orangepi_zero2_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-orangepi-zero2"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-orangepi-zero2"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x08080808
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e

2
configs/orangepi_zero2w_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero2w"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero2w"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e

2
configs/orangepi_zero3_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-orangepi-zero3"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-orangepi-zero3"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e

2
configs/tanix_tx1_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h313-tanix-tx1"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h313-tanix-tx1"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x06060606
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0d0d0d0d

2
configs/transpeed-8k618-t_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h618-transpeed-8k618-t"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-transpeed-8k618-t"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e

2
configs/x96_mate_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h616-x96-mate"
CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h616-x96-mate"
CONFIG_SPL=y
CONFIG_DRAM_SUN50I_H616_DX_ODT=0x03030303
CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e

8
drivers/clk/sunxi/clk_a80.c
View File

@ -75,10 +75,10 @@ static const struct ccu_clk_gate a80_mmc_gates[] = {
};
static const struct ccu_reset a80_mmc_resets[] = {
[0] = GATE(0x0, BIT(18)),
[1] = GATE(0x4, BIT(18)),
[2] = GATE(0x8, BIT(18)),
[3] = GATE(0xc, BIT(18)),
[0] = RESET(0x0, BIT(18)),
[1] = RESET(0x4, BIT(18)),
[2] = RESET(0x8, BIT(18)),
[3] = RESET(0xc, BIT(18)),
};
const struct ccu_desc a80_ccu_desc = {

2
drivers/power/axp809.c
View File

@ -93,7 +93,7 @@ int axp_set_dcdc4(unsigned int mvolt)
return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
AXP809_OUTPUT_CTRL1_DCDC4_EN);
ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
ret = pmic_bus_write(AXP809_DCDC4_CTRL, cfg);
if (ret)
return ret;

2
dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi
View File

@ -914,6 +914,8 @@
dmas = <&dma 48>, <&dma 48>;
dma-names = "rx", "tx";
resets = <&r_ccu RST_R_APB2_I2C>;
pinctrl-names = "default";
pinctrl-0 = <&r_i2c_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

6
dts/upstream/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts
View File

@ -201,12 +201,12 @@
vcc-pi-supply = <&reg_cldo3>;
};
&r_rsb {
&r_i2c {
status = "okay";
axp717: pmic@3a3 {
axp717: pmic@34 {
compatible = "x-powers,axp717";
reg = <0x3a3>;
reg = <0x34>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&nmi_intc>;

116
include/dt-bindings/clock/sun50i-h616-ccu.h
View File

@ -1,116 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2020 Arm Ltd.
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_
#define _DT_BINDINGS_CLK_SUN50I_H616_H_
#define CLK_PLL_PERIPH0 4
#define CLK_CPUX 21
#define CLK_APB1 26
#define CLK_DE 29
#define CLK_BUS_DE 30
#define CLK_DEINTERLACE 31
#define CLK_BUS_DEINTERLACE 32
#define CLK_G2D 33
#define CLK_BUS_G2D 34
#define CLK_GPU0 35
#define CLK_BUS_GPU 36
#define CLK_GPU1 37
#define CLK_CE 38
#define CLK_BUS_CE 39
#define CLK_VE 40
#define CLK_BUS_VE 41
#define CLK_BUS_DMA 42
#define CLK_BUS_HSTIMER 43
#define CLK_AVS 44
#define CLK_BUS_DBG 45
#define CLK_BUS_PSI 46
#define CLK_BUS_PWM 47
#define CLK_BUS_IOMMU 48
#define CLK_MBUS_DMA 50
#define CLK_MBUS_VE 51
#define CLK_MBUS_CE 52
#define CLK_MBUS_TS 53
#define CLK_MBUS_NAND 54
#define CLK_MBUS_G2D 55
#define CLK_NAND0 57
#define CLK_NAND1 58
#define CLK_BUS_NAND 59
#define CLK_MMC0 60
#define CLK_MMC1 61
#define CLK_MMC2 62
#define CLK_BUS_MMC0 63
#define CLK_BUS_MMC1 64
#define CLK_BUS_MMC2 65
#define CLK_BUS_UART0 66
#define CLK_BUS_UART1 67
#define CLK_BUS_UART2 68
#define CLK_BUS_UART3 69
#define CLK_BUS_UART4 70
#define CLK_BUS_UART5 71
#define CLK_BUS_I2C0 72
#define CLK_BUS_I2C1 73
#define CLK_BUS_I2C2 74
#define CLK_BUS_I2C3 75
#define CLK_BUS_I2C4 76
#define CLK_SPI0 77
#define CLK_SPI1 78
#define CLK_BUS_SPI0 79
#define CLK_BUS_SPI1 80
#define CLK_EMAC_25M 81
#define CLK_BUS_EMAC0 82
#define CLK_BUS_EMAC1 83
#define CLK_TS 84
#define CLK_BUS_TS 85
#define CLK_BUS_THS 86
#define CLK_SPDIF 87
#define CLK_BUS_SPDIF 88
#define CLK_DMIC 89
#define CLK_BUS_DMIC 90
#define CLK_AUDIO_CODEC_1X 91
#define CLK_AUDIO_CODEC_4X 92
#define CLK_BUS_AUDIO_CODEC 93
#define CLK_AUDIO_HUB 94
#define CLK_BUS_AUDIO_HUB 95
#define CLK_USB_OHCI0 96
#define CLK_USB_PHY0 97
#define CLK_USB_OHCI1 98
#define CLK_USB_PHY1 99
#define CLK_USB_OHCI2 100
#define CLK_USB_PHY2 101
#define CLK_USB_OHCI3 102
#define CLK_USB_PHY3 103
#define CLK_BUS_OHCI0 104
#define CLK_BUS_OHCI1 105
#define CLK_BUS_OHCI2 106
#define CLK_BUS_OHCI3 107
#define CLK_BUS_EHCI0 108
#define CLK_BUS_EHCI1 109
#define CLK_BUS_EHCI2 110
#define CLK_BUS_EHCI3 111
#define CLK_BUS_OTG 112
#define CLK_BUS_KEYADC 113
#define CLK_HDMI 114
#define CLK_HDMI_SLOW 115
#define CLK_HDMI_CEC 116
#define CLK_BUS_HDMI 117
#define CLK_BUS_TCON_TOP 118
#define CLK_TCON_TV0 119
#define CLK_TCON_TV1 120
#define CLK_BUS_TCON_TV0 121
#define CLK_BUS_TCON_TV1 122
#define CLK_TVE0 123
#define CLK_BUS_TVE_TOP 124
#define CLK_BUS_TVE0 125
#define CLK_HDCP 126
#define CLK_BUS_HDCP 127
#define CLK_PLL_SYSTEM_32K 128
#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */

70
include/dt-bindings/reset/sun50i-h616-ccu.h
View File

@ -1,70 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (C) 2020 Arm Ltd.
*/
#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_
#define _DT_BINDINGS_RESET_SUN50I_H616_H_
#define RST_MBUS 0
#define RST_BUS_DE 1
#define RST_BUS_DEINTERLACE 2
#define RST_BUS_GPU 3
#define RST_BUS_CE 4
#define RST_BUS_VE 5
#define RST_BUS_DMA 6
#define RST_BUS_HSTIMER 7
#define RST_BUS_DBG 8
#define RST_BUS_PSI 9
#define RST_BUS_PWM 10
#define RST_BUS_IOMMU 11
#define RST_BUS_DRAM 12
#define RST_BUS_NAND 13
#define RST_BUS_MMC0 14
#define RST_BUS_MMC1 15
#define RST_BUS_MMC2 16
#define RST_BUS_UART0 17
#define RST_BUS_UART1 18
#define RST_BUS_UART2 19
#define RST_BUS_UART3 20
#define RST_BUS_UART4 21
#define RST_BUS_UART5 22
#define RST_BUS_I2C0 23
#define RST_BUS_I2C1 24
#define RST_BUS_I2C2 25
#define RST_BUS_I2C3 26
#define RST_BUS_I2C4 27
#define RST_BUS_SPI0 28
#define RST_BUS_SPI1 29
#define RST_BUS_EMAC0 30
#define RST_BUS_EMAC1 31
#define RST_BUS_TS 32
#define RST_BUS_THS 33
#define RST_BUS_SPDIF 34
#define RST_BUS_DMIC 35
#define RST_BUS_AUDIO_CODEC 36
#define RST_BUS_AUDIO_HUB 37
#define RST_USB_PHY0 38
#define RST_USB_PHY1 39
#define RST_USB_PHY2 40
#define RST_USB_PHY3 41
#define RST_BUS_OHCI0 42
#define RST_BUS_OHCI1 43
#define RST_BUS_OHCI2 44
#define RST_BUS_OHCI3 45
#define RST_BUS_EHCI0 46
#define RST_BUS_EHCI1 47
#define RST_BUS_EHCI2 48
#define RST_BUS_EHCI3 49
#define RST_BUS_OTG 50
#define RST_BUS_HDMI 51
#define RST_BUS_HDMI_SUB 52
#define RST_BUS_TCON_TOP 53
#define RST_BUS_TCON_TV0 54
#define RST_BUS_TCON_TV1 55
#define RST_BUS_TVE_TOP 56
#define RST_BUS_TVE0 57
#define RST_BUS_HDCP 58
#define RST_BUS_KEYADC 59
#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */