gpio: Move OMAP_GPIO to Kconfig

This driver is used often enough such that we want to have this enabled
by default on any ARCH_OMAP2PLUS board, and this only compiles on
ARCH_OMAP2PLUS due to required defines, so mark that as the depends.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2017-05-12 22:33:21 -04:00
parent bdf10677a9
commit 29cb2b3b90
18 changed files with 8 additions and 35 deletions

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@ -95,6 +95,14 @@ config MSM_GPIO
- APQ8016
- MSM8916
config OMAP_GPIO
bool "TI OMAP GPIO driver"
depends on ARCH_OMAP2PLUS
default y
help
Support GPIO controllers on the TI OMAP3/4/5 and related (such as
AM335x/AM43xx/AM57xx/DRA7xx/etc) families of SoCs.
config PM8916_GPIO
bool "Qualcomm PM8916 PMIC GPIO/keypad driver"
depends on DM_GPIO && PMIC_PM8916

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@ -45,9 +45,6 @@
/* Hardware drivers */
/* OMAP GPIO configuration */
#define CONFIG_OMAP_GPIO
/* NS16550 Configuration */
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550_SERIAL

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@ -75,8 +75,6 @@
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
/* GPIO */
#define CONFIG_OMAP_GPIO
/*
* Our platforms make use of SPL to initalize the hardware (primarily

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@ -22,7 +22,6 @@
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#define CONFIG_SDRC /* The chip has SDRC controller */

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@ -79,8 +79,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_OMAP_GPIO
/* USB */
#define CONFIG_USB_MUSB_AM35X

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@ -53,12 +53,6 @@
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE)
/*
* GPIO
*/
#define CONFIG_OMAP_GPIO
/*
* I2C
*/

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@ -12,7 +12,6 @@
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP_GPIO
#define CONFIG_MACH_TYPE MACH_TYPE_MCX

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@ -125,7 +125,6 @@
#define CONFIG_TWL4030_LED
#define CONFIG_TWL4030_KEYPAD
#define CONFIG_OMAP_GPIO
#define GPIO_SLIDE 71
/*

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@ -83,7 +83,6 @@
/*
* High level configuration options
*/
#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* The chip has SDRC controller */

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@ -547,10 +547,6 @@
#endif
#endif
#define CONFIG_OMAP_GPIO
/* Gpio cmd support */
/* Watchdog */
#define CONFIG_HW_WATCHDOG

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@ -58,8 +58,6 @@
/*
* GPIO
*/
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_3
#define CONFIG_OMAP3_GPIO_4

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@ -13,7 +13,6 @@
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP_GPIO
#define CONFIG_SYS_TEXT_BASE 0x80008000

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@ -16,7 +16,6 @@
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP_GPIO
#define CONFIG_SDRC /* Has an SDRC controller */

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@ -109,8 +109,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */
#define CONFIG_OMAP_GPIO
/**
* Physical Memory Map
*/

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@ -49,7 +49,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_CMD_ASKENV
#define CONFIG_OMAP_GPIO
#define CONFIG_FS_FAT

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@ -20,9 +20,6 @@
/* SPI IP Block */
#define CONFIG_OMAP3_SPI
/* GPIO block */
#define CONFIG_OMAP_GPIO
/*
* GPMC NAND block. We support 1 device and the physical address to
* access CS0 at is 0x8000000.

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@ -46,9 +46,6 @@
/* Hardware drivers */
/* GPIO support */
#define CONFIG_OMAP_GPIO
/* GPIO banks */
#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */

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@ -1990,7 +1990,6 @@ CONFIG_OMAP3_SPI_D0_D1_SWAPPED
CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
CONFIG_OMAP_GPIO
CONFIG_OMAP_USB2PHY2_HOST
CONFIG_OMAP_USB3PHY1_HOST
CONFIG_OMAP_USB_PHY