mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-04 18:13:31 +08:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
Wolfgang Denk
commit
29840de6b6
@ -81,10 +81,16 @@ struct liodn_id_table fman2_liodn_tbl[] = {
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#endif
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
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SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
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SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
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SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
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/*
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* We assume currently that all JR are in the same partition
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* and as such they need to represent the same LIODN due to
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* a 4080 rev.2 h/w requirement that DECOs sharing from themselves
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* or from another DECO have the two Non-SEQ LIODN values equal
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*/
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SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */
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SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */
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SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */
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SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */
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SET_SEC_RTIC_LIODN_ENTRY(a, 144),
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SET_SEC_RTIC_LIODN_ENTRY(b, 145),
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SET_SEC_RTIC_LIODN_ENTRY(c, 176),
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@ -1589,7 +1589,9 @@ typedef struct cpc_corenet {
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u32 cpcerreaddr; /* error extended address */
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u32 cpcerraddr; /* error address */
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u32 cpcerrctl; /* error control */
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u32 res9[105]; /* pad out to 4k */
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u32 res9[41]; /* pad out to 4k */
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u32 cpchdbcr0; /* hardware debug control register 0 */
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u32 res10[63]; /* pad out to 4k */
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} cpc_corenet_t;
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#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
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@ -1616,6 +1618,7 @@ typedef struct cpc_corenet {
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#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
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#define CPC_SRCR0_SRAMEN 0x00000001
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#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
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#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
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#endif /* CONFIG_SYS_FSL_CPC */
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/* Global Utilities Block */
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@ -28,13 +28,21 @@
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#include <i2c.h>
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#include <linux/ctype.h>
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#ifdef CONFIG_SYS_I2C_EEPROM_CCID
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#include "../common/eeprom.h"
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#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID)
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#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID"
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#define MAX_NUM_PORTS 8
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#endif
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#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
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#ifdef CONFIG_SYS_I2C_EEPROM_NXID
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#define MAX_NUM_PORTS 8
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#define NXID_VERSION 0
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#endif
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#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define MAX_NUM_PORTS 23
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#define NXID_VERSION 1
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#endif
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/**
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* static eeprom: EEPROM layout for CCID or NXID formats
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@ -68,8 +76,8 @@ static struct __attribute__ ((__packed__)) eeprom {
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u8 res_1[21]; /* 0x2b - 0x3f Reserved */
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u8 mac_count; /* 0x40 Number of MAC addresses */
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u8 mac_flag; /* 0x41 MAC table flags */
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u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
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u32 crc; /* 0x72 CRC32 checksum */
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u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
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u32 crc; /* x+1 CRC32 checksum */
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#endif
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} e;
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@ -204,7 +212,7 @@ static void update_crc(void)
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*/
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static int prog_eeprom(void)
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{
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int ret = 0; /* shut up gcc */
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int ret = 0;
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int i;
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void *p;
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#ifdef CONFIG_SYS_EEPROM_BUS_NUM
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@ -225,6 +233,11 @@ static int prog_eeprom(void)
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i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
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#endif
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/*
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* The AT24C02 datasheet says that data can only be written in page
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* mode, which means 8 bytes at a time, and it takes up to 5ms to
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* complete a given write.
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*/
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for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
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ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
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p, min((sizeof(e) - i), 8));
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@ -233,12 +246,23 @@ static int prog_eeprom(void)
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udelay(5000); /* 5ms write cycle timing */
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}
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if (!ret) {
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/* Verify the write by reading back the EEPROM and comparing */
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struct eeprom e2;
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ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
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if (!ret && memcmp(&e, &e2, sizeof(e)))
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ret = -1;
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}
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#ifdef CONFIG_SYS_EEPROM_BUS_NUM
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i2c_set_bus_num(bus);
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#endif
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if (ret) {
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printf("Programming failed.\n");
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has_been_read = 0;
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return -1;
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}
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@ -300,7 +324,7 @@ static void set_mac_address(unsigned int index, const char *string)
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char *p = (char *) string;
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unsigned int i;
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if (!string) {
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if ((index >= MAX_NUM_PORTS) || !string) {
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printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
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return;
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}
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@ -333,7 +357,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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if (cmd == 'i') {
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#ifdef CONFIG_SYS_I2C_EEPROM_NXID
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memcpy(e.id, "NXID", sizeof(e.id));
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e.version = 0;
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e.version = NXID_VERSION;
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#else
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memcpy(e.id, "CCID", sizeof(e.id));
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#endif
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@ -382,8 +406,8 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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e.mac_count = simple_strtoul(argv[2], NULL, 16);
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update_crc();
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break;
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case '0' ... '7': /* "mac 0" through "mac 7" */
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set_mac_address(cmd - '0', argv[2]);
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case '0' ... '9': /* "mac 0" through "mac 22" */
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set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
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break;
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case 'h': /* help */
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default:
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@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose;
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_PCIE4
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static struct pci_controller pcie4_hose;
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#endif
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[3];
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struct fsl_pci_info pci_info[4];
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u32 devdisr;
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int first_free_busno = 0;
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int num = 0;
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@ -119,6 +123,28 @@ void pci_init_board(void)
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
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#endif
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#ifdef CONFIG_PCIE4
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pcie_configured = is_serdes_configured(PCIE4);
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if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
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set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
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LAW_TRGT_IF_PCIE_4);
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set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_4);
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SET_STD_PCIE_INFO(pci_info[num], 4);
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pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
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printf(" PCIE4 connected to as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie4_hose, first_free_busno);
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} else {
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printf (" PCIE4: disabled\n");
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}
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#else
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setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
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#endif
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}
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void pci_of_setup(void *blob, bd_t *bd)
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@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts,
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popts->write_data_delay = 2;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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* Enable half drive strength
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*/
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popts->half_strength_driver_enable = 0;
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popts->half_strength_driver_enable = 1;
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/* Write leveling override */
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popts->wrlvl_en = 1;
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xa;
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popts->wrlvl_start = 0x4;
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/* Rtt and Rtt_W override */
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popts->rtt_override = 1;
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popts->rtt_override_value = DDR3_RTT_60_OHM;
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popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
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}
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@ -27,6 +27,7 @@
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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@ -211,6 +212,31 @@ int board_early_init_f (void)
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
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const u8 flash_esel = 0;
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/*
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* Remap Boot flash to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, /* ts, esel */
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BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
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return 0;
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}
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int checkboard (void)
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{
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printf ("Board: 8569 MDS\n");
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@ -1,5 +1,5 @@
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 1 Initializations */
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/*
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* TLBe 0: 64M Non-cacheable, guarded
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* TLBe 0: 64M write-through, guarded
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* Out of reset this entry is only 4K.
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* 0xfc000000 256K NAND FLASH (CS3)
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* 0xfe000000 32M NOR FLASH (CS0)
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* 0xfc000000 32MB NAND FLASH (CS3)
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* 0xfe000000 32MB NOR FLASH (CS0)
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*/
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#ifdef CONFIG_NAND_SPL
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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||||
#else
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||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
#endif
|
||||
/*
|
||||
* TLBe 1: 256KB Non-cacheable, guarded
|
||||
* 0xf8000000 32K BCSR
|
||||
|
||||
@ -27,6 +27,7 @@
|
||||
#include <asm/mp.h>
|
||||
#include <netdev.h>
|
||||
#include <i2c.h>
|
||||
#include <hwconfig.h>
|
||||
|
||||
#include "../common/ngpixis.h"
|
||||
|
||||
@ -90,34 +91,58 @@ phys_size_t initdram(int board_type)
|
||||
|
||||
#define CONFIG_TFP410_I2C_ADDR 0x38
|
||||
|
||||
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
|
||||
#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
|
||||
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
|
||||
|
||||
/* Route the I2C1 pins to the SSI port instead. */
|
||||
#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
|
||||
|
||||
/* Choose the 12.288Mhz codec reference clock */
|
||||
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
|
||||
|
||||
/* Choose the 11.2896Mhz codec reference clock */
|
||||
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u8 temp;
|
||||
const char *audclk;
|
||||
size_t arglen;
|
||||
|
||||
/* Enable the TFP410 Encoder */
|
||||
/* For DVI, enable the TFP410 Encoder. */
|
||||
|
||||
temp = 0xBF;
|
||||
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
/* Verify if enabled */
|
||||
temp = 0;
|
||||
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
debug("DVI Encoder Read: 0x%02x\n", temp);
|
||||
|
||||
temp = 0x10;
|
||||
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
/* Verify if enabled */
|
||||
temp = 0;
|
||||
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
|
||||
return -1;
|
||||
|
||||
debug("DVI Encoder Read: 0x%02x\n",temp);
|
||||
|
||||
/*
|
||||
* Enable the reference clock for the WM8776 codec, and route the MUX
|
||||
* pins for SSI. The default is the 12.288 MHz clock
|
||||
*/
|
||||
|
||||
temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
|
||||
CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
|
||||
temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
|
||||
|
||||
audclk = hwconfig_arg("audclk", &arglen);
|
||||
/* Check the first two chars only */
|
||||
if (audclk && (strncmp(audclk, "11", 2) == 0))
|
||||
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
|
||||
else
|
||||
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
|
||||
out_8(&pixis->brdcfg1, temp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
/**
|
||||
* ft_codec_setup - fix up the clock-frequency property of the codec node
|
||||
*
|
||||
* Update the clock-frequency property based on the value of the 'audclk'
|
||||
* hwconfig option. If audclk is not specified, then default to 12.288MHz.
|
||||
*/
|
||||
static void ft_codec_setup(void *blob, const char *compatible)
|
||||
{
|
||||
const char *audclk;
|
||||
size_t arglen;
|
||||
u32 freq;
|
||||
|
||||
audclk = hwconfig_arg("audclk", &arglen);
|
||||
if (audclk && (strncmp(audclk, "11", 2) == 0))
|
||||
freq = 11289600;
|
||||
else
|
||||
freq = 12288000;
|
||||
|
||||
do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
|
||||
}
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
@ -327,6 +373,9 @@ void ft_board_setup(void *blob, bd_t *bd)
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
fsl_sgmii_riser_fdt_fixup(blob);
|
||||
#endif
|
||||
|
||||
/* Update the WM8776 node's clock frequency property */
|
||||
ft_codec_setup(blob, "wlf,wm8776");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
21
doc/README.fsl-hwconfig
Normal file
21
doc/README.fsl-hwconfig
Normal file
@ -0,0 +1,21 @@
|
||||
Freescale-specific 'hwconfig' options.
|
||||
|
||||
This file documents Freescale-specific key:value pairs for the 'hwconfig'
|
||||
option. See README.hwconfig for general information about 'hwconfig'.
|
||||
|
||||
audclk
|
||||
Specific to the P1022DS reference board.
|
||||
|
||||
This option specifies which of the two oscillator frequencies should be
|
||||
routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to
|
||||
route either a 11.2896MHz or a 12.288MHz clock. The default is
|
||||
12.288MHz. This option has two effects. First, the MUX on the board
|
||||
will be programmed accordingly. Second, the clock-frequency property
|
||||
in the codec node in the device tree will be updated to the correct
|
||||
value.
|
||||
|
||||
'audclk:11'
|
||||
Select the 11.2896MHz clock
|
||||
|
||||
'audclk:12'
|
||||
Select the 12.288MHz clock
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
@ -74,6 +74,7 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R 1
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
@ -505,8 +506,8 @@ extern unsigned long get_clock_freq(void);
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
|
||||
@ -134,6 +134,7 @@
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
#define CONFIG_FSL_NGPIXIS
|
||||
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
|
||||
|
||||
@ -399,6 +399,14 @@
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 4, Base address 203000 */
|
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
|
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
|
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* Qman/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
@ -607,14 +615,17 @@
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
||||
"bank_intlv=cs0_cs1\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"ubootaddr=" MK_STR(TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=p4080ds/ramdisk.uboot\0" \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user