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arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR register

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Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz.
Use this information instead of manual configuration in every board file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár 2021-07-31 14:22:52 +02:00 committed by Stefan Roese
parent 293a8de6fa
commit 29795302b9
8 changed files with 8 additions and 16 deletions
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13
arch/arm/mach-mvebu/include/mach/soc.h
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@ -33,11 +33,6 @@
#define MV_88F68XX_A0_ID 0x4
#define MV_88F68XX_B0_ID 0xa
/* TCLK Core Clock definition */
#ifndef CONFIG_SYS_TCLK
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
@ -170,6 +165,9 @@
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
200000000 : 250000000)
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
@ -207,4 +205,9 @@
#define BOOT_FROM_SPI 0x3
#endif
/* TCLK Core Clock definition */
#ifndef CONFIG_SYS_TCLK
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
#endif /* _MVEBU_SOC_H */

1
include/configs/clearfog.h
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@ -17,7 +17,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

2
include/configs/controlcenterdc.h
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@ -20,8 +20,6 @@
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#define CONFIG_LOADADDR 1000000
/*

2
include/configs/db-88f6820-amc.h
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@ -10,8 +10,6 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

2
include/configs/db-88f6820-gp.h
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@ -10,8 +10,6 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_I2C_MVTWSI

1
include/configs/helios4.h
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@ -17,7 +17,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

1
include/configs/turris_omnia.h
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@ -16,7 +16,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

2
include/configs/x530.h
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@ -12,8 +12,6 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
* NS16550 Configuration
*/