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Add support for SMSC95XX USB 2.0 10/100MBit Ethernet Adapter
The SMSC95XX is a USB hub with a built-in Ethernet adapter. This adds support for this, using the USB host network framework. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Eric Bénard <eric@eukrea.com>
This commit is contained in:
Simon Glass
Remy Bohmer
parent
fa82f871c8
commit
291391bed5
@ -28,6 +28,7 @@ COBJS-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
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ifdef CONFIG_USB_ETHER_ASIX
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COBJS-y += asix.o
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endif
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COBJS-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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879
drivers/usb/eth/smsc95xx.c
Normal file
879
drivers/usb/eth/smsc95xx.c
Normal file
@ -0,0 +1,879 @@
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* Copyright (C) 2009 NVIDIA, Corporation
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <usb.h>
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#include <linux/mii.h>
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#include "usb_ether.h"
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/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
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/* Tx command words */
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#define TX_CMD_A_FIRST_SEG_ 0x00002000
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#define TX_CMD_A_LAST_SEG_ 0x00001000
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/* Rx status word */
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#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
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#define RX_STS_ES_ 0x00008000 /* Error Summary */
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/* SCSRs */
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#define ID_REV 0x00
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#define INT_STS 0x08
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#define TX_CFG 0x10
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#define TX_CFG_ON_ 0x00000004
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#define HW_CFG 0x14
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#define HW_CFG_BIR_ 0x00001000
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#define HW_CFG_RXDOFF_ 0x00000600
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#define HW_CFG_MEF_ 0x00000020
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#define HW_CFG_BCE_ 0x00000002
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#define HW_CFG_LRST_ 0x00000008
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#define PM_CTRL 0x20
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#define PM_CTL_PHY_RST_ 0x00000010
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#define AFC_CFG 0x2C
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/*
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* Hi watermark = 15.5Kb (~10 mtu pkts)
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* low watermark = 3k (~2 mtu pkts)
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* backpressure duration = ~ 350us
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* Apply FC on any frame.
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*/
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#define AFC_CFG_DEFAULT 0x00F830A1
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#define E2P_CMD 0x30
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#define E2P_CMD_BUSY_ 0x80000000
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#define E2P_CMD_READ_ 0x00000000
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#define E2P_CMD_TIMEOUT_ 0x00000400
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#define E2P_CMD_LOADED_ 0x00000200
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#define E2P_CMD_ADDR_ 0x000001FF
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#define E2P_DATA 0x34
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#define BURST_CAP 0x38
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#define INT_EP_CTL 0x68
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#define INT_EP_CTL_PHY_INT_ 0x00008000
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#define BULK_IN_DLY 0x6C
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/* MAC CSRs */
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#define MAC_CR 0x100
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#define MAC_CR_MCPAS_ 0x00080000
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#define MAC_CR_PRMS_ 0x00040000
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#define MAC_CR_HPFILT_ 0x00002000
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#define MAC_CR_TXEN_ 0x00000008
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#define MAC_CR_RXEN_ 0x00000004
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#define ADDRH 0x104
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#define ADDRL 0x108
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#define MII_ADDR 0x114
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#define MII_WRITE_ 0x02
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#define MII_BUSY_ 0x01
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#define MII_READ_ 0x00 /* ~of MII Write bit */
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#define MII_DATA 0x118
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#define FLOW 0x11C
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#define VLAN1 0x120
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#define COE_CR 0x130
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#define Tx_COE_EN_ 0x00010000
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#define Rx_COE_EN_ 0x00000001
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/* Vendor-specific PHY Definitions */
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#define PHY_INT_SRC 29
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#define PHY_INT_MASK 30
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#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
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#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
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#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
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PHY_INT_MASK_LINK_DOWN_)
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/* USB Vendor Requests */
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#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
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#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
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/* Some extra defines */
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#define HS_USB_PKT_SIZE 512
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#define FS_USB_PKT_SIZE 64
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#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
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#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
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#define DEFAULT_BULK_IN_DELAY 0x00002000
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#define MAX_SINGLE_PACKET_SIZE 2048
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#define EEPROM_MAC_OFFSET 0x01
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#define SMSC95XX_INTERNAL_PHY_ID 1
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#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
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/* local defines */
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#define SMSC95XX_BASE_NAME "sms"
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#define USB_CTRL_SET_TIMEOUT 5000
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#define USB_CTRL_GET_TIMEOUT 5000
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#define USB_BULK_SEND_TIMEOUT 5000
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#define USB_BULK_RECV_TIMEOUT 5000
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#define AX_RX_URB_SIZE 2048
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#define PHY_CONNECT_TIMEOUT 5000
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#define TURBO_MODE
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/* local vars */
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static int curr_eth_dev; /* index for name of next device detected */
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/*
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* Smsc95xx infrastructure commands
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*/
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static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)
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{
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int len;
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cpu_to_le32s(&data);
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len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0),
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USB_VENDOR_REQUEST_WRITE_REGISTER,
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USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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00, index, &data, sizeof(data), USB_CTRL_SET_TIMEOUT);
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if (len != sizeof(data)) {
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debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
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index, data, len);
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return -1;
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}
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return 0;
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}
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static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data)
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{
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int len;
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len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0),
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USB_VENDOR_REQUEST_READ_REGISTER,
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USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
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00, index, data, sizeof(data), USB_CTRL_GET_TIMEOUT);
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if (len != sizeof(data)) {
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debug("smsc95xx_read_reg failed: index=%d, len=%d",
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index, len);
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return -1;
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}
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le32_to_cpus(data);
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return 0;
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}
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/* Loop until the read is completed with timeout */
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static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev)
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{
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unsigned long start_time = get_timer(0);
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u32 val;
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do {
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smsc95xx_read_reg(dev, MII_ADDR, &val);
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if (!(val & MII_BUSY_))
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return 0;
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} while (get_timer(start_time) < 1 * 1000 * 1000);
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return -1;
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}
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static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx)
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{
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u32 val, addr;
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/* confirm MII not busy */
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if (smsc95xx_phy_wait_not_busy(dev)) {
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debug("MII is busy in smsc95xx_mdio_read\n");
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return -1;
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}
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/* set the address, index & direction (read from PHY) */
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addr = (phy_id << 11) | (idx << 6) | MII_READ_;
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smsc95xx_write_reg(dev, MII_ADDR, addr);
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if (smsc95xx_phy_wait_not_busy(dev)) {
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debug("Timed out reading MII reg %02X\n", idx);
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return -1;
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}
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smsc95xx_read_reg(dev, MII_DATA, &val);
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return (u16)(val & 0xFFFF);
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}
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static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx,
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int regval)
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{
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u32 val, addr;
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/* confirm MII not busy */
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if (smsc95xx_phy_wait_not_busy(dev)) {
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debug("MII is busy in smsc95xx_mdio_write\n");
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return;
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}
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val = regval;
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smsc95xx_write_reg(dev, MII_DATA, val);
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/* set the address, index & direction (write to PHY) */
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addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
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smsc95xx_write_reg(dev, MII_ADDR, addr);
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if (smsc95xx_phy_wait_not_busy(dev))
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debug("Timed out writing MII reg %02X\n", idx);
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}
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static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev)
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{
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unsigned long start_time = get_timer(0);
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u32 val;
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do {
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smsc95xx_read_reg(dev, E2P_CMD, &val);
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if (!(val & E2P_CMD_LOADED_)) {
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debug("No EEPROM present\n");
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return -1;
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}
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if (!(val & E2P_CMD_BUSY_))
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return 0;
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udelay(40);
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} while (get_timer(start_time) < 1 * 1000 * 1000);
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debug("EEPROM is busy\n");
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return -1;
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}
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static int smsc95xx_wait_eeprom(struct ueth_data *dev)
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{
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unsigned long start_time = get_timer(0);
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u32 val;
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do {
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smsc95xx_read_reg(dev, E2P_CMD, &val);
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if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
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break;
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udelay(40);
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} while (get_timer(start_time) < 1 * 1000 * 1000);
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if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
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debug("EEPROM read operation timeout\n");
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return -1;
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}
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return 0;
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}
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static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length,
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u8 *data)
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{
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u32 val;
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int i, ret;
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ret = smsc95xx_eeprom_confirm_not_busy(dev);
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if (ret)
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return ret;
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for (i = 0; i < length; i++) {
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val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
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smsc95xx_write_reg(dev, E2P_CMD, val);
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ret = smsc95xx_wait_eeprom(dev);
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if (ret < 0)
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return ret;
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smsc95xx_read_reg(dev, E2P_DATA, &val);
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data[i] = val & 0xFF;
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offset++;
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}
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return 0;
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}
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/*
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* mii_nway_restart - restart NWay (autonegotiation) for this interface
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*
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* Returns 0 on success, negative on error.
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*/
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static int mii_nway_restart(struct ueth_data *dev)
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{
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int bmcr;
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int r = -1;
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/* if autoneg is off, it's an error */
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bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR);
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if (bmcr & BMCR_ANENABLE) {
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bmcr |= BMCR_ANRESTART;
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smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
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r = 0;
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}
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return r;
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}
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static int smsc95xx_phy_initialize(struct ueth_data *dev)
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{
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smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
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smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
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ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
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ADVERTISE_PAUSE_ASYM);
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/* read to clear */
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smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC);
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smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK,
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PHY_INT_MASK_DEFAULT_);
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mii_nway_restart(dev);
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debug("phy initialised succesfully\n");
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return 0;
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}
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static int smsc95xx_init_mac_address(struct eth_device *eth,
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struct ueth_data *dev)
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{
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/* try reading mac address from EEPROM */
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if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
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eth->enetaddr) == 0) {
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if (is_valid_ether_addr(eth->enetaddr)) {
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/* eeprom values are valid so use them */
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debug("MAC address read from EEPROM\n");
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return 0;
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}
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}
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/*
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* No eeprom, or eeprom values are invalid. Generating a random MAC
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* address is not safe. Just return an error.
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*/
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return -1;
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}
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static int smsc95xx_write_hwaddr(struct eth_device *eth)
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{
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struct ueth_data *dev = (struct ueth_data *)eth->priv;
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u32 addr_lo, addr_hi;
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int ret;
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/* set hardware address */
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debug("** %s()\n", __func__);
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addr_lo = cpu_to_le32(*((u32 *)eth->enetaddr));
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addr_hi = cpu_to_le16(*((u16 *)(eth->enetaddr + 4)));
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ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
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if (ret < 0) {
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debug("Failed to write ADDRL: %d\n", ret);
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return ret;
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}
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ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
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if (ret < 0)
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return ret;
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debug("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
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eth->enetaddr[0], eth->enetaddr[1],
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eth->enetaddr[2], eth->enetaddr[3],
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eth->enetaddr[4], eth->enetaddr[5]);
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dev->have_hwaddr = 1;
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return 0;
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}
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/* Enable or disable Tx & Rx checksum offload engines */
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static int smsc95xx_set_csums(struct ueth_data *dev,
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int use_tx_csum, int use_rx_csum)
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{
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u32 read_buf;
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int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
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if (ret < 0)
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return ret;
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if (use_tx_csum)
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read_buf |= Tx_COE_EN_;
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else
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read_buf &= ~Tx_COE_EN_;
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if (use_rx_csum)
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read_buf |= Rx_COE_EN_;
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else
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read_buf &= ~Rx_COE_EN_;
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ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
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if (ret < 0)
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return ret;
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debug("COE_CR = 0x%08x\n", read_buf);
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return 0;
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}
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static void smsc95xx_set_multicast(struct ueth_data *dev)
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{
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/* No multicast in u-boot */
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dev->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
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}
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/* starts the TX path */
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static void smsc95xx_start_tx_path(struct ueth_data *dev)
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{
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u32 reg_val;
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/* Enable Tx at MAC */
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dev->mac_cr |= MAC_CR_TXEN_;
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smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
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/* Enable Tx at SCSRs */
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reg_val = TX_CFG_ON_;
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smsc95xx_write_reg(dev, TX_CFG, reg_val);
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}
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/* Starts the Receive path */
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static void smsc95xx_start_rx_path(struct ueth_data *dev)
|
||||
{
|
||||
dev->mac_cr |= MAC_CR_RXEN_;
|
||||
smsc95xx_write_reg(dev, MAC_CR, dev->mac_cr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Smsc95xx callbacks
|
||||
*/
|
||||
static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
|
||||
{
|
||||
int ret;
|
||||
u32 write_buf;
|
||||
u32 read_buf;
|
||||
u32 burst_cap;
|
||||
int timeout;
|
||||
struct ueth_data *dev = (struct ueth_data *)eth->priv;
|
||||
#define TIMEOUT_RESOLUTION 50 /* ms */
|
||||
int link_detected;
|
||||
|
||||
debug("** %s()\n", __func__);
|
||||
dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
|
||||
|
||||
write_buf = HW_CFG_LRST_;
|
||||
ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
timeout = 0;
|
||||
do {
|
||||
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
udelay(10 * 1000);
|
||||
timeout++;
|
||||
} while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
|
||||
|
||||
if (timeout >= 100) {
|
||||
debug("timeout waiting for completion of Lite Reset\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
write_buf = PM_CTL_PHY_RST_;
|
||||
ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
timeout = 0;
|
||||
do {
|
||||
ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
udelay(10 * 1000);
|
||||
timeout++;
|
||||
} while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
|
||||
if (timeout >= 100) {
|
||||
debug("timeout waiting for PHY Reset\n");
|
||||
return -1;
|
||||
}
|
||||
if (!dev->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
|
||||
dev->have_hwaddr = 1;
|
||||
if (!dev->have_hwaddr) {
|
||||
puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
|
||||
return -1;
|
||||
}
|
||||
if (smsc95xx_write_hwaddr(eth) < 0)
|
||||
return -1;
|
||||
|
||||
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
|
||||
|
||||
read_buf |= HW_CFG_BIR_;
|
||||
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
debug("Read Value from HW_CFG after writing "
|
||||
"HW_CFG_BIR_: 0x%08x\n", read_buf);
|
||||
|
||||
#ifdef TURBO_MODE
|
||||
if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
|
||||
burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
|
||||
dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
|
||||
} else {
|
||||
burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
|
||||
dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
|
||||
}
|
||||
#else
|
||||
burst_cap = 0;
|
||||
dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
|
||||
#endif
|
||||
debug("rx_urb_size=%ld\n", (ulong)dev->rx_urb_size);
|
||||
|
||||
ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
|
||||
|
||||
read_buf = DEFAULT_BULK_IN_DELAY;
|
||||
ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
debug("Read Value from BULK_IN_DLY after writing: "
|
||||
"0x%08x\n", read_buf);
|
||||
|
||||
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
|
||||
|
||||
#ifdef TURBO_MODE
|
||||
read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
|
||||
#endif
|
||||
read_buf &= ~HW_CFG_RXDOFF_;
|
||||
|
||||
#define NET_IP_ALIGN 0
|
||||
read_buf |= NET_IP_ALIGN << 9;
|
||||
|
||||
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
|
||||
|
||||
write_buf = 0xFFFFFFFF;
|
||||
ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
debug("ID_REV = 0x%08x\n", read_buf);
|
||||
|
||||
/* Init Tx */
|
||||
write_buf = 0;
|
||||
ret = smsc95xx_write_reg(dev, FLOW, write_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
read_buf = AFC_CFG_DEFAULT;
|
||||
ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = smsc95xx_read_reg(dev, MAC_CR, &dev->mac_cr);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Init Rx. Set Vlan */
|
||||
write_buf = (u32)ETH_P_8021Q;
|
||||
ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Disable checksum offload engines */
|
||||
ret = smsc95xx_set_csums(dev, 0, 0);
|
||||
if (ret < 0) {
|
||||
debug("Failed to set csum offload: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
smsc95xx_set_multicast(dev);
|
||||
|
||||
if (smsc95xx_phy_initialize(dev) < 0)
|
||||
return -1;
|
||||
ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* enable PHY interrupts */
|
||||
read_buf |= INT_EP_CTL_PHY_INT_;
|
||||
|
||||
ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
smsc95xx_start_tx_path(dev);
|
||||
smsc95xx_start_rx_path(dev);
|
||||
|
||||
timeout = 0;
|
||||
do {
|
||||
link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR)
|
||||
& BMSR_LSTATUS;
|
||||
if (!link_detected) {
|
||||
if (timeout == 0)
|
||||
printf("Waiting for Ethernet connection... ");
|
||||
udelay(TIMEOUT_RESOLUTION * 1000);
|
||||
timeout += TIMEOUT_RESOLUTION;
|
||||
}
|
||||
} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
|
||||
if (link_detected) {
|
||||
if (timeout != 0)
|
||||
printf("done.\n");
|
||||
} else {
|
||||
printf("unable to connect.\n");
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int smsc95xx_send(struct eth_device *eth, volatile void* packet,
|
||||
int length)
|
||||
{
|
||||
struct ueth_data *dev = (struct ueth_data *)eth->priv;
|
||||
int err;
|
||||
int actual_len;
|
||||
u32 tx_cmd_a;
|
||||
u32 tx_cmd_b;
|
||||
unsigned char msg[PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)];
|
||||
|
||||
debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
|
||||
if (length > PKTSIZE)
|
||||
return -1;
|
||||
|
||||
tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
|
||||
tx_cmd_b = (u32)length;
|
||||
cpu_to_le32s(&tx_cmd_a);
|
||||
cpu_to_le32s(&tx_cmd_b);
|
||||
|
||||
/* prepend cmd_a and cmd_b */
|
||||
memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
|
||||
memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
|
||||
memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
|
||||
length);
|
||||
err = usb_bulk_msg(dev->pusb_dev,
|
||||
usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
|
||||
(void *)msg,
|
||||
length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
|
||||
&actual_len,
|
||||
USB_BULK_SEND_TIMEOUT);
|
||||
debug("Tx: len = %u, actual = %u, err = %d\n",
|
||||
length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
|
||||
actual_len, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int smsc95xx_recv(struct eth_device *eth)
|
||||
{
|
||||
struct ueth_data *dev = (struct ueth_data *)eth->priv;
|
||||
static unsigned char recv_buf[AX_RX_URB_SIZE];
|
||||
unsigned char *buf_ptr;
|
||||
int err;
|
||||
int actual_len;
|
||||
u32 packet_len;
|
||||
int cur_buf_align;
|
||||
|
||||
debug("** %s()\n", __func__);
|
||||
err = usb_bulk_msg(dev->pusb_dev,
|
||||
usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
|
||||
(void *)recv_buf,
|
||||
AX_RX_URB_SIZE,
|
||||
&actual_len,
|
||||
USB_BULK_RECV_TIMEOUT);
|
||||
debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
|
||||
actual_len, err);
|
||||
if (err != 0) {
|
||||
debug("Rx: failed to receive\n");
|
||||
return -1;
|
||||
}
|
||||
if (actual_len > AX_RX_URB_SIZE) {
|
||||
debug("Rx: received too many bytes %d\n", actual_len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
buf_ptr = recv_buf;
|
||||
while (actual_len > 0) {
|
||||
/*
|
||||
* 1st 4 bytes contain the length of the actual data plus error
|
||||
* info. Extract data length.
|
||||
*/
|
||||
if (actual_len < sizeof(packet_len)) {
|
||||
debug("Rx: incomplete packet length\n");
|
||||
return -1;
|
||||
}
|
||||
memcpy(&packet_len, buf_ptr, sizeof(packet_len));
|
||||
le32_to_cpus(&packet_len);
|
||||
if (packet_len & RX_STS_ES_) {
|
||||
debug("Rx: Error header=%#x", packet_len);
|
||||
return -1;
|
||||
}
|
||||
packet_len = ((packet_len & RX_STS_FL_) >> 16);
|
||||
|
||||
if (packet_len > actual_len - sizeof(packet_len)) {
|
||||
debug("Rx: too large packet: %d\n", packet_len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Notify net stack */
|
||||
NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4);
|
||||
|
||||
/* Adjust for next iteration */
|
||||
actual_len -= sizeof(packet_len) + packet_len;
|
||||
buf_ptr += sizeof(packet_len) + packet_len;
|
||||
cur_buf_align = (int)buf_ptr - (int)recv_buf;
|
||||
|
||||
if (cur_buf_align & 0x03) {
|
||||
int align = 4 - (cur_buf_align & 0x03);
|
||||
|
||||
actual_len -= align;
|
||||
buf_ptr += align;
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
static void smsc95xx_halt(struct eth_device *eth)
|
||||
{
|
||||
debug("** %s()\n", __func__);
|
||||
}
|
||||
|
||||
/*
|
||||
* SMSC probing functions
|
||||
*/
|
||||
void smsc95xx_eth_before_probe(void)
|
||||
{
|
||||
curr_eth_dev = 0;
|
||||
}
|
||||
|
||||
struct smsc95xx_dongle {
|
||||
unsigned short vendor;
|
||||
unsigned short product;
|
||||
};
|
||||
|
||||
static const struct smsc95xx_dongle smsc95xx_dongles[] = {
|
||||
{ 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
|
||||
{ 0x0424, 0x9500 }, /* LAN9500 Ethernet */
|
||||
{ 0x0000, 0x0000 } /* END - Do not remove */
|
||||
};
|
||||
|
||||
/* Probe to see if a new device is actually an SMSC device */
|
||||
int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
|
||||
struct ueth_data *ss)
|
||||
{
|
||||
struct usb_interface *iface;
|
||||
struct usb_interface_descriptor *iface_desc;
|
||||
int i;
|
||||
|
||||
/* let's examine the device now */
|
||||
iface = &dev->config.if_desc[ifnum];
|
||||
iface_desc = &dev->config.if_desc[ifnum].desc;
|
||||
|
||||
for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
|
||||
if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
|
||||
dev->descriptor.idProduct == smsc95xx_dongles[i].product)
|
||||
/* Found a supported dongle */
|
||||
break;
|
||||
}
|
||||
if (smsc95xx_dongles[i].vendor == 0)
|
||||
return 0;
|
||||
|
||||
/* At this point, we know we've got a live one */
|
||||
debug("\n\nUSB Ethernet device detected\n");
|
||||
memset(ss, '\0', sizeof(struct ueth_data));
|
||||
|
||||
/* Initialize the ueth_data structure with some useful info */
|
||||
ss->ifnum = ifnum;
|
||||
ss->pusb_dev = dev;
|
||||
ss->subclass = iface_desc->bInterfaceSubClass;
|
||||
ss->protocol = iface_desc->bInterfaceProtocol;
|
||||
|
||||
/*
|
||||
* We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
|
||||
* We will ignore any others.
|
||||
*/
|
||||
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
|
||||
/* is it an BULK endpoint? */
|
||||
if ((iface->ep_desc[i].bmAttributes &
|
||||
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
|
||||
if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
|
||||
ss->ep_in =
|
||||
iface->ep_desc[i].bEndpointAddress &
|
||||
USB_ENDPOINT_NUMBER_MASK;
|
||||
else
|
||||
ss->ep_out =
|
||||
iface->ep_desc[i].bEndpointAddress &
|
||||
USB_ENDPOINT_NUMBER_MASK;
|
||||
}
|
||||
|
||||
/* is it an interrupt endpoint? */
|
||||
if ((iface->ep_desc[i].bmAttributes &
|
||||
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
|
||||
ss->ep_int = iface->ep_desc[i].bEndpointAddress &
|
||||
USB_ENDPOINT_NUMBER_MASK;
|
||||
ss->irqinterval = iface->ep_desc[i].bInterval;
|
||||
}
|
||||
}
|
||||
debug("Endpoints In %d Out %d Int %d\n",
|
||||
ss->ep_in, ss->ep_out, ss->ep_int);
|
||||
|
||||
/* Do some basic sanity checks, and bail if we find a problem */
|
||||
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
|
||||
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
|
||||
debug("Problems with device\n");
|
||||
return 0;
|
||||
}
|
||||
dev->privptr = (void *)ss;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
|
||||
struct eth_device *eth)
|
||||
{
|
||||
debug("** %s()\n", __func__);
|
||||
if (!eth) {
|
||||
debug("%s: missing parameter.\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
|
||||
eth->init = smsc95xx_init;
|
||||
eth->send = smsc95xx_send;
|
||||
eth->recv = smsc95xx_recv;
|
||||
eth->halt = smsc95xx_halt;
|
||||
eth->write_hwaddr = smsc95xx_write_hwaddr;
|
||||
eth->priv = ss;
|
||||
return 1;
|
||||
}
|
||||
@ -44,6 +44,13 @@ static const struct usb_eth_prob_dev prob_dev[] = {
|
||||
.probe = asix_eth_probe,
|
||||
.get_info = asix_eth_get_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_USB_ETHER_SMSC95XX
|
||||
{
|
||||
.before_probe = smsc95xx_eth_before_probe,
|
||||
.probe = smsc95xx_eth_probe,
|
||||
.get_info = smsc95xx_eth_get_info,
|
||||
},
|
||||
#endif
|
||||
{ }, /* END */
|
||||
};
|
||||
|
||||
@ -51,6 +51,11 @@ struct ueth_data {
|
||||
unsigned char irqinterval; /* Intervall for IRQ Pipe */
|
||||
|
||||
/* private fields for each driver can go here if needed */
|
||||
#ifdef CONFIG_USB_ETHER_SMSC95XX
|
||||
size_t rx_urb_size; /* maximum USB URB size */
|
||||
u32 mac_cr; /* MAC control register value */
|
||||
int have_hwaddr; /* 1 if we have a hardware MAC address */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
@ -65,4 +70,12 @@ int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
|
||||
struct eth_device *eth);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_ETHER_SMSC95XX
|
||||
void smsc95xx_eth_before_probe(void);
|
||||
int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
|
||||
struct ueth_data *ss);
|
||||
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
|
||||
struct eth_device *eth);
|
||||
#endif
|
||||
|
||||
#endif /* __USB_ETHER_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user