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https://github.com/u-boot/u-boot.git
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Build fix/update of AFEB9260
Make AFEB9260 build again. Based on fix for AT91SAM9260EK. Signed-off-by: Sergey Lapin <slapin@ossfans.org>
This commit is contained in:
Sergey Lapin
Albert ARIBAUD
parent
6c169c12d7
commit
282e27c0b7
@ -31,7 +31,7 @@
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <netdev.h>
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@ -48,28 +48,28 @@ DECLARE_GLOBAL_DATA_PTR;
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static void afeb9260_nand_hw_init(void)
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{
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unsigned long csa;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Assign CS3 to NAND/SmartMedia Interface */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 |
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AT91_SMC_TDF_(2));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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@ -81,10 +81,15 @@ static void afeb9260_nand_hw_init(void)
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#ifdef CONFIG_MACB
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static void afeb9260_macb_hw_init(void)
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{
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unsigned long rstc;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
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struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
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unsigned long erstl;
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/* Enable EMAC clock */
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writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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/*
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* Disable pull-up on:
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@ -103,24 +108,22 @@ static void afeb9260_macb_hw_init(void)
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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&pioa->pudr);
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rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
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erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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AT91_RSTC_ERSTL | (0x0D << 8) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
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AT91_RSTC_MR_URSTEN, &rstc->mr);
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writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
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;
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(rstc) |
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AT91_RSTC_URSTEN);
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writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
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&rstc->mr);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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@ -129,23 +132,29 @@ static void afeb9260_macb_hw_init(void)
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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&pioa->puer);
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at91_macb_hw_init();
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}
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#endif
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int board_early_init_f(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clocks for all PIOs */
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writel((1 << ATMEL_ID_PIOA) |
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(1 << ATMEL_ID_PIOB) |
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(1 << ATMEL_ID_PIOC),
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&pmc->pcer);
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return 0;
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}
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91SAM9260EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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at91_serial_hw_init();
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at91_seriald_hw_init();
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#ifdef CONFIG_CMD_NAND
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afeb9260_nand_hw_init();
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#endif
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@ -159,8 +168,10 @@ int board_init(void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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@ -174,7 +185,7 @@ int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01);
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01);
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#endif
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return rc;
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}
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@ -25,17 +25,21 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 SoC*/
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#include <asm/arch/hardware.h>
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#define CONFIG_AT91_LEGACY
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#define CONFIG_SYS_TEXT_BASE 0x21f00000
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
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#define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_AFEB9260 /* AFEB9260 Board */
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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@ -46,12 +50,14 @@
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91_GPIO 1
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#define CONFIG_ATMEL_USART 1
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#undef CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#define CONFIG_USART3 1 /* USART 3 is DBGU */
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#define CONFIG_ATMEL_LEGACY
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#define CONFIG_AT91_GPIO
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#define CONFIG_AT91_PULLUP 1
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_USART3 /* USART 3 is DBGU */
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#define CONFIG_BOOTDELAY 3
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@ -74,20 +80,20 @@
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_SOURCE
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#define CONFIG_CMD_PING 1
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#define CONFIG_CMD_DHCP 1
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NAND 1
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#define CONFIG_CMD_USB 1
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_USB
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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/* DataFlash */
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#define CONFIG_ATMEL_DATAFLASH_SPI
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#define CONFIG_HAS_DATAFLASH 1
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#define CONFIG_HAS_DATAFLASH
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#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
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@ -100,8 +106,8 @@
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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@ -112,37 +118,36 @@
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#endif
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/* NOR flash - no real flash on this board */
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#define CONFIG_SYS_NO_FLASH 1
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#define CONFIG_SYS_NO_FLASH
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/* Ethernet */
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#define CONFIG_MACB 1
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#undef CONFIG_RMII /* We have full MII there */
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#define CONFIG_RESET_PHY_R 1
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#define CONFIG_MACB
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#define CONFIG_RESET_PHY_R
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_MULTI
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#define CONFIG_NET_RETRY_COUNT 20
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x21e00000
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#undef CONFIG_SYS_USE_DATAFLASH_CS0
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#define CONFIG_SYS_USE_DATAFLASH_CS1 1
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#undef CONFIG_SYS_USE_NANDFLASH
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#define CONFIG_SYS_USE_DATAFLASH_CS1
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#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 -\
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GENERATED_GBL_DATA_SIZE)
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/* bootstrap + u-boot + env + linux in dataflash on CS1 */
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#define CONFIG_ENV_IS_IN_DATAFLASH 1
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#define CONFIG_ENV_IS_IN_DATAFLASH
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
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#define CONFIG_ENV_OFFSET 0x4200
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#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
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@ -159,8 +164,8 @@
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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/*
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* Size of malloc() pool
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@ -172,5 +177,4 @@
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#ifdef CONFIG_USE_IRQ
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#error CONFIG_USE_IRQ not supported
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#endif
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#endif
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