board: asus: transformer: add ASUS Transformer T20 family support

The Asus Eee Pad Transformer family are 2-in-1 detachable/slider
tablets developed by Asus that run the Android operating system.
The Eee Pad Transformers feature a 10.1-inch (260 mm) display,
an Nvidia Tegra 2 dual-core chip, 1 GB of RAM, and 16/32 GB of storage.
Transformers board derives from Nvidia Ventana development board.

This patch brings support for all 3 known T20 Transformers:
- Asus Eee Pad Transformer TF101
- Asus Eee Pad Transformer TF101G
- Asus Eee Pad Slider SL101

Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101
Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # ASUS TF101
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Svyatoslav Ryhel 2022-01-27 19:42:04 +02:00
parent bd356e05cd
commit 28144ba8d0
17 changed files with 904 additions and 1 deletions

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@ -94,7 +94,11 @@ dtb-$(CONFIG_ARCH_S5P4418) += \
dtb-$(CONFIG_ARCH_MESON) += \
meson-a1-ad401.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
dtb-$(CONFIG_ARCH_TEGRA) += \
tegra20-asus-sl101.dtb \
tegra20-asus-tf101.dtb \
tegra20-asus-tf101g.dtb \
tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \

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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra20-asus-transformer.dtsi"
/ {
model = "ASUS EeePad Slider SL101";
compatible = "asus,sl101", "nvidia,tegra20";
};

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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra20-asus-transformer.dtsi"
/ {
model = "ASUS EeePad Transformer TF101";
compatible = "asus,tf101", "nvidia,tegra20";
};

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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra20-asus-transformer.dtsi"
/ {
model = "ASUS EeePad Transformer TF101G";
compatible = "asus,tf101g", "nvidia,tegra20";
};

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@ -0,0 +1,545 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
/ {
chosen {
stdout-path = &uartd;
};
aliases {
i2c0 = &pwr_i2c;
mmc0 = &sdmmc4; /* eMMC */
mmc1 = &sdmmc3; /* MicroSD */
rtc0 = &pmic;
rtc1 = "/rtc@7000e000";
usb0 = &usb1;
usb1 = &usb3; /* Dock USB */
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>;
};
host1x@50000000 {
dc@54200000 {
rgb {
status = "okay";
nvidia,panel = <&panel>;
};
};
};
pinmux@70000014 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
ata {
nvidia,pins = "ata";
nvidia,function = "ide";
};
atb {
nvidia,pins = "atb", "gma", "gme";
nvidia,function = "sdio4";
};
atc {
nvidia,pins = "atc";
nvidia,function = "nand";
};
atd {
nvidia,pins = "atd", "ate", "gmb", "spia",
"spib", "spic";
nvidia,function = "gmi";
};
cdev1 {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
};
cdev2 {
nvidia,pins = "cdev2";
nvidia,function = "pllp_out4";
};
crtp {
nvidia,pins = "crtp";
nvidia,function = "crt";
};
lm1 {
nvidia,pins = "lm1";
nvidia,function = "rsvd3";
};
csus {
nvidia,pins = "csus";
nvidia,function = "vi_sensor_clk";
};
dap1 {
nvidia,pins = "dap1";
nvidia,function = "dap1";
};
dap2 {
nvidia,pins = "dap2";
nvidia,function = "dap2";
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
};
dap4 {
nvidia,pins = "dap4";
nvidia,function = "dap4";
};
dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
nvidia,function = "vi";
};
dtf {
nvidia,pins = "dtf";
nvidia,function = "i2c3";
};
gmc {
nvidia,pins = "gmc";
nvidia,function = "uartd";
};
gmd {
nvidia,pins = "gmd";
nvidia,function = "sflash";
};
gpu {
nvidia,pins = "gpu";
nvidia,function = "pwm";
};
gpu7 {
nvidia,pins = "gpu7";
nvidia,function = "rtck";
};
gpv {
nvidia,pins = "gpv", "slxa";
nvidia,function = "pcie";
};
hdint {
nvidia,pins = "hdint";
nvidia,function = "hdmi";
};
i2cp {
nvidia,pins = "i2cp";
nvidia,function = "i2cp";
};
irrx {
nvidia,pins = "irrx", "irtx";
nvidia,function = "uartb";
};
kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf";
nvidia,function = "kbc";
};
lcsn {
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
"lsdi", "lvp0";
nvidia,function = "rsvd4";
};
ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lpp", "lpw0",
"lpw2", "lsc0", "lsc1", "lsck", "lsda",
"lspi", "lvp1", "lvs";
nvidia,function = "displaya";
};
owc {
nvidia,pins = "owc", "spdi", "spdo", "uac";
nvidia,function = "rsvd2";
};
pmc {
nvidia,pins = "pmc";
nvidia,function = "pwr_on";
};
rm {
nvidia,pins = "rm";
nvidia,function = "i2c1";
};
sdb {
nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
nvidia,function = "sdio3";
};
sdio1 {
nvidia,pins = "sdio1";
nvidia,function = "sdio1";
};
slxd {
nvidia,pins = "slxd";
nvidia,function = "spdif";
};
spid {
nvidia,pins = "spid", "spie", "spif";
nvidia,function = "spi1";
};
spig {
nvidia,pins = "spig", "spih";
nvidia,function = "spi2_alt";
};
uaa {
nvidia,pins = "uaa", "uab", "uda";
nvidia,function = "ulpi";
};
uad {
nvidia,pins = "uad";
nvidia,function = "irda";
};
uca {
nvidia,pins = "uca", "ucb";
nvidia,function = "uartc";
};
conf_ata {
nvidia,pins = "ata", "atb", "atc", "atd",
"cdev1", "cdev2", "dap1", "dap4",
"dte", "ddc", "dtf", "gma", "gmc",
"gme", "gpu", "gpu7", "gpv", "i2cp",
"irrx", "irtx", "pta", "rm", "sdc",
"sdd", "slxc", "slxd", "slxk", "spdi",
"spdo", "uac", "uad",
"uda", "csus";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ate {
nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd",
"owc", "spia", "spib", "spic",
"spid", "spie", "spig", "slxa";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
conf_crtp {
nvidia,pins = "crtp", "spih";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_spif {
nvidia,pins = "spif";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsck", "lsda", "lsdi", "lvp0";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf", "sdio1", "uaa", "uab",
"uca", "ucb";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
"lvp1", "lvs", "pmc", "sdb";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
};
drive_sdio1 {
nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1";
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <31>;
nvidia,pull-up-strength = <31>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
};
drive_csus {
nvidia,pins = "drive_csus";
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
nvidia,pull-down-strength = <31>;
nvidia,pull-up-strength = <31>;
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
};
};
state_i2cmux_ddc: pinmux-i2cmux-ddc {
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
};
pta {
nvidia,pins = "pta";
nvidia,function = "rsvd4";
};
};
state_i2cmux_idle: pinmux-i2cmux-idle {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
nvidia,function = "rsvd4";
};
};
state_i2cmux_pta: pinmux-i2cmux-pta {
ddc {
nvidia,pins = "ddc";
nvidia,function = "rsvd4";
};
pta {
nvidia,pins = "pta";
nvidia,function = "i2c2";
};
};
};
uartd: serial@70006300 {
status = "okay";
clock-frequency = <216000000>;
};
pwm: pwm@7000a000 {
status = "okay";
};
pwr_i2c: i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
pmic: tps6586x@34 {
compatible = "ti,tps6586x";
reg = <0x34>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,system-power-controller;
#gpio-cells = <2>;
gpio-controller;
regulators {
avdd_usb: ldo3 {
regulator-name = "vdd_ldo3,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vcore_emmc: ldo5 {
regulator-name = "vdd_ldo5,vcore_mmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
};
};
};
/* USB via ASUS connector */
usb1: usb@c5000000 {
status = "okay";
dr_mode = "otg";
};
usb-phy@c5000000 {
status = "okay";
nvidia,xcvr-setup-use-fuses;
};
/* Dock's USB port */
usb3: usb@c5008000 {
status = "okay";
};
sdmmc3: sdhci@c8000400 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_3v3_sys>;
vqmmc-supply = <&vdd_3v3_sys>;
};
sdmmc4: sdhci@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
vmmc-supply = <&vcore_emmc>;
vqmmc-supply = <&vdd_3v3_sys>;
};
backlight: backlight {
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
power-supply = <&vdd_3v3_sys>;
pwms = <&pwm 2 4000000>;
brightness-levels = <1 35 70 105 140 175 210 255>;
default-brightness-level = <5>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k-in {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "pmic-oscillator";
};
gpio-keys {
compatible = "gpio-keys";
key-power {
label = "Power";
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
linux,code = <KEY_ENTER>;
};
key-volume-down {
label = "Volume Down";
gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
};
key-volume-up {
label = "Volume Up";
gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
};
switch-dock-hall-sensor {
label = "Lid sensor";
gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>;
linux,code = <SW_LID>;
};
};
panel: panel {
compatible = "simple-panel";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
display-timings {
timing@0 {
clock-frequency = <71200000>;
hactive = <1280>;
hfront-porch = <8>;
hback-porch = <18>;
hsync-len = <184>;
vactive = <800>;
vfront-porch = <4>;
vback-porch = <8>;
vsync-len = <3>;
};
};
};
vdd_3v3_sys: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_vs";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_pnl_reg: regulator-pnl {
compatible = "regulator-fixed";
regulator-name = "vdd_panel";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

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@ -47,6 +47,10 @@ config TARGET_TEC
bool "Avionic Design Tamonten Evaluation Carrier"
select BOARD_LATE_INIT
config TARGET_TRANSFORMER_T20
bool "Asus Tegra20 Transformer board"
select BOARD_LATE_INIT
config TARGET_TRIMSLICE
bool "Compulab TrimSlice board"
select BOARD_LATE_INIT
@ -72,6 +76,7 @@ source "board/compal/paz00/Kconfig"
source "board/avionic-design/plutux/Kconfig"
source "board/nvidia/seaboard/Kconfig"
source "board/avionic-design/tec/Kconfig"
source "board/asus/transformer-t20/Kconfig"
source "board/compulab/trimslice/Kconfig"
source "board/nvidia/ventana/Kconfig"
source "board/toradex/colibri_t20/Kconfig"

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@ -0,0 +1,12 @@
if TARGET_TRANSFORMER_T20
config SYS_BOARD
default "transformer-t20"
config SYS_VENDOR
default "asus"
config SYS_CONFIG_NAME
default "transformer-t20"
endif

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@ -0,0 +1,8 @@
TRANSFORMER T20 BOARD
M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
F: arch/arm/dts/tegra20-asus-*
F: board/asus/transformer-t20/
F: configs/transformer_t20_defconfig
F: doc/board/asus/transformer_t20.rst
F: include/configs/transformer-t20.h

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@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2010,2011
# NVIDIA Corporation <www.nvidia.com>
#
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
obj-y += transformer-t20.o

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@ -0,0 +1 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101"

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@ -0,0 +1 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101"

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@ -0,0 +1 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101g"

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@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* (C) Copyright 2021
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
/* T20 Transformers derive from Ventana board */
#include <dm.h>
#include <i2c.h>
#include <log.h>
#include <linux/delay.h>
#define TPS6586X_I2C_ADDRESS 0x34
#define TPS6586X_SUPPLYENE 0x14
#define EXITSLREQ_BIT BIT(1)
#define SLEEP_MODE_BIT BIT(3)
#ifdef CONFIG_CMD_POWEROFF
int do_poweroff(struct cmd_tbl *cmdtp,
int flag, int argc, char *const argv[])
{
struct udevice *dev;
uchar data_buffer[1];
int ret;
ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev);
if (ret) {
log_debug("cannot find PMIC I2C chip\n");
return 0;
}
ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] &= ~EXITSLREQ_BIT;
ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
if (ret)
return ret;
data_buffer[0] |= SLEEP_MODE_BIT;
ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
if (ret)
return ret;
// wait some time and then print error
mdelay(5000);
printf("Failed to power off!!!\n");
return 1;
}
#endif

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@ -0,0 +1,82 @@
CONFIG_ARM=y
CONFIG_ARCH_TEGRA=y
CONFIG_SUPPORT_PASSING_ATAGS=y
CONFIG_CMDLINE_TAG=y
CONFIG_INITRD_TAG=y
CONFIG_TEXT_BASE=0x00110000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x3000
CONFIG_ENV_OFFSET=0xFFFFD000
CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101"
CONFIG_SPL_TEXT_BASE=0x00108000
CONFIG_SPL_STACK=0xffffc
CONFIG_TEGRA20=y
CONFIG_TARGET_TRANSFORMER_T20=y
CONFIG_TEGRA_ENABLE_UARTD=y
CONFIG_CMD_EBTUPDATE=y
CONFIG_SYS_LOAD_ADDR=0x2000000
CONFIG_BUTTON_CMD=y
CONFIG_BOOTDELAY=0
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_KEYED_CTRLC=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
CONFIG_SYS_PBSIZE=2085
CONFIG_SPL_FOOTPRINT_LIMIT=y
CONFIG_SPL_MAX_FOOTPRINT=0x8000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
CONFIG_SYS_PROMPT="Tegra20 (Transformer) # "
# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_BUTTON=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x11000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="ASUS"
CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
CONFIG_USB_GADGET_PRODUCT_NUM=0x4e0f
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_LOGO is not set
# CONFIG_VIDEO_BPP8 is not set
CONFIG_VIDEO_TEGRA20=y

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@ -7,4 +7,5 @@ ASUS
:maxdepth: 2
grouper_common
transformer_t20
transformer_t30

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@ -0,0 +1,129 @@
.. SPDX-License-Identifier: GPL-2.0+
U-Boot for the ASUS Eee Pad Transformer device family
=====================================================
``DISCLAMER!`` Moving your ASUS Eee Pad Transformer/Slider to use U-Boot
assumes replacement of the vendor ASUS bootloader. Vendor Android firmwares
will no longer be able to run on the device. This replacement IS reversible.
Quick Start
-----------
- Build U-Boot
- Process U-Boot
- Flashing U-Boot into the eMMC
- Boot
- Self Upgrading
Build U-Boot
------------
Device support is implemented by applying config fragment to a generic board
defconfig. Valid fragments are ``tf101.config``, ``tf101g.config`` and
``sl101.config``.
.. code-block:: bash
$ export CROSS_COMPILE=arm-linux-gnueabi-
$ make transformer_t20_defconfig tf101.config # For TF101
$ make
After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
image, ready for further processing.
Process U-Boot
--------------
``DISCLAMER!`` All questions related to the re-crypt work should be asked
in re-crypt repo issues. NOT HERE!
re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
usable by device. This process is required only on the first installation or
to recover the device in case of a failed update.
Permanent installation can be performed either by using the nv3p protocol or by
pre-loading just built U-Boot into RAM.
Processing for the NV3P protocol
********************************
.. code-block:: bash
$ git clone https://gitlab.com/grate-driver/re-crypt.git
$ cd re-crypt # place your u-boot-dtb-tegra.bin here
$ ./re-crypt.py --dev tf101
The script will produce a ``repart-block.bin`` ready to flash.
Processing for pre-loaded U-Boot
********************************
The procedure is the same, but the ``--split`` argument is used with the
``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
to flash.
Flashing U-Boot into the eMMC
-----------------------------
``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
Permanent installation can be performed either by using the nv3p protocol or by
pre-loading just built U-Boot into RAM.
Flashing with the NV3P protocol
*******************************
Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
pre-loading vendor bootloader with the Fusée Gelée.
With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
$ wheelie --blob blob.bin
$ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
When flashing is done, reboot the device.
Flashing with a pre-loaded U-Boot
*********************************
U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
of U-Boot permanently into eMMC.
While pre-loading U-Boot, hold the ``volume down`` button which will trigger
the bootmenu. There, select ``fastboot`` using the volume and power buttons.
After, on host PC, do:
.. code-block:: bash
$ fastboot flash 0.1 bct.img
$ fastboot flash 0.2 ebt.img
$ fastboot reboot
Device will reboot.
Boot
----
To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
eMMC. Additionally, if the Volume Down button is pressed while booting, the
device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
and update bootloader (check the next chapter).
Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
the user to use/partition it in any way the user desires.
Self Upgrading
--------------
Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
and insert it into the tablet. Enter bootmenu, choose update the bootloader
option with the Power button and U-Boot should update itself. Once the process
is completed, U-Boot will ask to press any button to reboot.

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* (C) Copyright 2022
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "tegra20-common.h"
#include "transformer-common.h"
/* Board-specific serial config */
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#include "tegra-common-post.h"
#endif /* __CONFIG_H */