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mtd: nand: force NAND_CMD_READID onto 8-bit bus

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As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

Thus porting  following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.

    commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
    mtd: nand: force NAND_CMD_READID onto 8-bit bus
    Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship)

    The NAND command helpers tend to automatically shift the column address
    for x16 bus devices, since most commands expect a word address, not a
    byte address. The Read ID command, however, expects an 8-bit address
    (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
    0x20).

    This fixes the column address for a few drivers which imitate the
    nand_base defaults.

Signed-off-by: Pekon Gupta <pekon@ti.com>
This commit is contained in:
Brian Norris 2014-05-06 00:46:17 +05:30 committed by Tom Rini
parent b9ae609fdb
commit 27ce9e4290
5 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/mtd/nand/am335x_spl_bch.c
View File

@ -55,7 +55,7 @@ static int nand_command(int block, int page, uint32_t offs,
}
/* Shift the offset from byte addressing to word addressing. */
if (this->options & NAND_BUSWIDTH_16)
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
/* Set ALE and clear CLE to start address cycle */

2
drivers/mtd/nand/atmel_nand.c
View File

@ -1195,7 +1195,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if (this->options & NAND_BUSWIDTH_16)
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);

6
drivers/mtd/nand/nand_base.c
View File

@ -575,7 +575,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
/* Serially input address */
if (column != -1) {
/* Adjust columns for 16 bit buswidth */
if (chip->options & NAND_BUSWIDTH_16)
if ((chip->options & NAND_BUSWIDTH_16) &&
!nand_opcode_8bits(command))
column >>= 1;
chip->cmd_ctrl(mtd, column, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
@ -668,7 +669,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
/* Serially input address */
if (column != -1) {
/* Adjust columns for 16 bit buswidth */
if (chip->options & NAND_BUSWIDTH_16)
if ((chip->options & NAND_BUSWIDTH_16) &&
!nand_opcode_8bits(command))
column >>= 1;
chip->cmd_ctrl(mtd, column, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;

2
drivers/mtd/nand/nand_spl_simple.c
View File

@ -78,7 +78,7 @@ static int nand_command(int block, int page, uint32_t offs,
}
/* Shift the offset from byte addressing to word addressing. */
if (this->options & NAND_BUSWIDTH_16)
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
/* Begin command latch cycle */

10
include/linux/mtd/nand.h
View File

@ -719,4 +719,14 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
}
#endif
/**
* Check if the opcode's address should be sent only on the lower 8 bits
* @command: opcode to check
*/
static inline int nand_opcode_8bits(unsigned int command)
{
return command == NAND_CMD_READID;
}
#endif /* __LINUX_MTD_NAND_H */