* Patch by Martin Krause, 17 Jul 2003:

add delay to get I2C working with "imm" command and s3c24x0_i2c.c * Patch by Richard Woodruff, 17 July 03: - Fixed bug in OMAP1510 baud rate divisor settings. * Patch by Nye Liu, 16 July 2003: MPC860FADS fixes: - add MPC86xADS support (uses MPC86xADS.h) - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T) o PLPRCR changes o BRG changes (EXTAL/XTAL restricted to 10MHz) o don't trust gclk() software measurement by default, depend on CONFIG_8xx_GCLK_FREQ - add DRAM SIMM not installed detection - use more "correct" SDRAM initialization sequence - allow different SDRAM sizes (8xxADS has 8M) - default DER is 0 - remove unused MAMR defines from FADS860T.h (all done in fads.c) - rename MAMR/MBMR defines to be more consistent. Should eventually be merged into MxMR to better reflect the PowerQUICC datasheet. * Patch by Yuli Barcohen, 16 Jul 2003: support new Motorola PQ2FADS-ZU evaluation board which replaced MPC8260ADS and MPC8266ADS
2024-11-24 04:34:22 +08:00 · 2003-07-17 23:16:40 +00:00 · 2003-07-17 23:16:40 +00:00 · 2535d60277
commit 2535d60277
parent 945af8d723
47 changed files with 1466 additions and 710 deletions
--- a/30
+++ b/30
@ -1,3 +1,33 @@
 ======================================================================
 Changes for U-Boot 0.4.5:
 ======================================================================
 * Patch by Martin Krause, 17 Jul 2003:
  add delay to get I2C working with "imm" command and s3c24x0_i2c.c
 * Patch by Richard Woodruff, 17 July 03:
  - Fixed bug in OMAP1510 baud rate divisor settings. 
 * Patch by Nye Liu, 16 July 2003:
  MPC860FADS fixes:
  - add MPC86xADS support (uses MPC86xADS.h)
  - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
    o PLPRCR changes
    o BRG changes (EXTAL/XTAL restricted to 10MHz)
    o don't trust gclk() software measurement by default, depend on
      CONFIG_8xx_GCLK_FREQ
  - add DRAM SIMM not installed detection
  - use more "correct" SDRAM initialization sequence
  - allow different SDRAM sizes (8xxADS has 8M)
  - default DER is 0
  - remove unused MAMR defines from FADS860T.h (all done in fads.c)
  - rename MAMR/MBMR defines to be more consistent. Should eventually
    be merged into MxMR to better reflect the PowerQUICC datasheet.
 * Patch by Yuli Barcohen, 16 Jul 2003:
  support new Motorola PQ2FADS-ZU evaluation board which replaced
  MPC8260ADS and MPC8266ADS
 ======================================================================
 Changes for U-Boot 0.4.4:
 ======================================================================
--- a/12
+++ b/12
@ -39,12 +39,12 @@ LIST_8xx="	\
 	IP860		IVML24		IVML24_128	IVML24_256	\
 	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
 	LANTEC	        lwmon   	MBX		MBX860T		\
-	MHPC		MVS1		NETVIA		NETVIA_V2	\
+	MHPC		MPC86xADS	MVS1		NETVIA		\
-	NX823		pcu_e		R360MPI		RBC823		\
+	NETVIA_V2	NX823		pcu_e		R360MPI		\
-	rmu		RPXClassic	RPXlite		RRvision	\
+	RBC823		rmu		RPXClassic	RPXlite		\
-	SM850		SPD823TS	svm_sc8xx	SXNI855T	\
+	RRvision	SM850		SPD823TS	svm_sc8xx	\
-	TOP860		TQM823L		TQM823L_LCD	TQM850L		\
+	SXNI855T	TOP860		TQM823L		TQM823L_LCD	\
-	TQM855L		TQM860L		v37				\
+	TQM850L		TQM855L		TQM860L		v37		\
 "
 #########################################################################
--- a/1
+++ b/1
@ -227,6 +227,7 @@ ETX094_config	:	unconfig
 FADS823_config	\
 FADS850SAR_config \
 MPC86xADS_config \
 FADS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads
--- a/27
+++ b/27
@ -197,7 +197,7 @@ Directory Hierarchy:
 - board/lwmon	Files specific to LWMON	     boards
 - board/mbx8xx	Files specific to MBX	     boards
 - board/mpc8260ads
-		Files specific to MMPC8260ADS boards
+		Files specific to MPC8260ADS and PQ2FADS-ZU boards
 - board/mpl/	Files specific to boards manufactured by MPL
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
@ -383,6 +383,14 @@ The following options need to be configured:
 					  the lcd display every second with
 					  a "rotator" |\-/|\-/
 - Board flavour: (if CONFIG_MPC8260ADS is defined)
 		CONFIG_ADSTYPE
 		Possible values are:
 			CFG_8260ADS	- original MPC8260ADS
 			CFG_8266ADS	- MPC8266ADS (untested)
 			CFG_PQ2FADS	- PQ2FADS-ZU
 - MPC824X Family Member (if CONFIG_MPC824X is defined)
 	Define exactly one of
 	CONFIG_MPC8240, CONFIG_MPC8245
@ -989,8 +997,8 @@ The following options need to be configured:
 		is FALSE, it clears it (low).
 		eg: #define I2C_SDA(bit) \
-		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-		         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 		I2C_SCL(bit)
@ -998,8 +1006,8 @@ The following options need to be configured:
 		is FALSE, it clears it (low).
 		eg: #define I2C_SCL(bit) \
-		         if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-		         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 		I2C_DELAY
@ -1687,9 +1695,10 @@ Low Level (hardware related) configuration options:
 - CFG_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.
-		Needed on some 8260 systems (MPC8260ADS and RPXsuper)
+
-		to be able to adjust the position of the IMMR
+                Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
-		register after a reset.
+                and RPXsuper) to be able to adjust the position of
                the IMMR register after a reset.
 - Floppy Disk Support:
 		CFG_FDC_DRIVE_NUMBER
@ -1862,7 +1871,7 @@ configurations; the following names are supported:
    GENIETV_config	  TQM823L_config	PIP405_config
    GEN860T_config	  EBONY_config		FPS860L_config
    ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
-    at91rm9200dk_config	  omap1510inn_config
+    at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
 Note: for some board special configuration names may exist; check  if
      additional  information is available from the board vendor; for
--- a/board/eltec/mhpc/mhpc.c
+++ b/board/eltec/mhpc/mhpc.c
@ -254,7 +254,7 @@ long int initdram (int board_type)
    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
    memctl->memc_mamr  = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
-    memctl->memc_mbmr  = MAMR_GPL_B4DIS;
+    memctl->memc_mbmr  = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
    memctl->memc_mptpr = MPTPR_PTP_DIV64;
    memctl->memc_mar   = 0x00008800;
--- a/board/fads/fads.c
+++ b/board/fads/fads.c
--- a/board/flagadm/flagadm.c
+++ b/board/flagadm/flagadm.c
@ -128,7 +128,7 @@ long int initdram (int board_type)
 	/* That should do it, just enable the periodic refresh in burst of 4*/
 	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
-	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_B4DIS);
+	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
 	size_b0 = 16*1024*1024;
@ -141,7 +141,7 @@ long int initdram (int board_type)
 	upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
-	memctl->memc_mbmr = MAMR_GPL_B4DIS;
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;
 	memctl->memc_or4 = CFG_OR4;
 	memctl->memc_br4 = CFG_BR4;
--- a/board/genietv/genietv.c
+++ b/board/genietv/genietv.c
@ -163,7 +163,7 @@ long int initdram (int board_type)
    memctl->memc_mcr  = 0x80804105;	/* SDRAM bank 1 */
    /* Execute refresh 8 times */
-    memctl->memc_mbmr = (CFG_MBMR_8COL & ~MAMR_TLFB_MSK) | MAMR_TLFB_8X ;
+    memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X ;
    memctl->memc_mcr  = 0x80802130;	/* SDRAM bank 0 - execute twice */
--- a/board/gth/gth.c
+++ b/board/gth/gth.c
@ -218,7 +218,7 @@ int _initsdram (uint base, uint * noMbytes)
 			   sizeof (fpga_table) / sizeof (uint));
 	/* Enable UPWAITB */
-	mc->memc_mbmr = MAMR_GPL_B4DIS;	/* (16-13) */
+	mc->memc_mbmr = MBMR_GPL_B4DIS;	/* (16-13) */
 	/* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
 	mc->memc_or2 = 0xffc00000 | OR_BI;
--- a/board/ivm/ivm.c
+++ b/board/ivm/ivm.c
@ -246,14 +246,14 @@ initdram (int board_type)
    udelay(1);
    memctl->memc_mcr = 0x80806130;	/* autorefresh */
-    memctl->memc_mbmr |= MAMR_PTBE;	/* refresh enabled */
+    memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
    /*
     * Check Bank 0 Memory Size for re-configuration
     */
    size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-    memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
+    memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
    return (size_b0);
 }
--- a/board/lantec/lantec.c
+++ b/board/lantec/lantec.c
@ -149,7 +149,7 @@ long int initdram (int board_type)
 	udelay(1);		/* 0x80006106 */
 	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
-	memctl->memc_mamr |= MAMR_PTBE;	/* refresh enabled */
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
 	udelay(200);
@ -170,7 +170,7 @@ long int initdram (int board_type)
 			     (ulong *)SDRAM_BASE3_PRELIM,
 			     SDRAM_MAX_SIZE);
-	memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
+	memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
 	/*
 	 * Final mapping:
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@ -246,7 +246,7 @@ long int initdram (int board_type)
 	udelay (1);				/* 0x80006106 */
 	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
-	memctl->memc_mamr |= MAMR_PTBE;	/* refresh enabled */
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
 	udelay (200);
@ -276,11 +276,11 @@ long int initdram (int board_type)
 	if (size8 < size9) {		/* leave configuration at 9 columns */
 		size_b0 = size9;
-		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;
+		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
 		udelay (500);
 	} else {			/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
+		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
 		udelay (500);
 	}
--- a/board/mpc8260ads/mpc8260ads.c
+++ b/board/mpc8260ads/mpc8260ads.c
@ -198,11 +198,19 @@ void reset_phy (void)
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
 	/* reset the FEC port */
-	bcsr[1] &= ~FETH_RST;
+	bcsr[1] &= ~FETH1_RST;
 	udelay(2);
-	bcsr[1] |=  FETH_RST;
+	bcsr[1] |=  FETH1_RST;
 	udelay(1000);
 #ifdef CONFIG_MII
 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 	/*
 	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
 	 * Enable autonegotiation.
 	 */
 	miiphy_write(0, 16, 0x610);
 	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #else
 	/*
 	 * Ethernet PHY is configured (by means of configuration pins)
 	 * to work at 10Mb/s only. We reconfigure it using MII
@ -212,6 +220,7 @@ void reset_phy (void)
 	miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
 	miiphy_write(0, PHY_DCR,  0x0000); /* Do not bypass Rx/Tx (de)scrambler */
 	miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 #endif /* CONFIG_MII */
 }
@ -219,7 +228,7 @@ int board_pre_init (void)
 {
 	vu_long *bcsr = (vu_long *)CFG_BCSR;
-	bcsr[1] = ~FETHIEN & ~RS232EN_1;
+	bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
 	return 0;
 }
@ -231,12 +240,10 @@ long int initdram (int board_type)
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar *ramaddr, c = 0xff;
-
+	long int msize;
-	/* Initialisation is for 16MB DIMM the board is shipped with */
+	uint or;
-	long int msize = 16;
+	uint psdmr;
-	uint or    = 0xFF000CA0;
+	uint psrt;
 	uint psdmr = CFG_PSDMR;
 	uint psrt  = CFG_PSRT;
 	int i;
@ -246,22 +253,29 @@ long int initdram (int board_type)
 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
 	memctl->memc_mptpr = CFG_MPTPR;
-	/* init local sdram, bank 4 */
+#ifdef CFG_LSDRAM_BASE
-	memctl->memc_lsrt  = 0x00000010;
+	/* Init local bus SDRAM */
 	memctl->memc_lsrt  = CFG_LSRT;
 #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
 	memctl->memc_or3   = 0xFF803280;
 	memctl->memc_br3   = CFG_LSDRAM_BASE | 0x00001861;
 #else  				  /* CS4 */
 	memctl->memc_or4   = 0xFFC01480;
-	memctl->memc_br4   = 0x04001861;
+	memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
-	memctl->memc_lsdmr = 0x2886A522;
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 	memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
 	ramaddr = (uchar *) CFG_LSDRAM_BASE;
 	*ramaddr = c;
-	memctl->memc_lsdmr = 0x0886A522;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
 	for (i = 0; i < 8; i++) {
 		*ramaddr = c;
 	}
-	memctl->memc_lsdmr = 0x1886A522;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
 	*ramaddr = c;
-	memctl->memc_lsdmr = 0x4086A522;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
 #endif /* CFG_LSDRAM_BASE */
-	/* init sdram dimm */
+	/* Init 60x bus SDRAM */
 #ifdef CONFIG_SPD_EEPROM
 	{
 		spd_eeprom_t spd;
@ -398,6 +412,16 @@ long int initdram (int board_type)
 		printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
 #endif /* SPD_DEBUG */
 	}
 #else  /* !CONFIG_SPD_EEPROM */
 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 	msize = 32;
 	or = 0xFE002EC0;
 #else
 	msize = 16;
 	or = 0xFF000CA0;
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 	psdmr = CFG_PSDMR;
 	psrt  = CFG_PSRT;
 #endif /* CONFIG_SPD_EEPROM */
 	memctl->memc_psrt = psrt;
 	memctl->memc_or2 = or;
@ -415,12 +439,20 @@ long int initdram (int board_type)
 	*ramaddr = c;
 #endif
-	/* return total ram size of DIMM */
+	/* return total 60x bus SDRAM size */
 	return (msize * 1024 * 1024);
 }
 int checkboard (void)
 {
 #if   CONFIG_ADSTYPE == CFG_8260ADS
 	puts ("Board: Motorola MPC8260ADS\n");
 #elif CONFIG_ADSTYPE == CFG_8266ADS
 	puts ("Board: Motorola MPC8266ADS\n");
 #elif CONFIG_ADSTYPE == CFG_PQ2FADS
 	puts ("Board: Motorola PQ2FADS-ZU\n");
 #else
 	puts ("Board: unknown\n");
 #endif
 	return 0;
 }
--- a/board/mvs1/u-boot.lds
+++ b/board/mvs1/u-boot.lds
@ -57,7 +57,6 @@ SECTIONS
    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
    cpu/mpc8xx/start.o		(.text)
    cpu/mpc8xx/speed.o		(.text)
    common/dlmalloc.o		(.text)
    lib_ppc/ppcstring.o		(.text)
    lib_generic/vsprintf.o	(.text)
@ -67,7 +66,6 @@ SECTIONS
    lib_generic/string.o	(.text)
    lib_ppc/extable.o		(.text)
    lib_ppc/kgdb.o		(.text)
 /*  lib_ppc/ticks.o		(.text) */
  . = env_offset;
    common/environment.o(.text)
--- a/board/r360mpi/r360mpi.c
+++ b/board/r360mpi/r360mpi.c
@ -205,7 +205,7 @@ long int initdram (int board_type)
 	memctl->memc_br3 = CFG_BR3_CAN;
 	/* Initialize MBMR */
-	memctl->memc_mbmr = MAMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */
 	/* Initialize UPMB for CAN: single read */
 	memctl->memc_mdr = 0xFFFFC004;
--- a/board/siemens/CCM/ccm.c
+++ b/board/siemens/CCM/ccm.c
@ -267,7 +267,7 @@ void can_driver_enable (void)
    volatile memctl8xx_t *memctl = &immap->im_memctl;
    /* Initialize MBMR */
-    memctl->memc_mbmr = MAMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+    memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
    /* Initialize UPMB for CAN: single read */
    memctl->memc_mdr = 0xFFFFC004;
--- a/board/siemens/pcu_e/pcu_e.c
+++ b/board/siemens/pcu_e/pcu_e.c
@ -217,9 +217,9 @@ initdram (int board_type)
 #endif	/* XXX */
    reg  =  memctl->memc_mamr;
-    reg &= ~MAMR_TLFB_MSK;		/* switch timer loop ... */
+    reg &= ~MAMR_TLFA_MSK;		/* switch timer loop ... */
-    reg |=  MAMR_TLFB_4X;		/* ... to 4x */
+    reg |=  MAMR_TLFA_4X;		/* ... to 4x */
-    reg |=  MAMR_PTBE;			/* enable refresh */
+    reg |=  MAMR_PTAE;			/* enable refresh */
    memctl->memc_mamr = reg;
    udelay(200);
@ -246,7 +246,7 @@ initdram (int board_type)
    size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 #endif	/* XXX */
-    memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
+    memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
    /*
     * Final mapping:
--- a/board/spd8xx/spd8xx.c
+++ b/board/spd8xx/spd8xx.c
@ -200,14 +200,14 @@ initdram (int board_type)
    udelay(1);
    memctl->memc_mcr = 0x80806106;
-    memctl->memc_mbmr |= MAMR_PTBE;	/* refresh enabled */
+    memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
    /*
     * Check Bank 0 Memory Size for re-configuration
     */
    size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-    memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
+    memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
    return (size_b0);
 }
--- a/board/v37/v37.c
+++ b/board/v37/v37.c
@ -140,7 +140,7 @@ long int initdram (int board_type)
    memctl->memc_br3 = CFG_BR3_CAN;
    /* Initialize MBMR */
-    memctl->memc_mamr = MAMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+    memctl->memc_mamr = MAMR_GPL_A4DIS;	/* GPL_A4 ouput line Disable */
    /* Initialize UPMB for CAN: single read */
    memctl->memc_mdr = 0xFFFFC004;
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@ -507,6 +507,9 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 				if(i2c_write(chip, addr, alen, (char *)&data, size) != 0) {
 					printf("Error writing the chip.\n");
 				}
 #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
 				udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 #endif
 				if (incrflag)
 					addr += size;
 			}
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@ -42,12 +42,23 @@
 static char *cpu_warning = "\n         " \
 	"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
-#if ((defined(CONFIG_MPC860) || defined(CONFIG_MPC855)) && \
+#if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
     !defined(CONFIG_MPC862))
-# ifdef CONFIG_MPC855
+
 # if defined(CONFIG_MPC855)
 #  define	ID_STR	"PC855"
 # elif defined(CONFIG_MPC852T)
 #  define	ID_STR	"PC852T"
 # elif defined(CONFIG_MPC859T)
 #  define	ID_STR	"PC859T"
 # elif defined(CONFIG_MPC859DSL)
 #  define	ID_STR	"PC859DSL"
 # elif defined(CONFIG_MPC860P)
 #  define	ID_STR	"PC860P"
 # elif defined(CONFIG_MPC866T)
 #  define	ID_STR	"PC866T"
 # else
-#  define	ID_STR	"PC860"
+#  define	ID_STR	"PC86x"	/* unknown 86x chip */
 # endif
 static int check_CPU (long clock, uint pvr, uint immr)
@ -68,6 +79,10 @@ static int check_CPU (long clock, uint pvr, uint immr)
 	m = 0;
 	switch (k) {
 #ifdef CONFIG_MPC866_et_al
                /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
 	case 0x08000003: pre = 'M'; suf = ""; m = 1; break;
 #else
 	case 0x00020001: pre = 'p'; suf = ""; break;
 	case 0x00030001: suf = ""; break;
 	case 0x00120003: suf = "A"; break;
@ -76,17 +91,16 @@ static int check_CPU (long clock, uint pvr, uint immr)
 	case 0x00200004: suf = "B"; break;
 	case 0x00300004: suf = "C"; break;
-	case 0x00310004: suf = "C1"; m = 1;
+	case 0x00310004: suf = "C1"; m = 1; break;
 		break;
 	case 0x00200064: mid = "SR"; suf = "B"; break;
 	case 0x00300065: mid = "SR"; suf = "C"; break;
 	case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
 	case 0x05010000: suf = "D3"; m = 1; break;
 	case 0x05020000: suf = "D4"; m = 1; break;
 		/* this value is not documented anywhere */
 	case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
 #endif
 	default: suf = NULL; break;
 	}
@ -101,7 +115,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
 	printf (" %u kB I-Cache", checkicache () >> 10);
 	printf (" %u kB D-Cache", checkdcache () >> 10);
-	/* lets check and see if we're running on a 860T (or P?) */
+	/* do we have a FEC (860T/P or 852/859/866)? */
 	immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
 	if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
@ -114,6 +128,12 @@ static int check_CPU (long clock, uint pvr, uint immr)
 	putc ('\n');
 #ifdef DEBUG
        if(clock != measure_gclk()) {
            printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
        }
 #endif
 	return 0;
 }
@ -316,7 +336,7 @@ int checkicache (void)
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	u32 cacheon = rd_ic_cst () & IDC_ENABLED;
-#ifdef CONFIG_IP860
+#ifdef CONFIG_IP86x
 	u32 k = memctl->memc_br1 & ~0x00007fff;	/* probe in flash memoryarea */
 #else
 	u32 k = memctl->memc_br0 & ~0x00007fff;	/* probe in flash memoryarea */
@ -363,7 +383,7 @@ int checkdcache (void)
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	u32 cacheon = rd_dc_cst () & IDC_ENABLED;
-#ifdef CONFIG_IP860
+#ifdef CONFIG_IP86x
 	u32 k = memctl->memc_br1 & ~0x00007fff;	/* probe in flash memoryarea */
 #else
 	u32 k = memctl->memc_br0 & ~0x00007fff;	/* probe in flash memoryarea */
@ -462,8 +482,20 @@ unsigned long get_tbclk (void)
 	if (immr->im_clkrst.car_sccr & SCCR_TBS) {
 		return (gd->cpu_clk / 16);
 	}
 #define PLPRCR_val(a) (((CFG_PLPRCR) & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
 #ifdef CONFIG_MPC866_et_al
        /*                   MFN
                     MFI + -------
                           MFD + 1
          factor =  -----------------
                     (PDF + 1) * 2^S
         */
-	factor = (((CFG_PLPRCR) & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT) + 1;
+	factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
                 (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
 #else
 	factor = PLPRCR_val(MF)+1;
 #endif
 	oscclk = gd->cpu_clk / factor;
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@ -145,6 +145,7 @@ void cpu_init_f (volatile immap_t * immr)
    defined(CONFIG_RPXCLASSIC)	|| \
    defined(CONFIG_RPXLITE)	|| \
    defined(CONFIG_SPD823TS)	|| \
    defined(CONFIG_MPC86xADS)	|| \
   (defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
 	memctl->memc_br0 = CFG_BR0_PRELIM;
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@ -217,7 +217,8 @@ static int fec_init(struct eth_device* dev, bd_t * bd)
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
-#if defined(CONFIG_FADS) && defined(CONFIG_MPC860T)
+#if defined(CONFIG_FADS) && \
 	( defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al) )
 	/* configure FADS for fast (FEC) ethernet, half-duplex */
 	/* The LXT970 needs about 50ms to recover from reset, so
 	 * wait for it by discovering the PHY before leaving eth_init().
--- a/cpu/mpc8xx/interrupts.c
+++ b/cpu/mpc8xx/interrupts.c
@ -334,7 +334,11 @@ void timer_interrupt (struct pt_regs *regs)
 	/* Reset Timer Expired and Timers Interrupt Status */
 	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
 	__asm__ ("nop");
 #ifdef CONFIG_MPC866_et_al
 	immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
 #else
 	immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
 #endif
 	/* Restore Decrementer Count */
 	set_dec (decrementer_count);
--- a/cpu/mpc8xx/scc.c
+++ b/cpu/mpc8xx/scc.c
@ -192,9 +192,9 @@ static int scc_init(struct eth_device* dev, bd_t *bis)
    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-#if defined(CONFIG_FADS)
+#ifdef CONFIG_FADS
-#if defined(CONFIG_MPC860T)
+#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
-    /* The FADS860T doesn't use the MODEM_EN or DATA_VOICE signals.	*/
+    /* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
    *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
    *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL;
    *((uint *) BCSR1) &= ~BCSR1_ETHEN;
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@ -68,6 +68,23 @@
 #error "console not correctly defined"
 #endif
 static void serial_setdivisor(volatile cpm8xx_t *cp)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	int divisor=gd->cpu_clk/16/gd->baudrate;
 	if(divisor/16>0x1000) {
 		/* bad divisor, assume 50Mhz clock and 9600 baud */
 		divisor=(50*1000*1000)/16/9600;
 	}
 	if(divisor<=0x1000) {
 		cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
 	} else {
 		cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
 	}
 }
 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
 /*
@ -229,8 +246,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	volatile cpm8xx_t *cp = &(im->im_cpm);
@ -242,8 +257,7 @@ serial_setbrg (void)
 	cp->cp_simode = 0x00000000;
-	cp->cp_brgc1 =
+	serial_setdivisor(cp);
 		(((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
 }
 #ifdef CONFIG_MODEM_SUPPORT
@ -506,8 +520,6 @@ int serial_init (void)
 void
 serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	volatile cpm8xx_t *cp = &(im->im_cpm);
@ -518,10 +530,8 @@ serial_setbrg (void)
 	 */
 	cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
 	/* no |= needed, since BRG1 is 000 */
-	cp->cp_brgc1 =
+	serial_setdivisor(cp);
 		(((gd->cpu_clk / 16 / gd->baudrate)-1) << 1) | CPM_BRG_EN;
 }
 void
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@ -32,7 +32,6 @@
 #define SPEED_PITC	 ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
 #define SPEED_PITC_INIT	 ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
 #if !defined(CONFIG_8xx_GCLK_FREQ)
 /* Access functions for the Machine State Register */
 static __inline__ unsigned long get_msr(void)
 {
@ -46,7 +45,6 @@ static __inline__ void set_msr(unsigned long msr)
 {
 	asm volatile("mtmsr %0" : : "r" (msr));
 }
 #endif
 /* ------------------------------------------------------------------------- */
@ -83,16 +81,20 @@ static __inline__ void set_msr(unsigned long msr)
 * CPU clock that is an even multiple of 0.1 MHz.
 */
-int get_clocks (void)
+unsigned long measure_gclk(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 #ifndef	CONFIG_8xx_GCLK_FREQ
 	volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
 	ulong timer2_val;
 	ulong msr_val;
 #ifdef CONFIG_MPC866_et_al
        /* dont use OSCM, only use EXTCLK/512 */
        immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
 #else
        immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
 #endif
 	/* Reset + Stop Timer 2, no cascading
 	 */
 	timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
@ -158,10 +160,27 @@ int get_clocks (void)
 	timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
 	immr->im_sit.sit_piscr &= ~PISCR_PTE;
-	gd->cpu_clk = ((timer2_val + 2) / 4) * 100000L;	/* convert to Hz    */
+#ifdef CONFIG_MPC866_et_al
        /* not using OSCM, using XIN, so scale appropriately */
 	return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
 #else
 	return ((timer2_val + 2) / 4) * 100000L;	/* convert to Hz    */
 #endif
 }
 /*
 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
 * or (if it is not defined) measure_gclk() (which uses the ref clock)
 * from above.
 */
 int get_clocks (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 #ifndef	CONFIG_8xx_GCLK_FREQ
 	gd->cpu_clk = measure_gclk();
 #else /* CONFIG_8xx_GCLK_FREQ */
 	/*
 	 * If for some reason measuring the gclk frequency won't
 	 * work, we return the hardwired value.
--- a/drivers/serial.c
+++ b/drivers/serial.c
@ -51,6 +51,7 @@ static int calc_divisor (void)
 		console->osc_12m_sel = OSC_12M_SEL;	/* enable 6.5 * divisor */
 		return (1);				/* return 1 for base divisor */
 	}
 	console->osc_12m_sel = 0;			/* clear if previsouly set */
 #endif
 	return (CFG_NS16550_CLK / 16 / gd->baudrate);
 }
--- a/include/common.h
+++ b/include/common.h
@ -43,6 +43,20 @@ typedef volatile unsigned char	vu_char;
 #endif
 #ifdef	CONFIG_8xx
 #include <asm/8xx_immap.h>
 #ifdef CONFIG_MPC860
 #define CONFIG_MPC86x 1
 #endif
 #ifdef CONFIG_MPC860T
 #define CONFIG_MPC86x 1
 #endif
 #if defined(CONFIG_MPC866P) || \
    defined(CONFIG_MPC866T) || \
    defined(CONFIG_MPC859T) || \
    defined(CONFIG_MPC859DSL) || \
    defined(CONFIG_MPC852T)
 #define CONFIG_MPC866_et_al 1
 #define CONFIG_MPC86x 1
 #endif
 #elif defined(CONFIG_5xx)
 #include <asm/5xx_immap.h>
 #elif defined(CONFIG_8260)
--- a/include/commproc.h
+++ b/include/commproc.h
@ -707,10 +707,10 @@ typedef struct scc_enet {
 /***  FADS860T********************************************************/
-#if defined(CONFIG_MPC860T) && defined(CONFIG_FADS)
+#if (defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al)) \
-/* This ENET stuff is for the MPC860TFADS with ethernet on SCC1.
+    && defined(CONFIG_FADS)
 /* This ENET stuff is for the MPC860TFADS/MPC8xxADS with ethernet on SCC1.
 */
 #ifdef CONFIG_SCC1_ENET
 #define	SCC_ENET	0
 #endif	/* CONFIG_SCC1_ETHERNET */
--- a/include/configs/ADS860.h
+++ b/include/configs/ADS860.h
@ -19,6 +19,7 @@
 #include <mpc8xx_irq.h>
 #define CONFIG_MPC860		1
 #define CONFIG_MPC860T		1
 #define CONFIG_ADS		1
 #define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1	    */
@ -31,10 +32,12 @@
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
 #define CFG_I2C_SLAVE		0x7F
-#define MPC8XX_XIN		32768	/* 32.768 kHz input frequency	*/
+#define CFG_8XX_XIN		32768	/* 32.768 kHz input frequency	*/
-#define MPC8XX_FACT		0x5F6	/* Multiply by 1526 */
+#define CFG_8XX_FACT		0x5F6	/* Multiply by 1526 */
 					/* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */
 #define CONFIG_8xx_GCLK_FREQ   ((CFG_8XX_XIN) * (CFG_8XX_FACT))
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 #if 0
@ -136,7 +139,7 @@
 * FLASH organization
 */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
@ -198,7 +201,7 @@
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
-#define CFG_PLPRCR  (((MPC8XX_FACT-1) << 20) |	\
+#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 /*-----------------------------------------------------------------------
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@ -23,6 +23,7 @@
 #define CFG_PCMCIA_MEM_ADDR	0xe0000000
 #define CFG_PCMCIA_MEM_SIZE	0x10000
 #define CFG_IMMR		0xFF000000
 #define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
 #define	CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE		0x02800000
 #define BCSR_ADDR		((uint) 0xff010000)
--- a/include/configs/FADS850SAR.h
+++ b/include/configs/FADS850SAR.h
@ -116,6 +116,7 @@
 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
 */
 #define	CFG_SDRAM_BASE		0x00000000
 #define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
 #define CFG_FLASH_BASE		0x02800000
 #define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 #if 0
--- a/include/configs/FADS860T.h
+++ b/include/configs/FADS860T.h
@ -32,25 +32,33 @@
 */
 #include <mpc8xx_irq.h>
-#define CONFIG_MPC860		1
+/* board type */
-#define CONFIG_MPC860T		1
+#define CONFIG_FADS		1       /* old/new FADS + new ADS */
-#define CONFIG_FADS		1
+
 /* processor type */
 #define CONFIG_MPC860T		1       /* 860T */
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600
+#define CONFIG_BAUDRATE		38400
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#if 0
+#if 0 /* old FADS */
-#define MPC8XX_FACT		10		/* Multiply by 10	*/
+# define CFG_8XX_FACT		12		/* Multiply by 12 */
-#define MPC8XX_XIN		5000000			/* 5 MHz in	*/
+# define CFG_8XX_XIN		4000000		/* 4 MHz in	*/
-#else
+#else /* new FADS */
-#define MPC8XX_FACT		12		/* Multiply by 12	*/
+# define CFG_8XX_FACT		10		/* Multiply by 10 */
-#define MPC8XX_XIN		4000000			/* 4 MHz in	*/
+# define CFG_8XX_XIN		5000000		/* 5 MHz in	*/
 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
 #endif
 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
 /* in general, we always know this for FADS+new ADS anyway */
 #define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ
 /* most vanilla kernels do not like this, set to 0 if in doubt */
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 #if 1
@ -59,8 +67,12 @@
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif
-#define CONFIG_BOOTCOMMAND	"bootm 2800100"	/* autoboot command */
+#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTARGS		""
+#define CONFIG_BOOTCOMMAND			    \
    "bootp; "				    \
    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	    \
    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
    "bootm"
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
@ -77,10 +89,10 @@
 /* choose SCC1 ethernet (10BASET on motherboard)
 * or FEC ethernet (10/100 on daughterboard)
 */
-#if 1
+#if 0
 #define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
 #undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */
-#else
+#else   /* all 86x cores have FECs, if in doubt, use it */
 #undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
 #define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
 #define CFG_DISCOVER_PHY
@ -107,7 +119,11 @@
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
 #if (CFG_SDRAM_SIZE)
 #define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
 #else
 #define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
 #endif
 #define CFG_LOAD_ADDR	 	0x00100000
@ -120,7 +136,7 @@
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
-/*-----------------------------------------------------------------------
+/*----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
 #define CFG_IMMR			0xFF000000
@ -141,6 +157,11 @@
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
 #define	CFG_SDRAM_BASE		0x00000000
 #ifdef CONFIG_FADS
 # define	CFG_SDRAM_SIZE	0x00400000      /* 4 meg */
 #else   /* !CONFIG_FADS */ /* old ADS */
 # define	CFG_SDRAM_SIZE	0x00000000      /* NO SDRAM */
 #endif
 #define CFG_FLASH_BASE		0x02800000
@ -218,7 +239,7 @@
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
-#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+#define CFG_PLPRCR	(((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 /*-----------------------------------------------------------------------
@ -235,7 +256,7 @@
 *-----------------------------------------------------------------------
 *
 */
-#define CFG_DER		0
+#define CFG_DER		 0
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
@ -280,36 +301,6 @@
 #define CFG_OR1_PRELIM	0xffff8110		/* 64Kbyte address space */
 #define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
 /*
 * Memory Periodic Timer Prescaler
 */
 /* periodic timer for refresh */
 #define CFG_MAMR_PTA		97	/* start with divider for 100 MHz	*/
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
 #define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
 #define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
 #define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
 /*
 * MAMR settings for SDRAM
 */
 /* 8 column SDRAM */
 #define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 /* 9 column SDRAM */
 #define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 #define CFG_MAMR		0x13a01114
 /*
 * Internal Definitions
 *
@ -425,7 +416,7 @@
 #endif /* CONFIG_MPC850 */
 #define CONFIG_DRAM_50MHZ		1
-#define CONFIG_SDRAM_50MHZ
+#define CONFIG_SDRAM_50MHZ              1
 #ifdef CONFIG_MPC860T
--- a/include/configs/IAD210.h
+++ b/include/configs/IAD210.h
@ -354,7 +354,7 @@
 */
 #define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
-			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLB_A11 |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_8X)
--- a/include/configs/IVML24.h
+++ b/include/configs/IVML24.h
@ -424,7 +424,7 @@
 */
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB	204
+#define CFG_MBMR_PTB	204
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
@ -448,19 +448,19 @@
 #if defined (CONFIG_IVML24_16M)
 /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
- 			 MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |	\
+ 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
- 			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+ 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVML24_32M)
 /* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVML24_64M)
 /* 128 MBit SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #endif
 /*
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@ -408,7 +408,7 @@
 */
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB	204
+#define CFG_MBMR_PTB	204
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
@ -431,19 +431,19 @@
 #if defined (CONFIG_IVMS8_16M)
 /* 8 column SDRAM */
-# define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
- 			 MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |	\
+ 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
- 			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+ 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_32M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_64M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |	\
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 #endif
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@ -9,7 +9,8 @@
 *
 * (C) Copyright 2003 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII.
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
 * Ported to PQ2FADS-ZU board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
@ -41,6 +42,15 @@
 #define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_MPC8260ADS	1	/* ...on motorola ads board */
 /* ADS flavours */
 #define CFG_8260ADS		1	/* MPC8260ADS */
 #define CFG_8266ADS		2	/* MPC8266ADS */
 #define CFG_PQ2FADS		3	/* PQ2FADS-ZU */
 #ifndef CONFIG_ADSTYPE
 #define CONFIG_ADSTYPE		CFG_8260ADS
 #endif /* CONFIG_ADSTYPE */
 #define CONFIG_BOARD_PRE_INIT	1	/* Call board_pre_init	*/
 /* allow serial and ethaddr to be overwritten */
@ -116,7 +126,9 @@
 #endif /* CONFIG_ETHER_ON_FCC */
-/* other options */
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
 #undef CONFIG_SPD_EEPROM	/* On PQ2FADS-ZU, SDRAM is soldered  */
 #else
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
@ -124,18 +136,23 @@
 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 #define CONFIG_SPD_ADDR         0x50
 #endif
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 #ifndef CONFIG_SDRAM_PBI
 #define CONFIG_SDRAM_PBI        1 /* By default, use page-based interleaving */
 #endif
 #ifndef CONFIG_8260_CLKIN
 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 #define CONFIG_8260_CLKIN	100000000	/* in Hz */
 #else
 #define CONFIG_8260_CLKIN	66666666	/* in Hz */
 #endif
 #endif
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+#define CFG_EXCLUDE		 CFG_CMD_BEDBUG | \
 				 CFG_CMD_BEDBUG | \
 				 CFG_CMD_BMP	| \
 				 CFG_CMD_BSP	| \
 				 CFG_CMD_DATE	| \
@ -143,11 +160,11 @@
 				 CFG_CMD_DTT	| \
 				 CFG_CMD_EEPROM | \
 				 CFG_CMD_ELF    | \
 				 CFG_CMD_FAT    | \
 				 CFG_CMD_FDC	| \
 				 CFG_CMD_FDOS	| \
 				 CFG_CMD_HWFLOW	| \
 				 CFG_CMD_IDE	| \
 				 CFG_CMD_JFFS2	| \
 				 CFG_CMD_KGDB	| \
 				 CFG_CMD_MMC	| \
 				 CFG_CMD_NAND	| \
@ -155,8 +172,18 @@
 				 CFG_CMD_PCMCIA | \
 				 CFG_CMD_SCSI	| \
 				 CFG_CMD_SPI	| \
-				 CFG_CMD_VFD	| \
+				 CFG_CMD_USB	| \
-				 CFG_CMD_USB	) )
+				 CFG_CMD_VFD
 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 #define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
 				 CFG_CMD_SDRAM	| \
 				 CFG_CMD_I2C	| \
 				 CFG_EXCLUDE	) )
 #else
 #define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
 				 CFG_EXCLUDE	) )
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@ -200,7 +227,6 @@
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 #define CFG_FLASH_BASE		0xff800000
 #define FLASH_BASE		0xff800000
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
 #define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
 #define CFG_FLASH_SIZE		8
@ -219,14 +245,16 @@
 #define CFG_DEFAULT_IMMR	0x0F010000
 #define CFG_IMMR		0xF0000000
-#define CFG_BCSR		0x04500000
+#define CFG_BCSR		0xF4500000
 #define CFG_SDRAM_BASE		0x00000000
-#define CFG_LSDRAM_BASE		0x04000000
+#define CFG_LSDRAM_BASE		0xD0000000
 #define RS232EN_1		0x02000002
 #define RS232EN_2		0x01000001
-#define FETHIEN			0x08000008
+#define FETHIEN1		0x08000008
-#define FETH_RST		0x04000004
+#define FETH1_RST		0x04000004
 #define FETHIEN2		0x01000000
 #define FETH2_RST		0x08000000
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
 #define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
@ -288,19 +316,30 @@
 #define CFG_SYPCR		0xFFFFFFC3
 #define CFG_BCR			0x100C0000
 #define CFG_SIUMCR		0x0A200000
-#define CFG_SCCR		0x00000000
+#define CFG_SCCR		SCCR_DFBRG01
-#define CFG_BR0_PRELIM		0xFF801801
+#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
-#define CFG_OR0_PRELIM		0xFF800836
+#define CFG_OR0_PRELIM		0xFF800876
-#define CFG_BR1_PRELIM		0x04501801
+#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
 #define CFG_OR1_PRELIM		0xFFFF8010
-#define CFG_RMR			0
+#define CFG_RMR			RMR_CSRE
 #define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 #define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
 #define CFG_RCCR		0
 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 #define CFG_PSDMR		0x824B36A3
 #define CFG_PSRT		0x13
 #define CFG_LSDMR		0x828737A3
 #define CFG_LSRT		0x13
 #define CFG_MPTPR		0x2800
 #else
 #define CFG_PSDMR		0x016EB452
-#define CFG_MPTPR		0x00001900
+#define CFG_PSRT		0x21
-#define CFG_PSRT		0x00000021
+#define CFG_LSDMR		0x0086A522
 #define CFG_LSRT		0x21
 #define CFG_MPTPR		0x1900
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 #define CFG_RESET_ADDRESS	0x04400000
--- a/include/configs/MPC86xADS.h
+++ b/include/configs/MPC86xADS.h
@ -0,0 +1,438 @@
 /*
  * A collection of structures, addresses, and values associated with
  * the Motorola MPC8xxADS board.  Copied from the FADS config.
  *
  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
  */
 /*
 * 1999-nov-26: The FADS is using the following physical memorymap:
 *
 * ff020000 -> ff02ffff : pcmcia
 * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
 * ff000000 -> ff00ffff : IMAP       internal in the cpu
 * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
 */
 /* ------------------------------------------------------------------------- */
 /*
 * board/config.h - configuration options, board specific
 */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
 * High Level Configuration Options
 * (easy to change)
 */
 #include <mpc8xx_irq.h>
 /* board type */
 #define CONFIG_MPC86xADS        1       /* new ADS */
 #define CONFIG_FADS		1       /* We are FADS compatible (more or less) */
 /* new 86xADS only - pick one of these */
 #define CONFIG_MPC866T 		1
 #undef CONFIG_MPC866P
 #undef CONFIG_MPC859T
 #undef CONFIG_MPC859DSL
 #undef CONFIG_MPC852T
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		38400
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #ifdef CONFIG_MPC86xADS
 # define CFG_8XX_FACT		5		/* Multiply by 5	*/
 # define CFG_8XX_XIN		10000000	/* 10 MHz in	*/
 #else /* ! CONFIG_MPC86xADS */
 # if 0 /* old FADS */
 #  define CFG_8XX_FACT		12		/* Multiply by 12 */
 #  define CFG_8XX_XIN		4000000		/* 4 MHz in	*/
 # else /* new FADS */
 #  define CFG_8XX_FACT		10		/* Multiply by 10 */
 #  define CFG_8XX_XIN		5000000		/* 5 MHz in	*/
 # endif
 #endif /* ! CONFIG_MPC86xADS */
 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
 /* in general, we always know this for FADS+new ADS anyway */
 #define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ
 /* most vanilla kernels do not like this, set to 0 if in doubt */
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 #if 1
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
 #else
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND			    \
    "bootp; "				    \
    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	    \
    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
    "bootm"
 /* #include "local.h" */
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 /* ATA / IDE and partition support */
 #define CONFIG_MAC_PARTITION    1
 #define CONFIG_DOS_PARTITION    1
 #define CONFIG_ISO_PARTITION	1
 #undef	CONFIG_ATAPI
 #define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
 #undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 /* choose SCC1 ethernet (10BASET on motherboard)
 * or FEC ethernet (10/100 on daughterboard)
 */
 #if 0
 #define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
 #undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */
 #else   /* all 86x cores have FECs, if in doubt, use it */
 #undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
 #define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
 #define CFG_DISCOVER_PHY
 #endif
 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 #endif
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 /*
 * Miscellaneous configurable options
 */
 #undef	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define	CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
 #if (CFG_SDRAM_SIZE)
 #define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
 #else
 #define CFG_MEMTEST_END		0x0400000     	/* 1 ... 4 MB in DRAM	*/
 #endif
 #define CFG_LOAD_ADDR	 	0x00100000
 #define	CFG_HZ		        1000		/* decr freq: 1 ms ticks */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 /*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
 /*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
 #define CFG_IMMR		0xFF000000
 #define CFG_IMMR_SIZE		((uint)(64 * 1024))
 /*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
 #define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
 #define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 /*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
 #define	CFG_SDRAM_BASE		0x00000000
 #ifdef CONFIG_FADS
 # ifdef CONFIG_MPC86xADS /* new ADS */
 #  define	CFG_SDRAM_SIZE	0x00800000      /* 8 meg */
 # else                   /* old/new FADS */
 #  define	CFG_SDRAM_SIZE	0x00400000      /* 4 meg */
 # endif
 #else   /* !CONFIG_FADS */ /* old ADS */
 # define	CFG_SDRAM_SIZE	0x00000000      /* NO SDRAM */
 #endif
 #define CFG_FLASH_BASE		0x02800000
 #define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
 #define	CFG_MONITOR_LEN		(272 << 10)	/* Reserve 272 kB for Monitor	*/
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
 #define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
 /*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
 #define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 /*-----------------------------------------------------------------------
 * FLASH organization
 */
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 #define	CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_OFFSET		0x00040000
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 #define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
 /*-----------------------------------------------------------------------
 * Cache Configuration
 */
 #define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 /*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
 #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 /*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration					11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
 #define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 /*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
 #define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 /*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
 #define CFG_PISCR	(PISCR_PS | PISCR_PITF)
 /*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
 #define CFG_PLPRCR	((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
 				PLPRCR_SPLSS | PLPRCR_TEXPS)
 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
 #define SCCR_MASK	SCCR_EBDF11
 #define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
 #define CFG_DER		 0
 /* Because of the way the 860 starts up and assigns CS0 the
 * entire address space, we have to set the memory controller
 * differently.  Normally, you write the option register
 * first, and then enable the chip select by writing the
 * base register.  For CS0, you must write the base register
 * first, followed by the option register.
 */
 /*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
 /* the other CS:s are determined by looking at parameters in BCSRx */
 #define BCSR_ADDR		((uint) 0xFF010000)
 #define BCSR_SIZE		((uint)(64 * 1024))
 #define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
 #define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
 #define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #ifdef USE_REAL_FLASH_VALUES
 /*
 * The "default" behaviour with 1Mbyte initial doesn't work for us!
 */
 #define CFG_OR0_PRELIM	0x0FFC00D34 /* Real values for the board */
 #define CFG_BR0_PRELIM	0x02800001  /* Real values for the board */
 #else
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
 #define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
 #endif
 /* BCSRx - Board Control and Status Registers */
 #define CFG_OR1_REMAP	CFG_OR0_REMAP
 #define CFG_OR1_PRELIM	0xffff8110		/* 64Kbyte address space */
 #define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
 /*
 * Internal Definitions
 *
 * Boot Flags
 */
 #define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 /* values according to the manual */
 #define PCMCIA_MEM_ADDR		((uint)0xff020000)
 #define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
 #define	BCSR0			((uint) (BCSR_ADDR + 00))
 #define	BCSR1			((uint) (BCSR_ADDR + 0x04))
 #define	BCSR2			((uint) (BCSR_ADDR + 0x08))
 #define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
 #define	BCSR4			((uint) (BCSR_ADDR + 0x10))
 /* FADS bitvalues by Helmut Buchsbaum
 * see MPC8xxADS User's Manual for a proper description
 * of the following structures
 */
 #define BCSR0_ERB       ((uint)0x80000000)
 #define BCSR0_IP        ((uint)0x40000000)
 #define BCSR0_BDIS      ((uint)0x10000000)
 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 #define BCSR1_ETHEN              ((uint)0x20000000)
 #define BCSR1_IRDEN              ((uint)0x10000000)
 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 #define BCSR1_PCCEN              ((uint)0x00800000)
 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 #define BCSR2_DRAM_PD_SHIFT      (23)
 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 #define BCSR3_BREVNR0            ((ushort)0x0080)
 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 #define BCSR3_BREVN1             ((ushort)0x0008)
 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 #define BCSR4_TFPLDL             ((uint)0x40000000)
 #define BCSR4_TPSQEL             ((uint)0x20000000)
 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 #define BCSR4_FETH_EN            ((uint)0x08000000)
 #define BCSR4_FETHCFG0           ((uint)0x04000000)
 #define BCSR4_FETHFDE            ((uint)0x02000000)
 #define BCSR4_FETHCFG1           ((uint)0x00400000)
 #define BCSR4_FETHRST            ((uint)0x00200000)
 #define CONFIG_DRAM_50MHZ		1
 #define CONFIG_SDRAM_50MHZ              1
 /* Interrupt level assignments.
 */
 #define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
 /* We don't use the 8259.
 */
 #define NR_8259_INTS	0
 /* Machine type
 */
 #define _MACH_8xx (_MACH_fads)
 #define CONFIG_DISK_SPINUP_TIME 1000000
 /* PCMCIA configuration */
 #define PCMCIA_MAX_SLOTS    2
 #ifdef CONFIG_MPC860
 #define PCMCIA_SLOT_A 1
 #endif
 /*#define CFG_PCMCIA_MEM_SIZE     ( 64 << 20) */
 #define CFG_PCMCIA_MEM_ADDR	(0x50000000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_DMA_ADDR	(0x54000000)
 #define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_ATTRB_ADDR	(0x58000000)
 #define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_IO_ADDR	(0x5C000000)
 #define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
 /* we have 8 windows, we take everything up to 60000000 */
 #define CFG_ATA_IDE0_OFFSET	0x0000
 #define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
 /* Offset for data I/O			*/
 #define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
 /* Offset for normal register accesses	*/
 #define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 /* Offset for alternate registers	*/
 #define CFG_ATA_ALT_OFFSET	0x0000
 /*#define CFG_ATA_ALT_OFFSET	0x0100 */
 #endif	/* __CONFIG_H */
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@ -331,8 +331,7 @@
 *
 */
 /* #define	CFG_DER	0x2002000F */
-/* #define CFG_DER	0 */
+#define CFG_DER	0
 #define	CFG_DER	0x0082000F
 /*
 * Init Memory Controller:
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@ -381,7 +381,7 @@
 */
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB	204
+#define CFG_MBMR_PTB	204
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
 #define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
@ -396,9 +396,9 @@
 */
 /* 8 column SDRAM */
-#define CFG_MBMR_8COL	((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
-			 MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |	\
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
-			 MAMR_RLFB_1X	 | MAMR_WLFB_1X	   | MAMR_TLFB_4X)
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
 /*
 * Internal Definitions
--- a/include/configs/pcu_e.h
+++ b/include/configs/pcu_e.h
@ -518,11 +518,11 @@
 #define CFG_MAMR_PTA	0x30	/* = 48 */
 #define CFG_MAMR	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
-			  MAMR_AMB_TYPE_1	| \
+			  MAMR_AMA_TYPE_1	| \
-			  MAMR_G0CLB_A10	| \
+			  MAMR_G0CLA_A10	| \
-			  MAMR_RLFB_1X		| \
+			  MAMR_RLFA_1X		| \
-			  MAMR_WLFB_1X		| \
+			  MAMR_WLFA_1X		| \
-			  MAMR_TLFB_8X		)
+			  MAMR_TLFA_8X		)
 /*
 * Internal Definitions
--- a/include/configs/v37.h
+++ b/include/configs/v37.h
@ -296,8 +296,7 @@
 *-----------------------------------------------------------------------
 *
 */
-#define	CFG_DER	0x0082000F
+#define CFG_DER	0
 /*#define CFG_DER	0*/
 /*
 * Init Memory Controller:
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@ -12,7 +12,7 @@
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
@ -121,8 +121,8 @@
 * RSR - Reset Status Register						 5-4
 */
 #define RSR_JTRS	0x01000000	/* JTAG Reset Status		*/
-#define RSR_DBSRS	0x02000000	/* Debug Port Soft Reset Status	*/
+#define RSR_DBSRS	0x02000000	/* Debug Port Soft Reset Status */
-#define RSR_DBHRS	0x04000000	/* Debug Port Hard Reset Status	*/
+#define RSR_DBHRS	0x04000000	/* Debug Port Hard Reset Status */
 #define RSR_CSRS	0x08000000	/* Check Stop Reset Status	*/
 #define RSR_SWRS	0x10000000	/* Software Watchdog Reset Status*/
 #define RSR_LLRS	0x20000000	/* Loss-of-Lock Reset Status	*/
@ -134,21 +134,42 @@
 /*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
 */
-#define PLPRCR_MF_MSK	0xFFF00000	/* Multiplication factor bits		*/
+#ifdef CONFIG_MPC866_et_al
 #define PLPRCR_MF_MSK	0xffff0000	/* Multiplication factor bits		*/
 #define PLPRCR_MFN_MSK	0xf8000000	/* Multiplication factor numerator bits */
 #define PLPRCR_MFN_SHIFT 0x0000001b	/* Multiplication factor numerator shift*/
 #define PLPRCR_MFD_MSK	0x03c00000	/* Multiplication factor denominator bits */
 #define PLPRCR_MFD_SHIFT 0x00000017	/* Multiplication factor denominator shift*/
 #define PLPRCR_S_MSK	0x00300000	/* Multiplication factor integer bits */
 #define PLPRCR_S_SHIFT	0x00000014	/* Multiplication factor integer shift*/
 #define PLPRCR_MFI_MSK	0x000f0000	/* Multiplication factor integer bits */
 #define PLPRCR_MFI_SHIFT 0x00000010	/* Multiplication factor integer shift*/
 #else
 #define PLPRCR_MF_MSK	0xfff00000	/* Multiplication factor bits		*/
 #define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
 #endif
 #define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
 #define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
 #ifndef CONFIG_MPC866_et_al
 #define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/
 #endif
 #define PLPRCR_CSRC	0x00000400	/* Clock Source				*/
 #ifndef CONFIG_MPC866_et_al
 #define PLPRCR_LPM_MSK	0x00000300	/* Low Power Mode mask			*/
 #define PLPRCR_LPM_NORMAL 0x00000000	/* normal power management mode		*/
 #define PLPRCR_LPM_DOZE	  0x00000100	/* doze power management mode		*/
 #define PLPRCR_LPM_SLEEP  0x00000200	/* sleep power management mode		*/
 #define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode		*/
 #define PLPRCR_LPM_DOWN	  0x00000300	/* down power management mode		*/
 #endif
 #define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
 #define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable		*/
 #define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down			*/
 #ifdef CONFIG_MPC866_et_al
 #define PLPRCR_PDF_MSK	0x0000001e	/* Predivision Factor bits		*/
 #define PLPRCR_PDF_SHIFT 0x00000001	/* Predivision Factor shift value	*/
 #define PLPRCR_DBRMO	0x00000001	/* DPLL BRM Order bit			*/
 #endif
 /*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register			15-27
@ -261,8 +282,8 @@
 * MCR - Memory Command Register
 */
 #define MCR_OP_WRITE	0x00000000	/* WRITE command			*/
-#define MCR_OP_READ	0x40000000	/* READ  command			*/
+#define MCR_OP_READ	0x40000000	/* READ	 command			*/
-#define MCR_OP_RUN	0x80000000	/* RUN   command			*/
+#define MCR_OP_RUN	0x80000000	/* RUN	 command			*/
 #define MCR_UPM_A	0x00000000	/* Select UPM A				*/
 #define MCR_UPM_B	0x00800000	/* Select UPM B				*/
 #define MCR_MB_CS0	0x00000000	/* Use Chip Select /CS0			*/
@ -359,138 +380,138 @@
 /*-----------------------------------------------------------------------
 * Machine B Mode Register						16-13
 */
-#define MAMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
+#define MBMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
-#define MAMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
+#define MBMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
-#define MAMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
+#define MBMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
-#define MAMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
+#define MBMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
-#define MAMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
+#define MBMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
-#define MAMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
+#define MBMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
-#define MAMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
+#define MBMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
-#define MAMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
+#define MBMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
-#define MAMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
+#define MBMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
-#define MAMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
+#define MBMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
-#define MAMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
+#define MBMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
-#define MAMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
+#define MBMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
-#define MAMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
+#define MBMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
-#define MAMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
+#define MBMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
-#define MAMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
+#define MBMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
-#define MAMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
+#define MBMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
-#define MAMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
+#define MBMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
-#define MAMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
+#define MBMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
-#define MAMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
+#define MBMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
-#define MAMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
+#define MBMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
-#define MAMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
+#define MBMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
-#define MAMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MBMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
-#define MAMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MBMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
-#define MAMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
+#define MBMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
-#define MAMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
+#define MBMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
-#define MAMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
+#define MBMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
-#define MAMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
+#define MBMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
-#define MAMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
+#define MBMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
-#define MAMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
+#define MBMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
-#define MAMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
+#define MBMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
-#define MAMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
+#define MBMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
-#define MAMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
+#define MBMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
-#define MAMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
+#define MBMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
-#define MAMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
+#define MBMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
-#define MAMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
+#define MBMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
-#define MAMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MBMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
-#define MAMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MBMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
-#define MAMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MBMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
-#define MAMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MBMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
-#define MAMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MBMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
-#define MAMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
+#define MBMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
-#define MAMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
+#define MBMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
-#define MAMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
+#define MBMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
-#define MAMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
+#define MBMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
-#define MAMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
+#define MBMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
-#define MAMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
+#define MBMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
-#define MAMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times	*/
+#define MBMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times	*/
-#define MAMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times	*/
+#define MBMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times	*/
-#define MAMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times	*/
+#define MBMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times	*/
-#define MAMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
+#define MBMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
-#define MAMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
+#define MBMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
-#define MAMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
+#define MBMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
-#define MAMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MBMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
-#define MAMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MBMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
-#define MAMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MBMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
-#define MAMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MBMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
-#define MAMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MBMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
-#define MAMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
+#define MBMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
-#define MAMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
+#define MBMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
-#define MAMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
+#define MBMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
-#define MAMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
+#define MBMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
-#define MAMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
+#define MBMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
-#define MAMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
+#define MBMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
-#define MAMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
+#define MBMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
-#define MAMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
+#define MBMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
-#define MAMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
+#define MBMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
-#define MAMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
+#define MBMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
-#define MAMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
+#define MBMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
-#define MAMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
+#define MBMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
-#define MAMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MBMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
-#define MAMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MBMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
-#define MAMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MBMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
-#define MAMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MBMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
-#define MAMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MBMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
-#define MAMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
+#define MBMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
-#define MAMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
+#define MBMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
 /*-----------------------------------------------------------------------
 * Timer Global Configuration Register					18-8
 */
 #define TGCR_CAS4	0x8000		/* Cascade Timer 3 and 4	*/
 #define TGCR_FRZ4	0x4000		/* Freeze timer 4		*/
-#define TGCR_STP4	0x2000		/* Stop timer   4		*/
+#define TGCR_STP4	0x2000		/* Stop timer	4		*/
-#define TGCR_RST4	0x1000		/* Reset timer  4		*/
+#define TGCR_RST4	0x1000		/* Reset timer	4		*/
 #define TGCR_GM2	0x0800		/* Gate Mode for Pin 2		*/
 #define TGCR_FRZ3	0x0400		/* Freeze timer 3		*/
-#define TGCR_STP3	0x0200		/* Stop timer   3		*/
+#define TGCR_STP3	0x0200		/* Stop timer	3		*/
-#define TGCR_RST3	0x0100		/* Reset timer  3		*/
+#define TGCR_RST3	0x0100		/* Reset timer	3		*/
 #define TGCR_CAS2	0x0080		/* Cascade Timer 1 and 2	*/
 #define TGCR_FRZ2	0x0040		/* Freeze timer 2		*/
-#define TGCR_STP2	0x0020		/* Stop timer   2		*/
+#define TGCR_STP2	0x0020		/* Stop timer	2		*/
-#define TGCR_RST2	0x0010		/* Reset timer  2		*/
+#define TGCR_RST2	0x0010		/* Reset timer	2		*/
 #define TGCR_GM1	0x0008		/* Gate Mode for Pin 1		*/
 #define TGCR_FRZ1	0x0004		/* Freeze timer 1		*/
-#define TGCR_STP1	0x0002		/* Stop timer   1		*/
+#define TGCR_STP1	0x0002		/* Stop timer	1		*/
-#define TGCR_RST1	0x0001		/* Reset timer  1		*/
+#define TGCR_RST1	0x0001		/* Reset timer	1		*/
 /*-----------------------------------------------------------------------
 * Timer Mode Register							18-9
 */
-#define TMR_PS_MSK              0xFF00  /* Prescaler Value 			*/
+#define TMR_PS_MSK		0xFF00	/* Prescaler Value			*/
-#define TMR_PS_SHIFT                 8  /* Prescaler position			*/
+#define TMR_PS_SHIFT		     8	/* Prescaler position			*/
-#define TMR_CE_MSK              0x00C0  /* Capture Edge and Enable Interrupt	*/
+#define TMR_CE_MSK		0x00C0	/* Capture Edge and Enable Interrupt	*/
-#define TMR_CE_INTR_DIS         0x0000  /* Disable Interrupt on capture event 	*/
+#define TMR_CE_INTR_DIS		0x0000	/* Disable Interrupt on capture event	*/
-#define TMR_CE_RISING           0x0040  /* Capture on Rising TINx edge only 	*/
+#define TMR_CE_RISING		0x0040	/* Capture on Rising TINx edge only	*/
-#define TMR_CE_FALLING          0x0080  /* Capture on Falling TINx edge only 	*/
+#define TMR_CE_FALLING		0x0080	/* Capture on Falling TINx edge only	*/
-#define TMR_CE_ANY              0x00C0  /* Capture on any TINx edge 		*/
+#define TMR_CE_ANY		0x00C0	/* Capture on any TINx edge		*/
-#define TMR_OM                  0x0020  /* Output Mode 				*/
+#define TMR_OM			0x0020	/* Output Mode				*/
-#define TMR_ORI                 0x0010  /* Output Reference Interrupt Enable	*/
+#define TMR_ORI			0x0010	/* Output Reference Interrupt Enable	*/
-#define TMR_FRR                 0x0008  /* Free Run/Restart 			*/
+#define TMR_FRR			0x0008	/* Free Run/Restart			*/
-#define TMR_ICLK_MSK            0x0006  /* Timer Input Clock Source mask 	*/
+#define TMR_ICLK_MSK		0x0006	/* Timer Input Clock Source mask	*/
-#define TMR_ICLK_IN_CAS         0x0000  /* Internally cascaded input 		*/
+#define TMR_ICLK_IN_CAS		0x0000	/* Internally cascaded input		*/
-#define TMR_ICLK_IN_GEN         0x0002  /* Internal General system clock	*/
+#define TMR_ICLK_IN_GEN		0x0002	/* Internal General system clock	*/
-#define TMR_ICLK_IN_GEN_DIV16   0x0004  /* Internal General system clk div 16  	*/
+#define TMR_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16	*/
-#define TMR_ICLK_TIN_PIN        0x0006  /* TINx pin 				*/
+#define TMR_ICLK_TIN_PIN	0x0006	/* TINx pin				*/
-#define TMR_GE                  0x0001  /* Gate Enable  			*/
+#define TMR_GE			0x0001	/* Gate Enable				*/
 /*-----------------------------------------------------------------------
 * I2C Controller Registers
 */
-#define	I2MOD_REVD		0x20	/* Reverese Data			*/
+#define I2MOD_REVD		0x20	/* Reverese Data			*/
 #define I2MOD_GCD		0x10	/* General Call Disable			*/
 #define I2MOD_FLT		0x08	/* Clock Filter				*/
 #define I2MOD_PDIV32		0x00	/* Pre-Divider 32			*/
 #define I2MOD_PDIV16		0x02	/* Pre-Divider 16			*/
-#define I2MOD_PDIV8		0x04	/* Pre-Divider  8			*/
+#define I2MOD_PDIV8		0x04	/* Pre-Divider	8			*/
-#define I2MOD_PDIV4		0x06	/* Pre-Divider  4			*/
+#define I2MOD_PDIV4		0x06	/* Pre-Divider	4			*/
 #define I2MOD_EN		0x01	/* Enable				*/
-#define	I2CER_TXE		0x10	/* Tx Error				*/
+#define I2CER_TXE		0x10	/* Tx Error				*/
 #define I2CER_BSY		0x04	/* Busy Condition			*/
 #define I2CER_TXB		0x02	/* Tx Buffer Transmitted		*/
 #define I2CER_RXB		0x01	/* Rx Buffer Received			*/
@ -514,7 +535,7 @@
 /*-----------------------------------------------------------------------
 * PCMCIA Interface General Control Register				17-12
 */
-#define	PCMCIA_GCRX_CXRESET	0x00000040
+#define PCMCIA_GCRX_CXRESET	0x00000040
 #define PCMCIA_GCRX_CXOE	0x00000080
 #define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
@ -539,36 +560,36 @@
 *
 * Bank Sizes:
 */
-#define PCMCIA_BSIZE_1		0x00000000	/* Bank size:   1 Bytes	*/
+#define PCMCIA_BSIZE_1		0x00000000	/* Bank size:	1 Bytes */
-#define PCMCIA_BSIZE_2		0x08000000	/* Bank size:   2 Bytes	*/
+#define PCMCIA_BSIZE_2		0x08000000	/* Bank size:	2 Bytes */
-#define PCMCIA_BSIZE_4		0x18000000	/* Bank size:   4 Bytes	*/
+#define PCMCIA_BSIZE_4		0x18000000	/* Bank size:	4 Bytes */
-#define PCMCIA_BSIZE_8		0x10000000	/* Bank size:   8 Bytes	*/
+#define PCMCIA_BSIZE_8		0x10000000	/* Bank size:	8 Bytes */
-#define PCMCIA_BSIZE_16		0x30000000	/* Bank size:  16 Bytes	*/
+#define PCMCIA_BSIZE_16		0x30000000	/* Bank size:  16 Bytes */
-#define PCMCIA_BSIZE_32		0x38000000	/* Bank size:  32 Bytes	*/
+#define PCMCIA_BSIZE_32		0x38000000	/* Bank size:  32 Bytes */
-#define PCMCIA_BSIZE_64		0x28000000	/* Bank size:  64 Bytes	*/
+#define PCMCIA_BSIZE_64		0x28000000	/* Bank size:  64 Bytes */
-#define PCMCIA_BSIZE_128	0x20000000	/* Bank size: 128 Bytes	*/
+#define PCMCIA_BSIZE_128	0x20000000	/* Bank size: 128 Bytes */
-#define PCMCIA_BSIZE_256	0x60000000	/* Bank size: 256 Bytes	*/
+#define PCMCIA_BSIZE_256	0x60000000	/* Bank size: 256 Bytes */
-#define PCMCIA_BSIZE_512	0x68000000	/* Bank size: 512 Bytes	*/
+#define PCMCIA_BSIZE_512	0x68000000	/* Bank size: 512 Bytes */
-#define PCMCIA_BSIZE_1K		0x78000000	/* Bank size:   1 kB	*/
+#define PCMCIA_BSIZE_1K		0x78000000	/* Bank size:	1 kB	*/
-#define PCMCIA_BSIZE_2K		0x70000000	/* Bank size:   2 kB	*/
+#define PCMCIA_BSIZE_2K		0x70000000	/* Bank size:	2 kB	*/
-#define PCMCIA_BSIZE_4K		0x50000000	/* Bank size:   4 kB	*/
+#define PCMCIA_BSIZE_4K		0x50000000	/* Bank size:	4 kB	*/
-#define PCMCIA_BSIZE_8K		0x58000000	/* Bank size:   8 kB	*/
+#define PCMCIA_BSIZE_8K		0x58000000	/* Bank size:	8 kB	*/
 #define PCMCIA_BSIZE_16K	0x48000000	/* Bank size:  16 kB	*/
 #define PCMCIA_BSIZE_32K	0x40000000	/* Bank size:  32 kB	*/
 #define PCMCIA_BSIZE_64K	0xC0000000	/* Bank size:  64 kB	*/
 #define PCMCIA_BSIZE_128K	0xC8000000	/* Bank size: 128 kB	*/
 #define PCMCIA_BSIZE_256K	0xD8000000	/* Bank size: 256 kB	*/
 #define PCMCIA_BSIZE_512K	0xD0000000	/* Bank size: 512 kB	*/
-#define PCMCIA_BSIZE_1M		0xF0000000	/* Bank size:   1 MB	*/
+#define PCMCIA_BSIZE_1M		0xF0000000	/* Bank size:	1 MB	*/
-#define PCMCIA_BSIZE_2M		0xF8000000	/* Bank size:   2 MB	*/
+#define PCMCIA_BSIZE_2M		0xF8000000	/* Bank size:	2 MB	*/
-#define PCMCIA_BSIZE_4M		0xE8000000	/* Bank size:   4 MB	*/
+#define PCMCIA_BSIZE_4M		0xE8000000	/* Bank size:	4 MB	*/
-#define PCMCIA_BSIZE_8M		0xE0000000	/* Bank size:   8 MB	*/
+#define PCMCIA_BSIZE_8M		0xE0000000	/* Bank size:	8 MB	*/
 #define PCMCIA_BSIZE_16M	0xA0000000	/* Bank size:  16 MB	*/
 #define PCMCIA_BSIZE_32M	0xA8000000	/* Bank size:  32 MB	*/
 #define PCMCIA_BSIZE_64M	0xB8000000	/* Bank size:  64 MB	*/
 /* PCMCIA Timing */
-#define PCMCIA_SHT(t)	((t & 0x0F)<<16)	/* Strobe Hold  Time 	*/
+#define PCMCIA_SHT(t)	((t & 0x0F)<<16)	/* Strobe Hold	Time	*/
 #define PCMCIA_SST(t)	((t & 0x0F)<<12)	/* Strobe Setup Time	*/
 #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length	*/
@ -579,10 +600,10 @@
 /* PCMCIA Region Select */
 #define PCMCIA_PRS_MEM		0x00000000	/* Common Memory Space	*/
 #define PCMCIA_PRS_ATTR		0x00000010	/*     Attribute Space	*/
-#define PCMCIA_PRS_IO		0x00000018	/*           I/O Space	*/
+#define PCMCIA_PRS_IO		0x00000018	/*	     I/O Space	*/
-#define PCMCIA_PRS_DMA		0x00000020	/* DMA, normal transfer	*/
+#define PCMCIA_PRS_DMA		0x00000020	/* DMA, normal transfer */
 #define PCMCIA_PRS_DMA_LAST	0x00000028	/* DMA, last transactn	*/
-#define PCMCIA_PRS_CEx		0x00000030	/* A[22:23] ==> CE1,CE2	*/
+#define PCMCIA_PRS_CEx		0x00000030	/* A[22:23] ==> CE1,CE2 */
 #define PCMCIA_PSLOT_A		0x00000000	/* Slot A		*/
 #define PCMCIA_PSLOT_B		0x00000004	/* Slot B		*/
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@ -43,7 +43,7 @@
 #elif defined(CONFIG_ADS)		/* The ADS  board use SLOT_A	*/
 # define CONFIG_PCMCIA_SLOT_A
 #elif defined(CONFIG_FADS)		/* The FADS series are a mess	*/
-# if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
+# if defined(CONFIG_MPC86x || defined(CONFIG_MPC821)
 #  define CONFIG_PCMCIA_SLOT_A
 # else
 #  define CONFIG_PCMCIA_SLOT_B
--- a/include/version.h
+++ b/include/version.h
@ -24,6 +24,6 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
-#define	U_BOOT_VERSION	"U-Boot 0.4.4"
+#define	U_BOOT_VERSION	"U-Boot 0.4.5"
 #endif	/* __VERSION_H__ */
--- a/post/ether.c
+++ b/post/ether.c
@ -130,8 +130,8 @@ CPM_CR_CH_SCC4 };
 			~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 #if defined(CONFIG_FADS)
-#if defined(CONFIG_MPC860T)
+#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
-	/* The FADS860T doesn't use the MODEM_EN or DATA_VOICE signals. */
+	/* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
 	*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
 	*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
 	*((uint *) BCSR1) &= ~BCSR1_ETHEN;