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pinctrl: qcom: move ipq4019 driver from mach-ipq40xx

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Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add
it to drivers/pinctrl/qcom.

Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Caleb Connolly 2023-11-14 12:55:41 +00:00
parent 53b2c7af69
commit 24d2908e98
No known key found for this signature in database
GPG Key ID: 7930459FB9303217
7 changed files with 27 additions and 207 deletions
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1
arch/arm/Kconfig
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@ -777,6 +777,7 @@ config ARCH_IPQ40XX
select SMEM
select OF_CONTROL
select CLK_QCOM_IPQ4019
select PINCTRL_QCOM_IPQ4019
imply CMD_DM
config ARCH_KEYSTONE

8
arch/arm/mach-ipq40xx/Makefile
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@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2019 Sartura Ltd.
#
# Author: Robert Marko <robert.marko@sartura.hr>
obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-ipq4019.o

166
arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
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@ -1,166 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* TLMM driver for Qualcomm IPQ40xx
*
* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
*
* Copyright (c) 2020 Sartura Ltd.
*
* Author: Robert Marko <robert.marko@sartura.hr>
*
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <linux/bitops.h>
#include "pinctrl-snapdragon.h"
struct msm_pinctrl_priv {
phys_addr_t base;
struct msm_pinctrl_data *data;
};
#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
#define TLMM_GPIO_DISABLE BIT(9)
static const struct pinconf_param msm_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 },
};
static int msm_get_functions_count(struct udevice *dev)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
return priv->data->functions_count;
}
static int msm_get_pins_count(struct udevice *dev)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
return priv->data->pin_count;
}
static const char *msm_get_function_name(struct udevice *dev,
unsigned int selector)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
return priv->data->get_function_name(dev, selector);
}
static int msm_pinctrl_probe(struct udevice *dev)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
priv->base = devfdt_get_addr(dev);
priv->data = (struct msm_pinctrl_data *)dev->driver_data;
return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
}
static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
return priv->data->get_pin_name(dev, selector);
}
static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
unsigned int func_selector)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
priv->data->get_function_mux(func_selector) << 2);
return 0;
}
static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
unsigned int param, unsigned int argument)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
switch (param) {
case PIN_CONFIG_DRIVE_STRENGTH:
clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_DRV_STRENGTH_MASK, argument << 6);
break;
case PIN_CONFIG_BIAS_DISABLE:
clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_GPIO_PULL_MASK);
break;
case PIN_CONFIG_BIAS_PULL_UP:
clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
TLMM_GPIO_PULL_MASK, argument);
break;
default:
return 0;
}
return 0;
}
static int msm_pinctrl_bind(struct udevice *dev)
{
ofnode node = dev_ofnode(dev);
const char *name;
int ret;
ofnode_get_property(node, "gpio-controller", &ret);
if (ret < 0)
return 0;
/* Get the name of gpio node */
name = ofnode_get_name(node);
if (!name)
return -EINVAL;
/* Bind gpio node */
ret = device_bind_driver_to_node(dev, "gpio_msm",
name, node, NULL);
if (ret)
return ret;
dev_dbg(dev, "bind %s\n", name);
return 0;
}
static struct pinctrl_ops msm_pinctrl_ops = {
.get_pins_count = msm_get_pins_count,
.get_pin_name = msm_get_pin_name,
.set_state = pinctrl_generic_set_state,
.pinmux_set = msm_pinmux_set,
.pinconf_num_params = ARRAY_SIZE(msm_conf_params),
.pinconf_params = msm_conf_params,
.pinconf_set = msm_pinconf_set,
.get_functions_count = msm_get_functions_count,
.get_function_name = msm_get_function_name,
};
static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
{ }
};
U_BOOT_DRIVER(pinctrl_snapdraon) = {
.name = "pinctrl_msm",
.id = UCLASS_PINCTRL,
.of_match = msm_pinctrl_ids,
.priv_auto = sizeof(struct msm_pinctrl_priv),
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
.bind = msm_pinctrl_bind,
};

28
arch/arm/mach-ipq40xx/pinctrl-snapdragon.h
View File

@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Qualcomm Pin control
*
* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
*
*/
#ifndef _PINCTRL_SNAPDRAGON_H
#define _PINCTRL_SNAPDRAGON_H
struct msm_pinctrl_data {
int pin_count;
int functions_count;
const char *(*get_function_name)(struct udevice *dev,
unsigned int selector);
unsigned int (*get_function_mux)(unsigned int selector);
const char *(*get_pin_name)(struct udevice *dev,
unsigned int selector);
};
struct pinctrl_function {
const char *name;
int val;
};
extern struct msm_pinctrl_data ipq4019_data;
#endif

7
drivers/pinctrl/qcom/Kconfig
View File

@ -20,6 +20,13 @@ config PINCTRL_QCOM_APQ8096
Say Y here to enable support for pinctrl on the MSM8996 / APQ8096
Snapdragon 820 SoC, as well as the associated GPIO driver.
config PINCTRL_QCOM_IPQ4019
bool "Qualcomm IPQ4019 GCC"
select PINCTRL_QCOM
help
Say Y here to enable support for pinctrl on the IPQ4019 SoC,
as well as the associated GPIO driver.
config PINCTRL_QCOM_QCS404
bool "Qualcomm QCS404 GCC"
select PINCTRL_QCOM

1
drivers/pinctrl/qcom/Makefile
View File

@ -4,6 +4,7 @@
obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o

23
arch/arm/mach-ipq40xx/pinctrl-ipq4019.c → drivers/pinctrl/qcom/pinctrl-ipq4019.c
View File

@ -7,12 +7,13 @@
* Author: Robert Marko <robert.marko@sartura.hr>
*/
#include "pinctrl-snapdragon.h"
#include <common.h>
#include <dm.h>
#include "pinctrl-qcom.h"
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN];
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const struct pinctrl_function msm_pinctrl_functions[] = {
{"gpio", 0},
{"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
@ -26,7 +27,6 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
{"mdc_0", 1}, /* Only for GPIO7 */
{"mdc_1", 2}, /* Only for GPIO52 */
};
static const char *ipq4019_get_function_name(struct udevice *dev,
unsigned int selector)
{
@ -45,10 +45,23 @@ static unsigned int ipq4019_get_function_mux(unsigned int selector)
return msm_pinctrl_functions[selector].val;
}
struct msm_pinctrl_data ipq4019_data = {
static const struct msm_pinctrl_data ipq4019_data = {
.pin_count = 100,
.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
.get_function_name = ipq4019_get_function_name,
.get_function_mux = ipq4019_get_function_mux,
.get_pin_name = ipq4019_get_pin_name,
};
static const struct udevice_id msm_pinctrl_ids[] = {
{ .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
{ /* Sentinal */ }
};
U_BOOT_DRIVER(pinctrl_ipq4019) = {
.name = "pinctrl_ipq4019",
.id = UCLASS_NOP,
.of_match = msm_pinctrl_ids,
.ops = &msm_pinctrl_ops,
.bind = msm_pinctrl_bind,
};