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x86: tangier: Add initial ACPI support for PMIC device
Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS and access is going via SCU device, enumerated via PCI. For now, we add just a minimum support of PMIC device to allow enabling, e.g. USB OTG, in the OS. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
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@ -320,6 +320,93 @@ Device (PCI0)
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})
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}
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}
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Device (IPC1)
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{
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Name (_ADR, 0x00130000)
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Method (_STA, 0, NotSerialized)
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{
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Return (STA_VISIBLE)
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}
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Device (PMIC)
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{
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Name (_ADR, Zero)
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Name (_HID, "INTC100E")
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Name (_CID, "INTC100E")
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Name (_DDN, "Basin Cove PMIC")
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Name (_DEP, Package ()
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{
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IPC1
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})
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Method (_STA, 0, NotSerialized)
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{
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Return (STA_VISIBLE)
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}
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Method (_CRS, 0, Serialized)
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{
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Name (RBUF, ResourceTemplate()
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{
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/*
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* Shadow registers in SRAM for PMIC:
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* SRAM PMIC register
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* --------------------
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* 0x00- Unknown
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* 0x03 THRMIRQ (0x04)
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* 0x04 BCUIRQ (0x05)
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* 0x05 ADCIRQ (0x06)
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* 0x06 CHGRIRQ0 (0x07)
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* 0x07 CHGRIRQ1 (0x08)
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* 0x08- Unknown
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* 0x0a PBSTATUS (0x27)
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* 0x0b- Unknown
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*/
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Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010)
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Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 }
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Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 }
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Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 }
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Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 }
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Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 }
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Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 }
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Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 }
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})
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Return (RBUF)
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}
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OperationRegion (PMOP, 0x8D, Zero, 0x0100)
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Field (PMOP, DWordAcc, NoLock, Preserve)
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{
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SEL1, 32,
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SEL2, 32,
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VCCL, 32,
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VNNL, 32,
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AONL, 32,
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CNTC, 32,
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CNTN, 32,
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AONN, 32,
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CNT1, 32,
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CNT2, 32,
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CNT3, 32,
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FLEX, 32,
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PRG1, 32,
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PRG2, 32,
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PRG3, 32,
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VLDO, 32,
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}
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Name (AVBL, Zero)
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Method (_REG, 2, NotSerialized)
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{
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If ((Arg0 == 0x8D))
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{
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AVBL = Arg1
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}
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}
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}
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}
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}
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Device (FLIS)
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